KR20070071688A - A liquid crystal display device - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to prevent errors from being generated in information stored in an EEPROM(Electronically Erasable and Programmable Read Only Memory), by forming a terminal for transmitting a signal, which maintains the EEPROM in a read state, in a connector of the LCD. An LCD comprises a storage unit(244) and an interface unit(290). The storage unit stores various types of information for driving the LCD. The interface unit includes a first terminal for transmitting a write protect signal to the storage unit. The storage unit is an EEPROM. The storage unit includes first to third input pins for receiving a device address signal, a fourth input pin for receiving a ground signal, a fifth signal for receiving serial data and an address signal, and a sixth input pin for receiving a serial clock signal, a seventh signal for receiving the write protect signal, and an eighth input signal for receiving a power signal.

Description

Liquid crystal display device

1 is a view showing a conventional EEPROM

2 is a view showing a liquid crystal display device according to an embodiment of the present invention.

3 is a diagram for explaining a connection relationship between a first cable and a first connector;

FIG. 4 is a diagram illustrating a pin map of terminals embedded in the first cable of FIG. 3.

FIG. 5 is a diagram illustrating another pinmap of terminals embedded in the first cable of FIG. 4. FIG.

6 is a view for explaining an operation of a storage unit according to an external signal;

* Explanation of symbols on the main parts of the drawings

201: data printed circuit board 202: gate printed circuit board

255: data TCP 266: gate TCP

277: data drive IC 288: gate drive IC

231: first cable 221: first connector

222: second connector 223: third connector

232: second cable 244: storage unit

P1 to P8: pin 200: liquid crystal panel

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that can prevent data errors of the storage unit due to an abnormal signal.

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some of them are already used as display devices in various devices.

 Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption, and mobile type such as monitor of notebook computer. In addition, it is being developed in various ways such as a monitor of a television and a computer for receiving and displaying broadcast signals.

Such a liquid crystal display may be classified into a liquid crystal display panel displaying a video signal and a driving circuit applying a driving signal to the liquid crystal display panel from the outside.

Although not shown in the drawing, the liquid crystal display panel includes two transparent substrates (glass substrates) bonded to each other with a predetermined space and a liquid crystal layer formed between the two substrates.

 Lower gates of the two transparent substrates include a plurality of gate lines arranged at regular intervals, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate line to define a pixel region, and the respective gates A plurality of pixel electrodes formed in each pixel area having a matrix defined by a line and a data line, and formed at an intersection portion of each gate line and a data line, and are switched according to a scan signal of the gate line to switch the data of the data line. A plurality of thin film transistors for applying a signal to each pixel electrode is formed.

On the other upper substrate, a black matrix layer for blocking light in portions other than the pixel regions, a color filter layer for implementing color in each pixel region, and a common electrode for applying a common voltage are formed. do.

Therefore, when the turn-on signal is sequentially applied to the gate line, an image is displayed because the data signal is applied to the pixel electrode of the corresponding line.

The conventional liquid crystal display device configured as described above includes an EEPROM (Electronically Erasable & Programmable Read Only Memory) storing various kinds of information necessary for driving the liquid crystal display device. Extended Display Indentification Data (EDID) information stored in the EEPROM includes information such as maximum and minimum frequencies, color coordinates, and standard timing of vertical and horizontal synchronization signals indicating the resolution of the liquid crystal display.

FIG. 1 shows a conventional EEPROM. As shown in the figure, the EEPROM 101 has eight input pins P1, P2, P3, P4, P5, P6, P7, and P8.

The first to third input pins P1, P2, and P3 are pins for inputting a device address, the fourth input pin P4 is a pin for inputting a ground signal, and the fifth input pin P5. ) Is a pin for inputting serial data and an address, a sixth input pin P6 is a pin for inputting a serial clock signal, and a seventh input pin P7 is a write protect signal (or read / write signal). And an eighth input pin is a pin for inputting a power signal.

Here, when a read / write signal is input to the seventh input pin P7, the EEPROM 101 is maintained in a state where both read and write operations are possible. On the other hand, when the write protect signal is input to the seventh input pin P7, the EEPROM 101 is maintained in a state where only a read operation is possible.

The EEPROM 101 is installed in a liquid crystal display device after various information necessary for the EEPROM 101 is input. At this time, the seventh input pin P7 of the EEPROM 101 is maintained in the ground state or the floating state. As such, when the seventh input pin P7 is connected to ground or maintained in a floating state, the EEPROM 101 is maintained in a state in which both read and write operations are possible.

Meanwhile, when the liquid crystal display is in operation, an abnormal signal from the outside may be supplied to the EEPROM 101. In particular, when the signal is applied to the fifth input pin P5, the following problem occurs.

That is, since the EEPROM 101 installed in the liquid crystal display is maintained in a read and write state, an abnormal signal applied to the fifth input pin P5 may be supplied to the EEPROM 101. Accordingly, an error occurs in the information stored in the EEPROM 101.

The present invention has been made to solve the above problems, by installing a terminal for transmitting a signal for keeping the EEPROM in the read state in the connector of the liquid crystal display device to prevent the error in the information stored in the EEPROM It is an object of the present invention to provide a liquid crystal display device.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a storage unit to which various information necessary for driving a liquid crystal display device is input; And an interface unit having a first terminal for transmitting a write protect signal to the storage unit.

Here, the storage unit is characterized in that the EEPROM (Electronicaly Erasable & Programmable Read Only Memory).

The storage unit may include: first to third input pins to which a device address signal is input; A fourth input pin to which a ground signal is input; A fifth input pin to which serial data and an address signal are input; A sixth input pin to which a serial clock signal is input; A seventh input pin to which the write protect signal is input; And an eighth input pin to which the power signal is input.

The first terminal is characterized in that for transmitting a ground signal.

The first terminal may further transmit a read / write signal.

The first terminal transmits a power signal as the write protect signal; The ground signal may be transmitted as the read / write signal.

The power signal is characterized in that it has a value of 1.8 to 6.0 [V].

The connector may include a plurality of second terminals for transmitting a power signal for driving the liquid crystal display; A plurality of third terminals for transmitting image data signals; A plurality of fourth terminals for transmitting a clock signal for sampling the image data signal; A plurality of fifth terminals for transmitting ground signals; And a sixth terminal transmitting a power signal for driving the storage.

The interface unit includes a cable for transmitting various signals and power from an external system; A first connector connected to the cable; And a second connector connecting the first connector and the storage unit.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

In the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIG. 2, the gate printed circuit board 202 connected to the upper side of the liquid crystal panel 200 through a plurality of gate TCP 266 (Tape Carrier Package). And a data printed circuit board 201 connected to one side of the liquid crystal panel 200 through a plurality of data TCPs 255.

FIG. 2 is a view illustrating a rear surface of the liquid crystal panel 200, in which gate lines and data lines are arranged to cross each other, and the gate lines and data lines are vertically crossed. The pixel region is located at. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed.

Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scanning signal applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

On the other hand, a gate drive IC 288 is mounted on each of the gate TCPs 266, and each gate drive IC 288 serves to drive the gate lines of the liquid crystal panel 200. Each data TCP 255 has a data drive IC 277 mounted thereon, and each data drive IC 277 serves to drive data lines of the liquid crystal panel 200.

The data printed circuit board 201 includes a timing controller for supplying a control signal for controlling the gate drive ICs 288 and the data drive ICs 277, and various driving voltages used in the liquid crystal display. The power supply for supplying them is mounted.

The timing controller controls the driving timing of the gate drive ICs 288 and the data drive ICs 277, and supplies a pixel data signal to the data drive ICs 277.

Here, the power supply unit boosts or depresses an input power to generate driving voltages such as a common voltage VCOM, a gate high voltage signal VGH, and a gate low voltage signal VGL required by the liquid crystal display.

The gate drive ICs 288 sequentially supply scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel 200 by one line.

The data drive ICs 277 supply a pixel voltage signal to each of the data lines whenever a scanning signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, each of the gate TCP 266 and the data TCP 255 is a flexible printed circuit board, and each of the gate TCP 266 and the data TCP 255 is connected to the liquid crystal panel 200 in a TAP manner. do.

 Each data TCP 255 is supplied with control signals and DC voltages from a timing controller and a power supply unit mounted on the data printed circuit board 201 through a data printed circuit board 201.

Each of the gate TCPs 266 is connected to the data printed circuit board 201 and a second cable 232 electrically connecting the data printed circuit board 201 and the gate printed circuit board 202. In addition, control signals and direct current voltages are supplied from a timing controller and a power supply unit mounted on the data printed circuit board 201. One side of the second cable 232 is connected to the second connector 222 formed on the data printed circuit board 201, and the other side of the second cable 232 is connected to the third connector 223 formed on the gate printed circuit board 202. do.

The data printed circuit board 201 may include a first connector 221 for receiving various signals and power from an external system through a first cable 231, and the various signals and the like on the gate printed circuit board 202. A second connector 222 is provided for supplying power.

On the other hand, the data printed circuit board 201 is provided with a storage unit 244 for storing a variety of information required for driving the liquid crystal display device. The storage unit 244 is an electronically erasable & programmable read only memory (EEPROM) in which information is stored in the storage unit 244 in the Extended Display Indentification Data (EDID) method. This EDID information includes information such as maximum and minimum frequencies, color coordinates, standard timing, and the like of the vertical and horizontal synchronization signals indicating the resolution of the liquid crystal display.

The storage unit 244 has eight input pins P1, P2, P3, P4, P5, P6, P7, and P8. That is, the first to third input pins P1, P2, and P3 are pins for inputting a device address, the fourth input pin P4 is a pin for inputting a ground signal, and the fifth input pin. P5 is a pin for inputting serial data and an address, a sixth input pin P6 is a pin for inputting a serial clock signal, and a seventh input pin P7 is a write protect signal (or read / write signal). ) Is input, and the eighth input pin P8 is a pin for inputting a power signal.

Here, when the read / write signal is input to the seventh input pin P7, the storage unit 244 is maintained in a state in which both read and write operations are possible. On the other hand, when the write protect signal is input to the seventh input pin P7, the storage unit 244 remains in a state where only a read operation is possible.

The storage unit 244 is installed in the liquid crystal display device after various information necessary for the storage unit 244 is input. In this case, the seventh input pin P7 of the storage unit 244 is maintained in the ground state or the floating state. As such, when the seventh input pin P7 is connected to the ground or maintained in a floating state, the storage unit 244 is maintained in a state in which both read and write operations are possible.

Here, the interface unit 290 including the first cable 231 and the first connector 221 will be described in more detail as follows.

3 is a view for explaining a connection relationship of the interface unit of FIG.

As shown in FIG. 3, a fourth connector 224 is connected to an end of the first cable 231, and the first cable 231 is connected to the first connector (224) through the fourth connector 224. 221 is electrically connected.

To this end, the first connector 221 is provided with a plurality of terminals 301 having a plug shape, the fourth connector 224 is provided with a plurality of terminals 311 having a socket shape.

Of course, the terminals 301 formed on the first connector 221 may have a socket shape, and the terminals 311 formed on the fourth connector 224 may have a plug shape.

Although not shown in the drawings, the first cable 231 has a plurality of terminals (not shown) connected to the terminals of the fourth connector 224.

Herein, the pin map of the terminal embedded in the first cable 231 will be described.

4 is a diagram illustrating a pin map of terminals embedded in the first cable of FIG. 3.

As shown in FIG. 4, the first cable 231 has 20 terminals. Wherein the first, tenth, sixteenth, and nineteenth terminals are terminals for transmitting a ground signal; The second and third terminals are terminals for transmitting a power signal of 3.3 [V]; The fourth terminal is a terminal for transmitting a power signal of 3.3 [V], and the fifth terminal is a terminal for transmitting a test signal; A sixth terminal is a terminal for transmitting an EDID type clock signal; A seventh terminal is a terminal for transmitting serial data of an EDID method; The eighth, ninth, eleventh, twelfth, fourteenth, and fifteenth terminals are terminals for transmitting image data of a Low Voltage Differential Signal (LVDS) scheme; The seventeenth and eighteenth terminals are the terminals for transmitting the LVDS type clock signal; The 20th terminal is a terminal for transmitting a write protect signal.

Wherein power signals from the second and third terminals are supplied to the timing controller and a power supply unit; The power signal from the fourth terminal, the serial clock signal from the sixth terminal, the serial data from the seventh terminal, and the write protect signal from the twentieth terminal are supplied to the storage unit 244.

As described above, when the first cable 231 has 20 terminals, the first connector 221 and the fourth connector 224 also have 20 terminals 301 and 311 having the functions listed above.

In addition, 30 terminals may be internal to the first cable 231.

FIG. 5 is a diagram illustrating another pin map of terminals embedded in the first cable of FIG. 4.

As shown in FIG. 5, the first cable 231 has 30 terminals. Wherein the first, tenth, thirteenth, sixteenth, nineteenth, twenty-second, and twenty-fifth terminals are terminals for transmitting ground signals; The second and third terminals are terminals for transmitting a power signal of 3.3 [V]; The fourth terminal is a terminal for transmitting a power signal of 3.3 [V]; The fifth terminal is a terminal for transmitting a test signal; A sixth terminal is a terminal for transmitting an EDID type clock signal; A seventh terminal is a terminal for transmitting serial data of an EDID method; The eighth, ninth, eleventh, twelfth, fourteenth, and fifteenth terminals are terminals for transmitting LVDS-type odd image data; The seventeenth and eighteenth terminals are the terminals for transmitting an LVDS type odd clock signal; The twenty-second, twenty-first, twenty-fourth, twenty-sixth, and twenty-seventh terminals are terminals for transmitting even image data of the LVDS scheme; The twenty-ninth and thirtieth terminals are terminals for transmitting an even clock signal of the LVDS scheme; The twenty-eighth terminal is a terminal for transmitting a write protect signal.

Wherein power signals from the second and third terminals are supplied to the timing controller and a power supply unit; The power signal from the fourth terminal, the serial clock signal from the sixth terminal, the serial data from the seventh terminal, and the write protect signal from the twenty-eighth terminal are supplied to the storage unit 244.

As described above, when the first cable 231 has 30 terminals, the first connector 221 and the fourth connector 224 also have 30 terminals 301 and 311 having the functions listed above.

A method of supplying the write protect signal to the storage unit 244 through the first cable 231 configured as described above is as follows.

6 is a diagram for describing an operation of a storage unit according to an external signal.

First, the storage unit 244 into which the information is input is mounted on the data printed circuit board 201.

Thereafter, the first cable 231 is connected to the first connector 221 through the fourth connector 224, and a write protect signal is supplied to the twentieth terminal (or the twenty-eighth terminal).

Then, the write protect signal may include a twentieth terminal (or twenty eighth terminal) of the first cable 231, a twentieth terminal (or twenty eighth terminal) of the fourth connector 224, and the first connector ( It is input to the storage unit 244 through the twentieth terminal (or the twenty eighth terminal) of the 221.

In this case, the write protect signal is supplied to the storage unit 244 through the seventh input pin P7 of the storage unit 244. Accordingly, the storage unit 244 is maintained in a read state (ie, a write protect state). Here, the write protect signal may use a power signal of about 3.3 [V]. That is, when the power signal of about 3.3 [V] is supplied to the seventh input pin P7 through the first cable 231, the fourth connector 224, and the second connector 222, the storage may be performed. The unit 244 is kept in a read state.

Meanwhile, in order to maintain the storage unit 244 in a read and write state, a read / write signal may be supplied to the twentieth terminal (or the twenty eighth terminal).

This read / write signal may be a ground signal. That is, when the ground signal is supplied to the seventh input pin P7 through the first cable 231, the fourth connector 224, and the second connector 222, the storage unit 244 reads and It remains writable.

As such, when the interface unit 290 according to the present invention is used, the storage unit 244 may be maintained in a readable state (that is, a write protection state), and thus an abnormal signal from the outside may be stored in the storage unit 244. Even if applied to the information stored in the storage unit 244 can be safely maintained.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The liquid crystal display according to the present invention as described above has the following effects.

In the interface portion (first connector, fourth connector, and first cable) of the liquid crystal display according to the present invention, a transmission terminal for transmitting a signal for holding the storage portion in a read state (write protection state) is formed. Therefore, using the interface unit according to the present invention, it is possible to safely maintain the information of the storage unit.

Claims (9)

A storage unit to which various information necessary for driving the liquid crystal display device is input; And, And an interface unit having a first terminal for transmitting a light protect signal to the storage unit. The method of claim 1, And the storage unit is an electronically erasable & programmable read only memory (EEPROM). The method of claim 1, The storage unit, First to third input pins to which a device address signal is input; A fourth input pin to which a ground signal is input; A fifth input pin to which serial data and an address signal are input; A sixth input pin to which a serial clock signal is input; A seventh input pin to which the write protect signal is input; And, And an eighth input pin to which a power signal is input. The method of claim 1, And the first terminal transmits a ground signal. The method of claim 1, And the first terminal further transmits a read / write signal. The method of claim 5, The first terminal, Transmit a power signal as the write protect signal; And, And a ground signal as the read / write signal. The method of claim 6, And the power signal has a value of 1.8 to 6.0 [V]. The method of claim 1, The connector, A plurality of second terminals configured to transmit a power signal for driving the liquid crystal display; A plurality of third terminals for transmitting image data signals; A plurality of fourth terminals for transmitting a clock signal for sampling the image data signal; A plurality of fifth terminals for transmitting ground signals; And, And a sixth terminal which transmits a power signal for driving the storage unit. The method of claim 1, The interface unit, Cables for transmitting various signals and power from external systems; A first connector connected to the cable; And, And a second connector connecting the first connector and the storage unit.

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