KR20070071562A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20070071562A
KR20070071562A KR1020050135117A KR20050135117A KR20070071562A KR 20070071562 A KR20070071562 A KR 20070071562A KR 1020050135117 A KR1020050135117 A KR 1020050135117A KR 20050135117 A KR20050135117 A KR 20050135117A KR 20070071562 A KR20070071562 A KR 20070071562A
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South Korea
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gate
semiconductor substrate
region
recess
gate region
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KR1020050135117A
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Korean (ko)
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오태경
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주식회사 하이닉스반도체
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Priority to KR1020050135117A priority Critical patent/KR20070071562A/en
Publication of KR20070071562A publication Critical patent/KR20070071562A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for fabricating a semiconductor device is provided to increase the total length of a channel by simultaneously forming a step gate and a recess gate by two recess processes. A first photoresist layer pattern is formed which defines a step gate region where an impurity junction region in the upper part of a semiconductor substrate(100) protrudes. A predetermined depth of the semiconductor substrate is etched by using the first photoresist layer pattern, and the first photoresist layer pattern is removed to form a step gate region. A second photoresist layer pattern is formed on the resultant structure, defining a recess gate region. A predetermined depth of the semiconductor substrate is etched by using the second photoresist layer pattern as a mask, and the second photoresist layer pattern is removed to form the recess gate region. A predetermined thickness of a gate oxide layer(140) is formed on the resultant structure. A stack structure of a gate polysilicon layer(150), a gate metal layer(160) and a gate hard mask layer(170) is formed on the resultant structure and is etched to form a gate pattern. The recess gate region can be formed at both sides of a step gate region having a type that the impurity junction region in the upper part of the semiconductor substrate protrudes.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1 및 도 2는 종래기술에 따른 반도체 소자의 제조 방법을 도시한 단면도. 1 and 2 are cross-sectional views showing a method for manufacturing a semiconductor device according to the prior art.

도 3a 내지 도 3g는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들. 3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 두 번의 리세스 공정을 수행하여 스텝 게이트와 리세스 게이트를 동시에 형성함으로써 두 영역을 활성화 영역으로 이용하여 총 채널 길이를 증가시켜 디램 셀의 리프레쉬 특성을 향상시키는 기술을 개시한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, wherein a step gate and a recess gate are simultaneously formed by performing two recess processes to increase the total channel length by using two regions as an activation region, thereby improving refresh characteristics of the DRAM cell. Disclosed is a technique for improving.

도 1은 종래 기술에 따른 반도체 소자의 스텝 게이트 제조 방법을 도시한 단면도이다. 1 is a cross-sectional view showing a step gate manufacturing method of a semiconductor device according to the prior art.

도 1을 참조하면, 반도체 기판(10) 상부에 스텝 게이트 영역을 정의하는 감광막 패턴(미도시)을 형성하고 상기 감광막 패턴(미도시)을 마스크로 반도체 기판(10)을 소정 깊이 식각한 후 상기 감광막 패턴(미도시)을 제거하여 계단형의 스텝 게이트 영역(13)을 형성한다. Referring to FIG. 1, after forming a photoresist pattern (not shown) defining a step gate region on the semiconductor substrate 10 and etching the semiconductor substrate 10 by a predetermined depth using the photoresist pattern (not shown) as a mask. The photoresist pattern (not shown) is removed to form a stepped step gate region 13.

다음에, 스텝 게이트 영역(13)을 포함하는 반도체 기판(10) 전면에 일정 두께의 게이트 산화막(15)을 형성하고, 전체 표면 상부에 게이트 폴리실리콘층(20), 텅스텐 실리사이드층(25) 및 질화막 하드마스크층(30)의 적층구조를 형성한 후 상기 적층구조를 식각하여 스텝 게이트를 형성한다. Next, a gate oxide film 15 having a predetermined thickness is formed on the entire surface of the semiconductor substrate 10 including the step gate region 13, the gate polysilicon layer 20, the tungsten silicide layer 25, After the stack structure of the nitride film hard mask layer 30 is formed, the stack structure is etched to form a step gate.

도 2는 종래 기술에 따른 반도체 소자의 리세스 게이트 제조 방법을 도시한 단면도이다.2 is a cross-sectional view illustrating a recess gate manufacturing method of a semiconductor device according to the prior art.

도 2를 참조하면, 반도체 기판(50) 상부에 리세스 게이트 영역을 정의하는 감광막 패턴(미도시)을 형성하고 상기 감광막 패턴(미도시)을 마스크로 반도체 기판(50)을 소정 깊이 식각한 후 상기 감광막 패턴(미도시)을 제거하여 리세스 게이트 영역(53)을 형성한다. Referring to FIG. 2, a photoresist pattern (not shown) defining a recess gate region is formed on the semiconductor substrate 50, and the semiconductor substrate 50 is etched with a predetermined depth using the photoresist pattern (not shown) as a mask. The photoresist layer pattern (not shown) is removed to form a recess gate region 53.

다음에, 리세스 게이트 영역(53)을 포함하는 반도체 기판(50) 전면에 일정 두께의 게이트 산화막(55)을 형성하고, 전체 표면 상부에 게이트 폴리실리콘층(60), 텅스텐 실리사이드층(65) 및 질화막 하드마스크층(70)의 적층구조를 형성한 후 상기 적층구조를 식각하여 리세스 게이트를 형성한다. Next, a gate oxide film 55 having a predetermined thickness is formed on the entire surface of the semiconductor substrate 50 including the recess gate region 53, and the gate polysilicon layer 60 and the tungsten silicide layer 65 are formed over the entire surface. And forming a stack structure of the nitride film hard mask layer 70 and etching the stack structure to form a recess gate.

상술한 종래 기술에 따른 반도체 소자의 제조 방법에서, 반도체 소자의 집적도를 높이기 위해 셀 트랜지스터의 크기가 감소되면서 숏채널(Short Channel) 효과로 인해 디램 셀 트랜지스터의 성능 및 리프레쉬 특성이 악화되는 문제점이 있다. In the above-described method of manufacturing a semiconductor device, there is a problem in that the performance and refresh characteristics of a DRAM cell transistor are deteriorated due to a short channel effect as the size of the cell transistor is reduced to increase the degree of integration of the semiconductor device. .

상기 문제점을 해결하기 위하여, 두 번의 리세스 공정을 수행하여 스텝 게이트와 리세스 게이트를 동시에 형성함으로써 두 영역을 활성화 영역으로 이용하여 총 채널 길이를 증가시켜 디램 셀의 리프레쉬 특성을 향상시키는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다. In order to solve the above problems, a semiconductor device that improves the refresh characteristics of a DRAM cell by increasing the total channel length by using two regions as an activation region by simultaneously forming a step gate and a recess gate by performing two recess processes. It is an object to provide a manufacturing method.

본 발명에 따른 반도체 소자의 제조 방법은 Method for manufacturing a semiconductor device according to the present invention

반도체 기판 상부의 불순물 접합 영역을 돌출시키는 형태의 스텝 게이트 영역을 정의하는 제 1 감광막 패턴을 형성하는 단계와,Forming a first photoresist film pattern defining a step gate region in which an impurity junction region protrudes over the semiconductor substrate;

상기 제 1 감광막 패턴을 마스크로 소정 깊이의 반도체 기판을 식각한 후 상기 제 1 감광막 패턴을 제거하여 스텝 게이트 영역을 형성하는 단계와,Etching the semiconductor substrate having a predetermined depth using the first photoresist pattern as a mask, and then removing the first photoresist pattern to form a step gate region;

상기 반도체 기판 상부에 리세스 게이트 영역을 정의하는 제 2 감광막 패턴을 형성하는 단계와,Forming a second photoresist layer pattern defining a recess gate region on the semiconductor substrate;

상기 제 2 감광막 패턴을 마스크로 상기 반도체 기판을 소정 깊이 식각한 후 제 2 감광막 패턴을 제거하여 리세스 게이트 영역을 형성하는 단계와,Etching the semiconductor substrate using the second photoresist pattern as a mask for a predetermined depth, and then removing the second photoresist pattern to form a recess gate region;

상기 스텝 게이트 영역 및 리세스 게이트 영역을 포함한 반도체 기판 전면에 일정 두께의 게이트 산화막을 형성하는 단계와,Forming a gate oxide film having a predetermined thickness on an entire surface of the semiconductor substrate including the step gate region and the recess gate region;

전체 표면 상부에 게이트 폴리실리콘층, 게이트 금속층 및 게이트 하드마스크층의 적층구조를 형성하고, 상기 적층구조를 식각하여 게이트 패턴을 형성하는 단계Forming a stacked structure of a gate polysilicon layer, a gate metal layer, and a gate hard mask layer on the entire surface, and etching the stacked structure to form a gate pattern

를 포함하는 것을 특징으로 한다. Characterized in that it comprises a.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 3a 내지 도 3g는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들이다.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 3a를 참조하면, 반도체 기판(100) 상부의 불순물 접합 영역을 돌출시키는 형태의 스텝 게이트 (Step Gate) 영역을 정의하는 제 1 감광막 패턴(110)을 형성한다.Referring to FIG. 3A, a first photoresist layer pattern 110 defining a step gate region protruding from an impurity junction region on the semiconductor substrate 100 is formed.

도 3b를 참조하면, 제 1 감광막 패턴(110)을 마스크로 반도체 기판(100)을 소정 깊이 식각한 후 제 1 감광막 패턴(110)을 제거하여 스텝 게이트 영역(115)를 형성한다. Referring to FIG. 3B, the semiconductor substrate 100 is etched to a predetermined depth using the first photoresist pattern 110 as a mask, and then the first photoresist pattern 110 is removed to form the step gate region 115.

도 3c를 참조하면, 반도체 기판(100) 상부에 리세스 게이트 (Recess Gate) 영역을 정의하는 제 2 감광막 패턴(120)을 형성한다. Referring to FIG. 3C, a second photoresist layer pattern 120 defining a recess gate region is formed on the semiconductor substrate 100.

여기서, 리세스 게이트 영역은 스텝 게이트 영역의 양측에 형성되도록 하는 것이 바람직하다. Here, the recess gate region is preferably formed on both sides of the step gate region.

도 3d를 참조하면, 제 2 감광막 패턴(120)을 마스크로 반도체 기판(100)을 소정 깊이 식각하여 리세스 게이트 영역(130)을 형성한다. Referring to FIG. 3D, the recess gate region 130 is formed by etching the semiconductor substrate 100 by a predetermined depth using the second photoresist pattern 120 as a mask.

도 3e를 참조하면, 스텝 게이트 영역(115) 및 리세스 게이트 영역(130)을 포함한 반도체 기판(100) 전면에 일정 두께의 게이트 산화막(140)을 형성한다.Referring to FIG. 3E, a gate oxide layer 140 having a predetermined thickness is formed on the entire surface of the semiconductor substrate 100 including the step gate region 115 and the recess gate region 130.

도 3f 및 도 3g를 참조하면, 전체 표면 상부에 게이트 폴리실리콘층(150), 게이트 금속층(160) 및 게이트 하드마스크층(170)의 적층구조를 형성한다. 3F and 3G, a stacked structure of the gate polysilicon layer 150, the gate metal layer 160, and the gate hard mask layer 170 is formed on the entire surface.

여기서, 게이트 금속층(160)은 텅스텐 실리사이드층으로 형성하고, 게이트 하드마스크층(170)은 질화막으로 형성한다. Here, the gate metal layer 160 is formed of a tungsten silicide layer, and the gate hard mask layer 170 is formed of a nitride film.

다음에, 상기 적층구조의 상부에 게이트 영역을 정의하는 제 3 감광막 패턴(180)을 형성한다. 제 3 감광막 패턴(180)을 마스크로 상기 적층구조를 식각한 후 제 3 감광막 패턴(180)을 제거하여 게이트 패턴을 형성한다.Next, a third photoresist pattern 180 defining a gate region is formed on the stacked structure. After etching the stack structure using the third photoresist pattern 180 as a mask, the third photoresist pattern 180 is removed to form a gate pattern.

본 발명에 따른 반도체 소자의 제조 방법은 두 번의 리세스 공정을 수행하여 스텝 게이트와 리세스 게이트를 동시에 형성함으로써 두 영역을 활성화 영역으로 이용하여 총 채널 길이를 증가시켜 디램 셀의 리프레쉬 특성을 향상시키는 효과가 있다. In the method of manufacturing a semiconductor device according to the present invention, a step gate and a recess gate are simultaneously formed by performing two recess processes to increase the total channel length by using two regions as an activation region, thereby improving refresh characteristics of the DRAM cell. It works.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (4)

반도체 기판 상부의 불순물 접합 영역을 돌출시키는 형태의 스텝 게이트 영역을 정의하는 제 1 감광막 패턴을 형성하는 단계;Forming a first photoresist layer pattern defining a step gate region protruding from the impurity junction region on the semiconductor substrate; 상기 제 1 감광막 패턴을 마스크로 소정 깊이의 반도체 기판을 식각하고 상기 제 1 감광막 패턴을 제거하여 스텝 게이트 영역을 형성하는 단계;Etching the semiconductor substrate having a predetermined depth using the first photoresist pattern as a mask and removing the first photoresist pattern to form a step gate region; 상기 반도체 기판 상부에 리세스 게이트 영역을 정의하는 제 2 감광막 패턴을 형성하는 단계;Forming a second photoresist pattern defining a recess gate region on the semiconductor substrate; 상기 제 2 감광막 패턴을 마스크로 상기 반도체 기판을 소정 깊이 식각한 후 제 2 감광막 패턴을 제거하여 리세스 게이트 영역을 형성하는 단계;Etching the semiconductor substrate by a predetermined depth using the second photoresist pattern as a mask, and then removing the second photoresist pattern to form a recess gate region; 상기 스텝 게이트 영역 및 리세스 게이트 영역을 포함한 반도체 기판 전면에 일정 두께의 게이트 산화막을 형성하는 단계; 및Forming a gate oxide film having a predetermined thickness on an entire surface of the semiconductor substrate including the step gate region and the recess gate region; And 전체 표면 상부에 게이트 폴리실리콘층, 게이트 금속층 및 게이트 하드마스크층의 적층구조를 형성하고, 상기 적층구조를 식각하여 게이트 패턴을 형성하는 단계;Forming a stacked structure of a gate polysilicon layer, a gate metal layer, and a gate hard mask layer on an entire surface of the entire surface, and etching the stacked structure to form a gate pattern; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 리세스 게이트 영역은 반도체 기판 상부의 불순물 접합 영역을 돌출시키는 형태의 스텝 게이트 영역의 양측에 형성되는 것을 특징으로 하는 반도체 소자 의 제조 방법. And the recess gate regions are formed at both sides of the step gate region protruding from the impurity junction region on the semiconductor substrate. 제 1 항에 있어서, The method of claim 1, 상기 게이트 금속층은 텅스텐 실리사이드로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. And the gate metal layer is formed of tungsten silicide. 제 1 항에 있어서, The method of claim 1, 상기 게이트 하드마스크층은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. And the gate hard mask layer is formed of a nitride film.
KR1020050135117A 2005-12-30 2005-12-30 Method for manufacturing semiconductor device KR20070071562A (en)

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