KR20070068878A - Methods of fabricating a semiconductor devices employing a low-k dielectric layer as a pre-metal dielectric layer and semiconductor devices fabricated thereby - Google Patents

Abstract

A method for fabricating a semiconductor device and a semiconductor device fabricated by the same are provided to decrease the parasitic capacitance between gate patterns by improving thermal stability of a low-k dielectric layer. Wiring patterns are formed between a semiconductor substrate and an interlayer dielectric in such a way that each of the wiring patterns has a conductive wiring. A low-k dielectric layer(67) is formed to cover the wiring patterns and the semiconductor substrate, in which the low-k dielectric layer is made of an insulation layer having dielectric constant lower than a silicon oxide layer. A capping layer(71) is formed on the low-k dielectric layer to block oxygen and/or moisture.

Description

Methods of fabricating a semiconductor devices employing a low-k dielectric layer as a pre-metal dielectric layer and semiconductor devices fabricated }

1 is a cross-sectional view illustrating a conventional method of manufacturing a semiconductor device.

2 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device and a semiconductor device manufactured thereby according to an embodiment of the present invention.

FIG. 5 is a graph illustrating a change in characteristics of a low dielectric film employed as a pre-metal dielctric layer of a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to methods of manufacturing semiconductor devices and semiconductor devices manufactured thereby, and more particularly, to methods of manufacturing semiconductor devices employing a low dielectric film as an insulating film before a metal process and semiconductor devices manufactured thereby.

As the degree of integration of semiconductor devices increases, the spacing between wirings becomes narrower. The regions between the wirings are filled with an insulating film, that is, an interlayer insulating film. Accordingly, electrical signals applied to the wirings are delayed due to the dielectric constant of the interlayer insulating film. In order to improve the operating speed of the semiconductor device, the interlayer insulating film must have a low dielectric constant.

A silicon oxide film is widely used as the interlayer insulating film. The silicon oxide film has a dielectric constant of about 3.9. However, when the interlayer insulating film is formed of the silicon oxide film, there may be a limit in improving the operating speed of the highly integrated semiconductor device. Therefore, in order to manufacture a high performance semiconductor device, the interlayer insulating film must be formed of a low dielectric film having a dielectric constant lower than 3.9.

A method of forming a low-k dielectric film between metal wires such as copper wires is described in US Pat. No. 6,465,361, entitled "Method for Preventing Damage of Low-k Dielectrics During Patterning. Patterning ”, as described by You et al. According to Yu et al., A low dielectric film and a capping film are sequentially formed on a semiconductor substrate, and a photoresist pattern is formed on the capping film. The capping layer and the low dielectric layer are etched using the photoresist pattern as an etching mask to form openings. Subsequently, the photoresist pattern is removed using oxygen gas. During the removal of the photoresist pattern, damage may be applied to the low dielectric film exposed by the opening to change properties of the low dielectric film. Accordingly, Dielectric et al. Discloses curing the damaged low dielectric film after the photoresist pattern is removed to recover the damage of the low dielectric film. After curing the low dielectric film, a copper wiring filling the opening is formed.

As described above, dielectric and the like provide a method of forming an insulating film between metal wirings into a low dielectric film. Therefore, parasitic capacitance between the metal wires is reduced, and the delay time of the electrical signal applied to the metal wires can also be reduced. Nevertheless, there may be a limit in improving electrical characteristics of high performance and highly integrated semiconductor devices. This is because it is difficult to adopt the low-dielectric film as an insulating film (ie, a pre-metal dielctric layer) between the conductive lines formed before the metallization process. If the pre-metal dielectric layer is formed of the low dielectric film, the low dielectric film may change into a high dielectric film due to a subsequent high heat treatment temperature. Therefore, the insulating film before the metal process adopted in the conventional semiconductor device is still formed of a silicon oxide film having thermal stability.

1 is a cross-sectional view illustrating a method of manufacturing a conventional flash memory device.

Referring to FIG. 1, an isolation layer (not shown) is formed in a predetermined region of the semiconductor substrate 1 to define the active region 3a. A plurality of parallel gate patterns, for example, first to fourth gate patterns G1,..., G4, are formed to cross the upper portion of the active region 3a. Each of the gate patterns G1,..., And G4 includes a tunnel oxide layer 5, a floating gate 7, a gate interlayer insulating layer 9, a control gate electrode 11, and a gate capping layer pattern that are sequentially stacked. 13) can be formed. Low concentration source / drain regions 15 are formed by implanting impurity ions into the active region 3a using the gate patterns G1,..., And G4 as an ion implantation mask. After formation of the low concentration source / drain regions 15, gate spacers 17 are formed on sidewalls of the gate patterns G1,..., G4. The gate spacers 17 may be formed of silicon nitride for self-aligned contact technology. An interlayer insulating film 19 is formed on the substrate having the gate spacers 17. The interlayer insulating film 19 is formed of a silicon oxide film as described above. First to fourth flash memory cells C1 to C4 are formed at intersections of the gate patterns G1 to G4 and the active region 3a, respectively.

In the above-described conventional flash memory device, the gap regions between the floating gates 7 are filled with the gate spacers 17 and the interlayer insulating layer 19, and parasitics between the floating gates 7. The capacitance C _FG may be determined by the dielectric constant of the gate spacers 17 and the interlayer insulating layer 19 and the gap between the floating gates 7. For example, when the gate spacers 17 are formed of a silicon nitride film having a dielectric constant of about 7.9 and the spacing between the floating gates 7 decreases, the parasitic capacitance C _FG may increase significantly. have. In this case, when the second flash memory cell C2 is selectively programmed, electrons are injected into the floating gate 7 of the second flash memory cell C2 to float the second flash memory cell C2. The electric potential of the gate 7 is changed and the potential of the floating gate 7 of the third flash memory cell C3 adjacent to the second flash memory cell C2 is also applied to the parasitic capacitance C _FG . May change due to As a result, the threshold voltage of the third flash memory cell C3 changes. Therefore, a read error may occur in an operation mode for selectively reading data stored in the third flash memory cell C3. Therefore, there is a continuous need for a method of forming an insulating film before a metal process into a thermally stable low dielectric film in order to improve electrical characteristics of a high performance semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device capable of improving thermal stability of a low dielectric film that is employed as an insulating film before a metal process.

Another technical problem to be achieved by the present invention is to provide a semiconductor device suitable for improving the thermal stability of a low dielectric film employed as an insulating film before a metal process.

According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device having an intermetallic insulating film formed on a semiconductor substrate and metal wires formed in the intermetallic insulating film. The method includes forming wiring patterns between the semiconductor substrate and the interlayer insulating film. Each of the wiring patterns is formed to have at least conductive wiring. A low dielectric film is formed on the wiring patterns and the semiconductor substrate. The low dielectric film is formed of an insulating film having a lower dielectric constant than the silicon oxide film. A capping film is formed on the low dielectric film to block oxygen and / or water (H ₂ O). The low dielectric layer and the capping layer are formed under the interlayer insulating layer.

In some embodiments of the present invention, each of the wiring patterns may be formed to include a tunnel oxide film, a floating gate, a gate interlayer insulating film, and a control gate electrode which are sequentially stacked.

In other embodiments, the wiring patterns may be word line patterns of DRAM cells.

In still other embodiments, the low dielectric layer may include a fluorine-doped silicate glass layer (FSG), a hydrogen-containing silicon oxide film (HSQ), or a carbon-containing silicon silsesquioxane layer; MSQ or SiOC).

In other embodiments, the capping layer may be formed of a silicon nitride layer (SiN), a silicon carbide layer (SiC), or a silicon oxide layer.

In another embodiment, an adhesion layer may be further formed at an interface between the capping layer and the low dielectric layer. The adhesive layer may be formed by applying a plasma treatment to the low dielectric layer before forming the capping layer. The plasma treatment may be performed using nitrogen gas, oxygen gas, helicase gas, nitrogen oxide (N ₂ O) gas, or silane (SiH ₄ ) gas as the plasma source gas.

In still other embodiments, low concentration source / drain regions may be formed by implanting impurity ions into the active region using the wiring patterns as an ion implantation mask before forming the low dielectric layer, and may be formed on sidewalls of the wiring patterns. Gate spacers may be formed in the substrate. Subsequently, impurity ions may be implanted into the active region using the gate spacers and the wiring patterns as ion implantation masks to form high concentration source / drain regions having a higher impurity concentration than the low concentration source / drain regions. . In addition, after the formation of the high concentration impurity regions, the gate spacers may be selectively removed.

According to another aspect of the present invention, there is provided a semiconductor device having a semiconductor substrate, an intermetallic insulating film on the semiconductor substrate, and metal wires in the intermetallic insulating film. The semiconductor device may include wiring patterns interposed between the semiconductor substrate and the metal interlayer insulating layer. Each of the wiring patterns has at least conductive wiring. The wiring patterns and the semiconductor substrate are covered with a low dielectric film. The low dielectric film has a lower dielectric constant than the silicon oxide film. A capping film is provided on the low dielectric film to block oxygen and / or water (H ₂ O). The low dielectric layer and the capping layer are disposed under the interlayer insulating layer.

In some embodiments of the present invention, each of the wiring patterns may include a tunnel oxide film, a floating gate, a gate interlayer insulating film, and a control gate electrode that are sequentially stacked.

In other embodiments, the wiring patterns may be word line patterns of DRAM cells.

In still other embodiments, the low dielectric layer may include a fluorine-doped silicate glass layer (FSG), a hydrogen-containing silicon oxide film (HSQ), or a carbon-containing silicon silsesquioxane layer; MSQ or SiOC).

In other embodiments, the capping layer may be a silicon nitride layer (SiN), a silicon carbide layer (SiC), or a silicon oxide layer.

In another embodiment, an adhesion layer may be further provided between the capping layer and the low dielectric layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

2 to 4 are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

Referring to FIG. 2, an isolation layer (not shown) is formed in a predetermined region of the semiconductor substrate 51 to define the active region 52a. A plurality of wiring patterns, for example, a plurality of gate patterns G1 ', ..., G4, are formed to cross the active region 52a. Each of the gate patterns G1 ′,..., G4 ′ is formed of a tunnel oxide film 53, a floating gate 55, a gate interlayer insulating film 57, a control gate electrode 59, and a gate capping insulating film that are sequentially stacked. It can be formed to have (61). The gate patterns G1 ′,..., G4 ′ may be formed by a conventional method, and the floating gate 55 and the control gate electrode 59 may be formed of a conductive material film.

Low concentration source / drain regions 63 are formed by implanting impurity ions into the active region 52a using the gate patterns G1 ', ..., G4' as an ion implantation mask. As a result, a plurality of flash memory cells, that is, first to fourth flash memory cells C1 ',..., At the intersections of the gate patterns G1',..., G4 'and the active region 52a, respectively. C4 ') can be formed.

Referring to FIG. 3, after formation of the low concentration source / drain regions 63, gate spacers 65 may be formed on sidewalls of the gate patterns G1 ′,..., G4 ′. have. The gate spacers 65 may be formed of the same material layer as the gate capping insulating layer 61 or a material layer having an etch selectivity with respect to the gate capping insulating layer 61. For example, when the gate capping insulating layer 61 is formed of a silicon nitride layer, the gate spacers 65 may be formed of a silicon nitride layer or a silicon oxide layer. Alternatively, the gate capping insulating layer 61 may be formed of a silicon oxide layer. In this case, the gate spacers 65 may be formed of a silicon nitride film or a silicon oxide film.

As the degree of integration of the flash memory device increases, the distance between the gate patterns G1 ′,..., G4 ′ may decrease. In this case, gap regions between the gate patterns G1 ′,..., G4 ′ may be filled with the gate spacers 65. The low concentration source / drain regions are formed by implanting impurity ions into the active region 52a using the gate spacers 65 and the gate patterns G1 ′,..., G4 ′ as ion implantation masks. High concentration source / drain regions (not shown) having an impurity concentration higher than 63 are formed. As described above, when the gap regions between the gate patterns G1 ', ..., G4' are filled with the gate spacers 65, the gate patterns G1 ', ..., G4 The high concentration source / drain regions may not be formed in the active region 52a between '). An ion implantation process for forming the high concentration source / drain regions may include a common source line (not shown) and a bit line (not shown) of a cell string including the plurality of flash memory cells C1 ', ..., C4'. May be performed to form a string drain region and a string source region electrically connected to each other.

After formation of the high concentration source / drain regions, the gate spacers 65 may be selectively removed. A low dielectric layer 67, that is, a pre-metal dielectric layer before a metal process is formed on the substrate from which the gate spacers 65 are removed. The low dielectric film 67 is formed of an insulating film having a lower dielectric constant than the silicon oxide film. For example, the low dielectric layer 67 may include a fluorine-doped silicate glass layer (FSG layer), a hydrogen-containing silicon oxide layer (HSQ layer), or a carbon-containing silicon oxide layer (methyl). silsesquioxane layer (MSQ layer or SiOC layer). As a result, gap regions between the gate patterns G1 ′,..., And G4 ′ may be filled with the low dielectric layer 67.

An adhesion layer 69 may be formed on the low dielectric layer 67. The adhesive film 69 is formed to improve adhesion between the capping film formed in a subsequent process and the low dielectric film 67. The adhesive film 69 may be formed by applying a plasma treatment process (P) to the low dielectric film 67. In this case, the plasma treatment process P may be performed using nitrogen gas, oxygen gas, helium gas, nitrogen oxide (N ₂ O) gas, or silane (SiH ₄ ) gas as the plasma source gas.

Referring to FIG. 4, a capping layer 71 is formed on the adhesive layer 69. The capping layer 71 may be formed of a material layer that blocks oxygen and moisture (H ₂ O). For example, the capping film 71 may be formed of a silicon nitride film, a silicon carbide film (SiC), or a silicon oxide film. The capping film 71 prevents external oxygen and / or moisture from penetrating into the low dielectric film 67 during a subsequent heat treatment process performed at a temperature higher than about 500 ° C. Is formed. In the case where the formation of the capping film 71 is omitted, the low dielectric film 67 reacts with external oxygen and / or moisture during subsequent high temperature heat treatment processes to form silanol groups (Si-OH bondings). It may contain. The silanol groups change the properties of the low dielectric film 67. For example, the silanol groups may significantly increase the dielectric constant of the low dielectric layer 67. Thus, the capping film 71 prevents the low dielectric film from deteriorating due to a subsequent high temperature heat treatment process.

The capping layer 71 may be formed using a thermal CVD technique or a plasma CVD technique. In particular, when the capping layer 71 is formed of a silicon oxide layer, the silicon oxide layer may be formed of a high density plasma oxide layer showing dense film quality.

Subsequently, although not shown in the drawing, wires such as bit lines may be formed on the capping layer 71, and an interlayer insulating layer may be formed on a substrate having the bit lines. Subsequently, an interlayer insulating layer and metal lines may be formed on the interlayer insulating layer by using a metal wiring process.

In another embodiment of the present invention, the wiring patterns, that is, the gate patterns G1 ′,..., G4 ′, may correspond to word line patterns of DRAM cells.

According to the above-described embodiment, parasitic capacitance between the gate patterns G1 ′,..., G4 ′, for example, parasitic capacitance between the floating gates 55 (C _FG ′ in FIG. 4). May be determined by the dielectric constant of the low dielectric film 67 and the gap between the floating gates 55. In addition, although the low dielectric film 67 is used as a pre-metal dielectric layer as described in the above embodiment, the low dielectric film 67 is thermally due to the presence of the capping film. Can maintain stable characteristics. Therefore, the parasitic capacitance C _FG 'may be smaller than the conventional parasitic capacitance C _FG of FIG. 1.

Now, the structure of the semiconductor device according to the present invention will be described with reference to FIG. 4 again.

Referring back to FIG. 4, an isolation layer (not shown) is provided in a predetermined region of the semiconductor substrate 51 to define the active region 52a. A plurality of impurity regions, for example, a plurality of low concentration source / drain regions 63 are provided in the active region 52a. A plurality of wiring patterns, for example, first through fourth gate patterns G1 ′,..., G4 ′, are disposed on the channel regions between the low concentration source / drain regions 63. The plurality of gate patterns G1 ′,..., G4 ′ may extend to cross the active region 52a. Each of the gate patterns G1, ..., G4 ′ may include at least a conductive line. For example, each of the gate patterns G1 ′,..., G4 ′ may include a tunnel oxide layer 53, a floating gate 55, an interlayer insulating layer 57, and a control gate electrode 59 that are sequentially stacked. And a gate capping insulating layer 61.

Gate spacers 65 may be provided on sidewalls of the gate patterns G1 ′,..., G4 ′. However, the gate spacers 65 may not be provided. The gate patterns G1 ′,..., G4 ′ and the semiconductor substrate 51 are covered with a low dielectric film 67. The low dielectric film 67 is an insulating film having a lower dielectric constant than the silicon oxide film. For example, the low dielectric layer 67 may include a fluorine-doped silicate glass layer (FSG layer), a hydrogen-containing silicon oxide layer (HSQ layer), or a carbon-containing silicon oxide layer (methyl). silsesquioxane layer (MSQ layer or SiOC layer). As a result, the gap regions between the gate patterns G1 ',..., G4' are filled with the low dielectric film 67.

A capping film 71 is provided on the low dielectric film 67. The capping layer 71 is a material layer that blocks oxygen and / or moisture (H ₂ O). For example, the capping layer 71 may be a silicon nitride layer, a silicon carbide layer, or a silicon oxide layer. Therefore, even if a heat treatment process proceeding at a temperature higher than about 500 ° C. is applied to the substrate having the capping film 71, the capping film 71 has external oxygen and / or moisture into the low dielectric film 67. Penetration can be prevented. As a result, the low dielectric film 67 may exhibit thermally stable characteristics. In other words, the capping film 71 may prevent the low dielectric film 67 from deteriorating during the high temperature heat treatment process.

In another embodiment of the present invention, an adhesive film 69 may be provided between the low dielectric film 67 and the capping film 71. The adhesive film 69 may be provided to improve the adhesive force between the low dielectric film 67 and the capping film 71. The adhesive film 69 may be a material film obtained by applying a plasma treatment process to the surface of the low dielectric film 67.

In another embodiment of the present invention, the gate patterns G1 ′,..., G4 ′ may be word line patterns of DRAM cells.

Although not shown, an interlayer insulating film may be provided on the capping layer 71 to cover wirings such as bit lines and the wirings, and an interlayer insulating film may be disposed on the interlayer insulating film to cover the metal wires and the metal wires. Can be provided.

Experimental Examples; examples>

FIG. 5 is a graph illustrating a change in characteristics of a low dielectric film employed as a pre-metal dielctric layer of a semiconductor device according to the present invention. In Fig. 5, the horizontal axis shows the heat treatment temperature (T) of the low dielectric film, and the vertical axis shows the dielectric constant (C) of the low dielectric film. In addition, the data denoted by "A" correspond to the characteristics of the low dielectric film of the samples without the capping film, and the data denoted by "B" correspond to the characteristics of the low dielectric films of the samples having the capping film.

The low dielectric films of the samples showing the experimental results of FIG. 5 were formed of SiOC films, and the capping films were formed of silicon oxide films using plasma CVD techniques. In addition, the heat treatment process applied to the low dielectric film was performed for 30 minutes in a nitrogen atmosphere.

Referring to FIG. 5, both the low dielectric films of the samples A without the capping film and the samples B with the capping film showed a dielectric constant of about 2.5 before the heat treatment process. However, the low dielectric film of Samples A without the capping film showed a dielectric constant of about 3.0 and a dielectric constant of about 4.2 after the heat treatment at 700 ° C. and the heat treatment at 800 ° C., respectively. On the contrary, the low dielectric film of the samples B having the capping film still showed a dielectric constant of 2.5 even after the heat treatment at 700 ° C., and a dielectric constant of about 2.9 after the heat treatment at 800 ° C. As a result, when the insulating film before the metal process was formed of the low dielectric film and the capping film was formed on the low dielectric film, the low dielectric film retained the properties of the low dielectric film even after the heat treatment process at about 800 ° C.

As described above, according to the present invention, when the insulating film before the metal process is formed of the low dielectric film covered with the capping film, the thermal stability of the low dielectric film can be improved. Therefore, the parasitic capacitance between the gate patterns can be reduced, thereby further improving the operation speed of the semiconductor device.

Claims (16)

A method of manufacturing a semiconductor device having a metal interlayer insulating film formed on a semiconductor substrate and metal wirings formed in the metal interlayer insulating film, the method comprises Wiring patterns are formed between the semiconductor substrate and the interlayer insulating film, each of the wiring patterns being formed to have at least conductive wiring, A low dielectric film is formed to cover the wiring patterns and the semiconductor substrate. The low dielectric film is formed of an insulating film having a lower dielectric constant than that of a silicon oxide film. And forming a capping film blocking oxygen and / or moisture (H ₂ O) on the low dielectric film, wherein the low dielectric film and the capping film are formed under the interlayer insulating film. Method of manufacturing a semiconductor device. The method of claim 1, Wherein each of the wiring patterns is formed to include a tunnel oxide film, a floating gate, a gate interlayer insulating film, and a control gate electrode which are sequentially stacked. The method of claim 1, And the wiring patterns are word line patterns of DRAM cells. The method of claim 1, The low dielectric film is formed of a fluorine-doped silicate glass layer (FSG), a hydrogen-containing silicon oxide film (hydrogen silsesquioxane layer (HSQ) or a carbon-containing silicon oxide film (methyl silsesquioxane layer (MSQ or SiOC)) A method of manufacturing a semiconductor device, characterized in that. The method of claim 1, The capping film is a method of manufacturing a semiconductor device, characterized in that formed of a silicon nitride film (SiN), a silicon carbide film (SiC) or a silicon oxide film. The method of claim 1, And forming an adhesion layer at an interface between the capping film and the low dielectric film. The method of claim 6, And the adhesive film is formed by applying a plasma treatment to the low dielectric film before the capping film is formed. The method of claim 7, wherein The plasma process is a method of manufacturing a semiconductor device, characterized in that the nitrogen gas, oxygen gas, helicase gas, nitrogen oxide (N ₂ O) gas or silane (SiH ₄ ) gas is used as the plasma source gas. The method of claim 1, Before forming the low dielectric layer, the interconnection patterns are used as an ion implantation mask to implant impurity ions into the active region to form low concentration source / drain regions, Forming gate spacers on sidewalls of the wiring patterns, Implanting impurity ions into the active region using the gate spacers and the wiring patterns as ion implantation masks to form high concentration source / drain regions having a higher impurity concentration than the low concentration source / drain regions; A method of manufacturing a semiconductor device, characterized in that. The method of claim 9, Selectively removing the gate spacers after the formation of the high concentration impurity regions. A semiconductor device having a semiconductor substrate, an intermetallic insulating film on the semiconductor substrate, and metal wires in the intermetallic insulating film, Wiring patterns interposed between the semiconductor substrate and the metal interlayer insulating layer, each of which includes at least conductive wires; A low dielectric film covering the wiring patterns and the semiconductor substrate and having a lower dielectric constant than that of the silicon oxide film; And And a capping film covering the low dielectric film and blocking oxygen and / or moisture (H ₂ O), wherein the low dielectric film and the capping film are disposed under the interlayer insulating film. The method of claim 11, Each of the wiring patterns includes a tunnel oxide film, a floating gate, a gate interlayer insulating film, and a control gate electrode, which are sequentially stacked. The method of claim 11, And the wiring patterns are word line patterns of DRAM cells. The method of claim 11, The low dielectric film may be a fluorine-doped silicate glass layer (FSG), a hydrogen-containing silicon oxide film (hydrogen silsesquioxane layer (HSQ) or a carbon-containing silicon oxide film (methyl silsesquioxane layer (MSQ or SiOC)), characterized in that A semiconductor element. The method of claim 11, The capping film is a semiconductor device, characterized in that the silicon nitride film (SiN), silicon carbide (SiC) or silicon oxide film. The method of claim 11, And an adhesion layer between the capping film and the low dielectric film.

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