KR20070068851A - Voltage down converting circuit of semiconductor memory apparatus - Google Patents

Abstract

A voltage down converting circuit of a semiconductor memory device is provided to stabilize operation of the memory device by reducing the variation in an internal voltage, even when an external voltage is varied. A voltage down converting circuit of a semiconductor memory device includes a clamping unit(100) and a voltage down converter(200). The clamping unit clamps an external supply voltage in response to a first internal voltage input and outputs the result. The voltage down converter uses the clamped voltage as a source voltage. The first internal voltage is a high voltage, which is formed by pumping up the external supply voltage. The clamping unit is a first NMOS(Negative Metal Oxide Semiconductor) transistor(N1), which receives the first interval voltage at a gate thereof. The clamping unit further includes a second NMOS transistor(N2).

Description

Voltage Down Converting Circuit of Semiconductor Memory Apparatus

1 is an output diagram of a voltage down converting circuit of a general semiconductor memory device;

2 is a block diagram of a voltage down converting circuit of a semiconductor memory device according to the present invention;

3 is a detailed block diagram of the voltage down converting circuit shown in FIG. 2;

4 is a detailed circuit diagram of a voltage down converting circuit of a semiconductor memory device according to the present invention;

5 is an output diagram of the voltage down converting circuit shown in FIG. 4;

FIG. 6 is a circuit diagram illustrating another example of the clamp unit illustrated in FIG. 4.

<Description of the symbols for the main parts of the drawings>

100: clamp portion 200: voltage down converter

210: comparator 220: voltage divider

230: switching unit

The present invention relates to a voltage down converting circuit of a semiconductor memory device, and more particularly, to a drain terminal of a MOS transistor instead of directly using a power supply of a voltage down converter as an external supply voltage VDD. Supply the external supply voltage (VDD) to the high voltage, supply a high potential voltage (VPP), one of the internal power supply to the gate terminal and clamp the external supply voltage (VDD) to output the voltage down converter (Voltage Down Converter) The present invention relates to a voltage down converting circuit of a semiconductor memory device capable of stabilizing the operation of a memory by using the same as a power source.

A voltage down converting circuit of a general semiconductor memory device may use the external supply voltage VDD as a power source, a voltage VREF that is a reference to the internal voltage Vint to be made from the external supply voltage VDD, and By comparing the voltage generated by dividing the internal voltage Vint to a constant level, the external supply voltage VDD is supplied or cut off to the internal voltage Vint to generate an internal voltage Vint of a constant level.

1 is a diagram illustrating an internal voltage output of a voltage down converting circuit of a general semiconductor memory device.

As shown in FIG. 1, as the external supply voltage VDD increases, the level of the internal voltage Vint increases, and the fluctuation width of the internal voltage Vint level also increases.

In order to improve the reliability of the transistor, the internal voltage Vint level is gradually lowered. When the internal voltage Vint level is made low at the high external supply voltage VDD, the external supply voltage VDD level increases. The internal voltage Vint level is increased and fluctuation width is also increased, which causes problems in operation and characteristics of the memory.

The present invention has been made to solve the above-described problem, and instead of directly using the power of a voltage down converter as an external supply power supply VDD, the clamped external supply voltage ( A semiconductor memory capable of reducing the increase or fluctuation width of the internal voltage Vint due to the increase in the external supply power supply VDD by using the VDD level as a power supply of a voltage down converter. The technical challenge is to provide a voltage down converting circuit of the device.

According to another aspect of the present invention, there is provided a voltage down converting circuit of a semiconductor memory device, the clamp unit configured to clamp and output an external supply voltage in response to a first internal voltage input; And a voltage down converter using the clamp voltage as a power source.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram illustrating a voltage down converting circuit of a semiconductor memory device according to the present invention.

The voltage down converting circuit of the semiconductor memory device according to the present invention outputs a clamp voltage VDDCLP by clamping the external supply voltage VDD in response to a high potential voltage VPP generated by pumping an external supply voltage VDD. To clamp portion 100; And a voltage down converter 200 which outputs an internal voltage Vint by using the clamp voltage VDDCLP as a power source and a converter driving signal EN_DIFF and a reference voltage VREF as inputs.

3 is a detailed block diagram of the voltage down converting circuit shown in FIG. 2.

The voltage down converting circuit of the semiconductor memory device according to the present invention includes a clamp unit 100 for outputting the clamp voltage VDDCLP clamping the external supply voltage VDD in response to the high potential voltage VPP; A comparator 210 comparing the divided voltage levels of the reference voltage VREF and the internal voltage Vint with the clamp voltage VDDCLP as the power and the converter driving signal EN_DIFF as an input. ); A voltage divider 220 for distributing the level of the internal voltage Vint; And a switching unit 230 that controls the supply of the clamp voltage VDDCLP by using the clamp voltage VDDCLP and the level output from the comparison unit as inputs.

4 is a detailed circuit diagram of a voltage down converting circuit of a semiconductor memory device according to the present invention.

The clamp unit 100 receives the external supply voltage VDD at a drain terminal and the high potential voltage VPP at a gate terminal, and outputs the clamp voltage VDDCLP through a source terminal. It is composed of a MOS transistor (N1).

The comparator 210 is configured at a common node and a drain terminal of the second NMOS transistor N2 and the second NMOS transistor N2 that receive the converter driving signal EN_DIFF from a gate terminal. A third NMOS transistor N3 connected to a source terminal and receiving the reference voltage VREF at the gate terminal, the common node and the source terminal connected to each other, and exiting from the gate terminal through a third node nodeC A fourth NMOS transistor N4 that receives a voltage division level, the clamp voltage VDDCLP is input to a source terminal, and a drain terminal of the fourth NMOS transistor N4 receives a voltage distribution level. The first PMOS transistor P1, which is met at one node nodeA and has a gate terminal connected to the second node nodeB, is inputted with the clamp voltage VDDCLP at a source terminal, and a drain terminal and a gate terminal are connected to each other. The fourth NMOS transistor It is configured in the second PMOS (PMOS) transistor (P2) is connected at the drain end and the second node (nodeB) of (N4).

The voltage divider 220 includes a fifth NMOS transistor N5 which is a diode-type load receiving the internal voltage Vint and a sixth NMOS transistor N6 that is a diode-type load. Is connected at the third node nodeC.

The switching unit 230 receives a level output from the first node nodeA from a gate terminal and determines a supply of the clamp voltage VDDCLP input to a source terminal. It is composed of

The operation of the voltage down converting circuit of the semiconductor memory device according to the present invention will be described with reference to FIG. 4 as follows.

The external supply voltage VDD is input to the drain terminal of the first NMOS transistor N1, and the high potential voltage VPP is input to the gate terminal of the first NMOS transistor N1. When input to, the threshold voltage Vt of the first NMOS transistor N1 at the high potential voltage VPP when the external supply voltage VDD is higher than the high potential voltage VPP. VPP-Vt subtracted) is output from the source terminal of the first NMOS transistor N1 to the clamp voltage VDDCLP, and the external supply voltage VDD is applied to the high potential voltage When the level is lower than VPP), the external supply voltage VDD level is output as the converter supply voltage VDDCLP.

When the output voltage of the clamp voltage VDDCLP is used as the power of the voltage down converter, the second NMOS transistor N2 is enabled when the converter driving signal EN_DIFF is enabled. It is turned on.

Input to the gate terminal of the fourth NMOS transistor N4 through the reference voltage VREF and the third node nodeC received from the gate terminal of the third NMOS transistor N3. When the voltage division level inputted through the third node nodeC is higher than the reference voltage VREF, the current flowing through the second node nodeB is increased by the fourth NMOS. More than the third NMOS transistor N3 flows through the NMOS transistor N4, and the voltage level of the second node nodeB is lowered so that the first PMOS transistor P1 and the NMOS transistor N4 flow. The second PMOS transistor P2 is turned on to supply the clamp voltage VDDCLP to the first node nodeA and the second node nodeB. Since a relatively small current flows through the third NMOS transistor N3 through the first node nodeA, the voltage level of the first node nodeA increases and the third PMOS is increased. The PMOS transistor P3 is turned off to block the clamp voltage VDDCLP from being supplied to the internal voltage Vint, thereby lowering the level of the internal voltage Vint.

On the other hand, when the reference voltage VREF level is higher than the voltage level of the third node nodeC, the current flowing through the third NMOS transistor N3 causes the fourth NMOS transistor. Since the second node nodeB is at a high level because the current flows through N4, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on. It is turned off to block the clamp voltage VDDCL from being supplied to the comparator 210. Since the first node nodeA is at a low level, the clamp voltage VDDCLP is supplied by turning on the third PMOS transistor to raise the internal voltage Vint.

As described above, the voltage down converter supplies a current to increase the internal voltage Vint level when the internal voltage Vint level is lower than a voltage level to be made from the reference voltage VREF. When the internal voltage Vint level is higher than the desired voltage level, the current supply is cut off so that the internal voltage Vint level is always maintained at a constant voltage level.

5 is an output diagram of a voltage down converting circuit of a semiconductor memory device according to the present invention.

Since the first NMOS transistor N1 acts as a clamp even when the external supply voltage VDD level rises above the high potential voltage VPP level, the high potential voltage VPP. ) Is a constant voltage (VPP-Vt) from which the threshold voltage (Vt) of the first NMOS transistor (N1) is removed is used as the supply voltage (VDDCLP) of the voltage down converter (200). Vint) can be kept stable.

In other words, even when the external supply voltage VDD rises, the internal voltage Vint level remains constant, and the fluctuation width of the internal voltage Vint is small.

FIG. 6 is a circuit diagram illustrating still another embodiment of the clamp unit illustrated in FIG. 4.

As illustrated in FIG. 6, the clamp unit 100-1 may include a first NMOS transistor N1 and a first NMOS that receive the high potential voltage VPP at a drain terminal and a gate terminal. NMOS) The second NMOS transistor N2 receives the voltage output from the source terminal of the transistor N1 at the gate terminal and the external supply power supply VDD at the drain terminal. The clamp unit 100-1 may output the voltage VPP Vt from which the threshold voltage Vt is removed from the high potential voltage VPP by the first NMOS transistor N1. N2 receives the voltage VPP Vt at the gate terminal and outputs the clamp voltage VDDCLP which is the clamped voltage VPP 2Vt with the external supply power supply VPP at the drain terminal. Since the clamp voltage VPP 2Vt is lower than the clamp voltage VPP Vt in FIG. 4, the straight line A representing the output of the internal voltage Vint in FIG. 5 is slightly lowered and the voltage of the internal voltage Vint is lower. The fluctuation range is also reduced, which makes the internal power supply Vint more stable.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

The present invention increases the internal voltage level even if the external supply voltage VDD is increased by using a power that clamps the external supply voltage VDD as a power of a voltage down converter. Since a stable internal power supply with less fluctuations is formed, it has an effect of stabilizing memory operation.

Claims (6)

A clamp unit configured to clamp and output an external supply voltage in response to the first internal voltage input; And a voltage down converter using the clamp voltage as a power source. The method of claim 1, And the first internal voltage is a high potential voltage generated by pumping the external supply voltage. The method according to claim 1 or 2, And the clamp unit is a first NMOS transistor configured to input the external supply voltage to a drain terminal and the first internal voltage to a gate terminal. The method of claim 1, The clamp unit may input a voltage output from a source terminal of the first NMOS transistor and the first NMOS transistor having the first internal voltage to the drain terminal and the gate terminal, and input the external supply voltage to the drain terminal. A voltage down converting circuit of a semiconductor memory device, comprising: an input second NMOS transistor. The method of claim 1, The voltage down converter includes: a comparing unit configured to compare the divided voltage levels of the reference voltage and the second internal voltage by using the clamp voltage as a power source and a converter driving signal as an input; A voltage divider distributing the second internal voltage level; And a switching unit configured to control the output of the clamp voltage by inputting the clamp voltage and the level output from the comparison unit. The method of claim 5, And the second internal voltage is a voltage output from the voltage down converter.

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