KR20070066471A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device is provided to perform a fabricating process by a variation of a mask process without using an additional process by forming a gate pad when a metal interconnection is formed. A well region is formed in a substrate. An STI layer is formed in the well region to define an active region and a field region. A drift region is formed in the well region corresponding to the active region. A gate electrode(123) is formed on the substrate between the drift regions, not overlapping the drift region, including a gate insulation layer and a gate conductive layer. The gate insulation layer is formed on the substrate between the drift regions, not overlapping the drift region. The gate conductive layer is formed on the gate insulation layer, separated from both sides of the gate insulation layer by a predetermined interval. A source/drain region(127a,127b) is formed in the drift region, separated from the gate electrode by a predetermined interval. An insulation layer is formed on the substrate to cover the gate electrode. A gate pad(132d) is formed on the insulation layer to overlap the drift region between the source/drain region and the gate electrode, electrically connected to the gate electrode.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a cross-sectional view showing an NMOSFET device having a DDD structure according to the prior art.

2 is a plan view of an NMOSFET device having an offset STI structure according to the prior art.

3 is a cross-sectional view showing a cross-sectional structure of the NMOSFET device along the line II ′ shown in FIG. 2.

Figure 4 is a SEM (Scanning Electron Microscope) photo showing the thinning phenomenon of the actual gate oxide film.

5 is a plan view illustrating an NMOSFET device in accordance with an embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a cross-sectional structure of the NMOSFET device along the line II ′ shown in FIG. 5. FIG.

FIG. 7 is a cross-sectional view for explaining the operating characteristics of the NMOSFET device shown in FIG. 6;

8A through 8M are cross-sectional views illustrating a method of fabricating an NMOSFET device in accordance with an embodiment of the present invention.

9 is a sectional view showing a deformation of the gate electrode.

<Description of the symbols for the main parts of the drawings>

100: substrate

101: screen oxide

102, 106, 112, 121, 124, 128: photoresist pattern

103, 107, 129: ion implantation process

105: high voltage P well region

109: N ^- drift region

110: pad oxide film

111: pad nitride film

113, 122: etching process

115: trench

117: STI device isolation layer

119: gate oxide film

120: polysilicon film

123: gate electrode

125 source / drain ion implantation process

127a and 127b: source and drain regions

130: P ⁺ junction area

131: interlayer insulating film

132a, 132b: Source pads and drain pads

132c: Body Pads

132d: Gate Pad

The present invention relates to a semiconductor device, and more particularly to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device having a shallow trench isolation (STI) device isolation film and a method of manufacturing the same.

In the semiconductor integrated circuit, a high voltage control element to which a high voltage is directly applied is formed to directly control an external system using a high voltage. Such high voltage control devices are also required in circuits requiring a high breakdown voltage (BV).

As a device for high voltage control, a CMOS device with low power consumption is widely used. The CMOS device is composed of a P-type MOS (PMOS) transistor and an N-type (MOS) transistor, each transistor having a source region and a drain region below the source region and the drain region to obtain a high breakdown voltage. It has the same conductivity type as the drain region and has a double diffusion drain (hereinafter referred to as DDD) structure having a low concentration region.

Hereinafter, a MOSFET device having a DDD structure according to the prior art will be described with reference to FIG. 1. 1 is a cross-sectional view showing an example of an NMOSFET device having a DDD structure.

As shown in FIG. 1, an NMOFET device having a DDD structure according to the prior art includes a high voltage P ^- well region HPWELL formed in a P-type or N-type semiconductor substrate 10 and a constant in the P ^- well region HPWELL. drift (drift) region 11 and the N ^{- -} drift region 11, the N at risk from the substrate 10, the gate electrode 14 and gate electrode 14 formed on the ^{between-drift} N formed in the region N ⁺ source region 15a and N ⁺ drain region 15b respectively formed in region 11. On the other hand, the gate electrode 14 is composed of a gate oxide film 12 and a polysilicon film 13.

In the conventional NMOSFET device having such a structure, when a high voltage V _PP is applied to the gate electrode 14 and the drain region 15b, respectively, for operation, the gate electrode 14 and the substrate 10 or the drain region are applied. A high electric field is formed between the 15b and the substrate 10. That is, a high electric field is formed in a region (see 'A' region) where the drain region 15b and the gate electrode 14 are adjacent to each other, thereby causing a breakdown voltage. This phenomenon occurs not only in NMOSFET devices but also in PMOSFET devices.

Accordingly, in order to prevent a breakdown of breakdown voltage occurring in a MOSFET device having a DDD structure, a MOSFET device having an offset-Shallow Trench Isolation (STI) structure has been proposed in a technology of 0.25 μm or less.

2 is a plan view of an NMOSFET device having an offset STI structure according to the prior art, and FIG. 3 is a cross-sectional view illustrating a cross-sectional structure of the NMOSFET device along the line II ′ shown in FIG. 2.

As shown in FIG. 2 and FIG. 3, the NMOSFET device having the offset STI structure according to the related art is used in the NMOSFET device having the DDD structure shown in FIG. 1. The device isolation film 23 is further formed in the substrate 20 between 27b). The device isolation film 23 is formed to dissipate a high electric field applied to both sides of the gate oxide film 24 during device operation to alleviate stress caused by the electric field in this region. For reference, the electrical stress due to the electric field decreases as the thickness of the gate oxide layer 24 increases. In addition, the device isolation film 23 is usually formed by forming an N ⁻ drift 22 region and then performing an STI process.

However, due to the STI characteristics, the mott is generated at both corners of the device isolation film 23 having the STI structure. Accordingly, in the related art, the thickness of the gate oxide film 24 in the region where the gate oxide film 24 and the device isolation layer 23 overlap (see 'E' region), that is, the region corresponding to the mote generation region, has a channel region. A thinning phenomenon, which becomes relatively thinner than the thickness of the gate oxide film 24 in the region corresponding to, may occur.

The thinning phenomenon of the gate oxide film 24 can also be confirmed through FIG. 4. FIG. 4 is a scanning electron microscope (SEM) photograph showing a thinning phenomenon of a gate oxide film. Referring to FIG. 4, a gate oxide film 24 in a region corresponding to both edges of an isolation layer 23 having an STI structure is a channel. It can be seen that it is formed significantly thinner than the gate oxide film 24 in the region corresponding to the region.

As described above, when the thinning phenomenon of the gate oxide layer 24 occurs, the breakdown voltage is lowered in a region where the thickness of the gate oxide layer 24 becomes thin, that is, a region corresponding to both edge portions of the device isolation layer 23 having the STI structure. .

Meanwhile, '21', which is not described among the reference numerals shown in FIGS. 2 and 3, is a high voltage P well region HPWELL, and 27c is a P ⁺ junction region for applying a voltage to the high voltage P well region. 25 'is a polysilicon film forming the gate electrode 26,' 28 'is an interlayer insulating film,' 29a 'is a source pad connected to the source region 27a, and' 29b 'is connected to the drain region 27b. Is a dray pad, and '29c' is a body pad connected to the P ⁺ contact area 27c.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and a semiconductor device and a method of manufacturing the same, which can suppress the breakdown voltage from being lowered in the region where the device isolation film having the STI structure and the gate oxide film overlap. The purpose is to provide.

According to an aspect of the present invention, a well region formed in a substrate, an STI device isolation layer formed in the well region to define an active region and a field region, and formed in the well region corresponding to the active region A drift region, a gate electrode formed on the substrate between the drift region so as not to overlap the drift region, a source / drain region formed in the drift region spaced apart from the gate electrode by a predetermined distance, and covering the gate electrode A semiconductor device comprising: an insulating film formed on an entire surface of the substrate; and a gate pad formed on the insulating film so as to overlap the drift region between the source / drain area and the gate electrode and electrically connected to the gate electrode. do.

In addition, according to another aspect of the present invention, there is provided a method of forming a well region in a substrate, forming a drift region in the well region, and defining an active region and a field region in the well region. Forming an STI device isolation film for forming the gate electrode; forming a gate electrode on the substrate between the drift region so as not to overlap the drift region; and source / drain regions within the drift region to be spaced apart from the gate electrode by a predetermined distance Forming an insulating film on the entire surface of the substrate to cover the gate electrode, selectively etching the insulating film to form a contact hole exposing the source / drain region, and forming the contact hole; Depositing a metal layer to fill the gap; and etching the metal layer to bury the source. Forming a gate pad on the insulating layer so as to overlap a source / drain pad connected to the drain / drain region and the source / drain pad so as to overlap the drift region between the source / drain region and the gate electrode; It provides a method of manufacturing a semiconductor device comprising the step of connecting the gate pad and the gate electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

5 is a plan view of a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along the line II ′ of FIG. 5. Here, an NMOSFET device is shown as an example for convenience of description, but this is also sufficiently applicable to a PMOSFET or a CMOSFET device.

5 and 6, an NMOSFET device according to an embodiment of the present invention is an isolation layer 117 (hereinafter, STI) having an STI structure formed in the well region 105 to define an active region A and a field region. An isolation layer), an N ⁻ drift region 109 formed in the well region 105 corresponding to the active region A, and an N ⁻ drift region 109 formed on the well region 105 so as not to overlap the N ⁻ drift region 109. The gate electrode 123 is included. That is, the STI device isolation layer 117 is not formed in the N ⁻ drift region 109.

As described above, in the MOSFET device having the offset-STI structure shown in FIG. 3, both sides of the gate oxide film 119 are partially overlapped with the STI device isolation layer 26 formed in the drift region 22. A thinning phenomenon in which both sides of 119 are relatively thinned occurs, causing a problem in that the breakdown voltage decreases at both sides of the gate oxide film 119.

Therefore, in the embodiment of the present invention, in order to prevent the STI device isolation film 117 from being formed in the substrate 100 at the bottom of the gate oxide film 119, the STI device isolation film 117 is formed in the N ⁻ drift region 109. Not formed. In addition, these N ^- drift region 109 not to overlap with N ^- drift region 109, a gate electrode 123 on the substrate 100 between is formed.

As a result, it is possible to suppress the breakdown voltage from decreasing in the region where the STI device isolation layer 117 and the gate oxide layer 119 overlap each other.

In addition, NMOSFET device according to an embodiment of the present invention, the source and drain regions (127a, 127b) and the gate electrode (123) N formed in the well region 105, ^between-the interlayer insulating film so as to overlap the drift region 109 and the respective ( And two gate pads 132d formed on the inter layer dielectric (ILD) 131.

The gate pad 132d is electrically connected to the gate electrode 123 through the gate contact 140 to function as a gate electrode. Accordingly, the interlayer insulating layer 131 formed under the gate pad 132d is formed between the gate electrode 24 and the source / drain regions 25a / 25b in the MOSFET device having the offset-STI structure shown in FIG. 3. The same function as the device isolation layer 26 is performed.

In this case, the interlayer insulating layer 131 is formed of an oxide-based material, and the gate pad 132d is formed to have the same width as the gate electrode 123.

As described above, in the MOSFET device having the offset-STI structure shown in FIG. 3, the device isolation layer 26 disperses a high electric field applied to both sides of the gate oxide layer 22 during operation of the device, thereby causing stress by the electric field in this region. The electrical stress caused by the electric field decreases as the thickness of the gate oxide layer 22 increases.

Therefore, in the exemplary embodiment of the present invention, the interlayer insulating film 131 is used instead of forming the device isolation film 26 to alleviate the stress caused by the electric field in the MOSFET device having the offset-STI structure shown in FIG. 3.

Accordingly, as illustrated in FIG. 7, the oxide film thickness T at both sides of the gate electrode 123 is determined according to the thickness of the interlayer insulating film 131. As described above, the thicker the portion where the electric field is concentrated, that is, the oxide film on both sides of the gate oxide film 119, the more the stress caused by the electric field is dispersed and alleviated.

As described above, in the MOSFET device according to the exemplary embodiment, the electric field concentrated on both sides of the gate oxide film 119 is dispersed by using the interlayer insulating film 131. This is possible because the gate pad 132d is formed on the interlayer insulating film 131 so as to overlap the N ⁻ drift region 109 on both sides of the gate electrode 123, and then the gate pad 132d is connected to the gate contact 140. This is because it is electrically connected to the gate electrode 123 through. As a result, the gate pad 132d functions as a part of the gate electrode 123 during the device operation. As a result, the interlayer insulating film 131 interposed between the gate pad 132d and the N ⁻ drift region 109 becomes a gate oxide film ( The thickness of both sides of the gate oxide layer 119 in which the electric field is concentrated by being part of 119 is increased.

On the other hand, even if the interlayer insulating film 131 functions as a part of the gate oxide film 119 in the present invention, a basic device is ultimately formed because the channel region is formed in the high voltage P well region 105 (HPWELL) under the gate oxide film 119. It does not affect the properties at all.

Through this structure, the following effects can be obtained in the embodiment of the present invention.

First, a phenomenon in which the breakdown voltage decreases on both sides of the gate oxide film 119 in the MOSFET having the STI device isolation film 117 can be prevented. This is because the STI device isolation film 117 is removed at portions overlapping both sides of the gate oxide film 119.

Next, the electric field stress dispersion and relaxation effects obtained in the MOSFET device having the offset-STI structure can be obtained. This is because, as described above, the electric field concentration is dispersed and relaxed in the offset-STI structure through the interlayer insulating layer 131.

In addition, as described below through the manufacturing method, in the present invention, the gate pad 132d is formed together during the metal wiring forming process for forming the source pad 132a, the drain pad 132b, and the body pad 132c. Therefore, the process may be performed by changing the mask process without an additional process. Therefore, the manufacturing process is easy by that much.

Meanwhile, the gate electrode 123 is formed on the substrate 100 between the N ⁻ drift regions 109 so as not to overlap the N ⁻ drift regions 109 as illustrated in FIG. 9. And the polysilicon film 120 formed on the gate oxide film so as to be spaced apart from both sides of the gate oxide film 119 by a predetermined distance.

This prevents the polysilicon film 120 functioning as the gate conductive film from being formed at both sides of the gate oxide film 119, which is a portion where stress caused by an electric field is concentrated and the breakdown voltage is lowered. Through this, the possibility that the polysilicon layer 120 may overlap with the STI device isolation layer may be removed in advance, thereby improving TDDB (Time Dependent Dielectric Breakdown) and GOI (Gate Oxide Integrity) characteristics.

Hereinafter, a method of manufacturing a MOSFET device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 8A to 8M. Here, the manufacturing method of the NMOSFET device will be described as an example as shown in FIG.

First, as shown in FIG. 8A, a screen oxide 101 is formed on the entire surface of the N-type or P-type doped substrate 100. The screen oxide film 101 prevents the exposed upper surface of the substrate 100 from being damaged during a diffusion process (or ion implantation process) for forming subsequent well and drift regions. In this case, the screen oxide film 101 is formed of a silicon oxide film (SiO ₂ ) using a wet or dry oxidation process. For example, it is formed by a thermal oxidation process using O ₂ gas.

Subsequently, after the photoresist (not shown) is applied onto the screen oxide film 101, an exposure and development process using a photo mask (not shown) is performed to form the photoresist pattern 102. Then, a P-type ion implantation process 103 using the photoresist pattern 102 is performed to implant P-type impurity ions such as boron (B), which is a group 3 material, into the substrate 100.

Subsequently, as shown in FIG. 8B, a strip process is performed to remove the photoresist pattern 102 (see FIG. 8A).

Subsequently, a drive in process is performed to diffuse the P-type impurity ions implanted into the substrate 100 to form the high voltage P well region 105 (HPWELL).

Subsequently, as shown in FIG. 8C, a photomask process is performed to form a photoresist pattern 106 having a structure in which a part of the high voltage P well region 105 is opened on the screen oxide film 101. Here, the region exposed through the photoresist pattern 106 is a region where an N ⁻ drift region of the NMOS device is to be formed.

Subsequently, an N-type ion implantation process 107 using the photoresist pattern 106 is performed to deposit N-type impurity ions such as arsenic (As) or phosphorus (P), which is a Group 5 material, in the exposed P well region 105. Inject.

Subsequently, as shown in FIG. 8D, after removing the photoresist pattern 106 (see FIG. 8D) through a strip process, a drive-in process is performed to diffuse the N ^- type impurity ions implanted into the substrate 100 to form N ^−. The drift region 109 is formed.

Subsequently, as shown in FIG. 8E, a wet etching process is performed to remove the screen oxide film 101 (see FIG. 8D). In this case, the screen oxide layer 101 is selectively removed within a range in which the upper surface of the substrate 100 is not damaged by adjusting the process time of the wet etching process.

Subsequently, an oxidation process is performed to form a pad oxide film 110 on the entire surface of the substrate 100. Here, the pad oxide film 110 is used as a mask in a subsequent device isolation film forming process. The oxidation process is carried out by a wet or dry oxidation process.

Subsequently, a pad nitride film 111 is deposited on the pad oxide film 110. In this case, the pad nitride film 111 is formed of a Si ₃ N ₄ film by using a low pressure chemical vapor deposition (LPCVD) method. Here, the pad nitride film 111 functions as a mask for protecting the surface of the substrate 100 in a subsequent device isolation film forming process.

Subsequently, as shown in FIG. 8F, a photomask process is performed to form a photoresist pattern 112 having an open field region.

Subsequently, a part of the exposed pad nitride layer 111, the pad oxide layer 110, and the substrate 100 is etched by performing the STI etching process 113 using the photoresist pattern 112. As a result, a plurality of trenches 115 are formed in the substrate 100 in the field region.

Subsequently, as shown in FIG. 8G, after the strip process is performed to remove the photoresist pattern 112, a high density HDP (High Density) is formed on the entire surface of the pad nitride film 111 so that the trench 115 (see FIG. 8F) is buried. Plasma) An oxide film is deposited.

Subsequently, a CMP (Chemical Mechanical Polishing) process is performed to form the device isolation film 117 that fills the trench 115.

Subsequently, as shown in FIG. 8H, a wet etching process is performed to remove the pad nitride layer 111 (see FIG. 8G). At this time, the wet etching process is performed using a phosphoric acid (H ₃ PO ₄ ) solution.

Subsequently, a wet etching process is performed to remove the pad oxide film 111. At this time, the wet etching process is performed using a diluted HF (DHF) solution or a BOE (Buffered Oxide Etchant, a solution in which HF and NH ₄ F are mixed at 100: 1 or 300: 1). When the pad oxide layer 111 is removed, the device isolation layer 117 protruding above the substrate 100 is also removed.

Subsequently, as illustrated in FIG. 8I, an oxidation process is performed to form a gate oxide film 119 on the substrate 100. At this time, the oxidation process is carried out in a dry or wet oxidation process.

Subsequently, a polysilicon film 120 to be used as a gate conductive film is deposited on the gate oxide film 119. In this case, the polysilicon film 120 is formed of an undoped or doped silicon film. The undoped silicon film is formed using SiH ₄ or Si ₂ H ₆ by LPCVD. On the other hand, the doped silicon film is formed using SiH ₄ and PH ₃ or Si ₂ H ₆ and PH ₃ by LPCVD.

Subsequently, as shown in FIG. 8J, a photomask process is performed to form the photoresist pattern 121. Here, the photoresist pattern 121 is a mask for defining the gate electrode.

Next, an etching process 122 using the photoresist pattern 121 as an etching mask is performed to sequentially etch the polysilicon layer 120 and the gate oxide layer 119. As a result, the gate electrode 123 is formed on the substrate 100 between the N ⁻ drift regions 109.

Subsequently, as shown in FIG. 8K, a strip process is performed to remove the photoresist pattern 121 (see FIG. 8J).

Next, a photoresist pattern 124 is formed by performing a photo mask process. Here, the photoresist pattern 124 is a mask for defining the source / drain regions.

Subsequently, the source / drain ion implantation process 125 using the photoresist pattern 124 is performed to expose the source and drain regions 127a and 127 in the exposed N ⁻ drift region 109 so as to be spaced apart from the gate electrode 123 by a predetermined distance. 127b). Here, the source / drain ion implantation step 125 is performed by implanting N-type impurity ions such as phosphorus and arsenic, which are Group 5 materials.

Subsequently, as shown in FIG. 8L, a strip process is performed to remove the photoresist pattern 124 (see FIG. 8K).

Next, a photoresist pattern 128 is formed by performing a photomask process. Here, the photoresist pattern 128 is a mask for defining a P ⁺ junction region connected to the body pad.

Subsequently, an ion implantation process 129 using the photoresist pattern 128 as a mask is performed to form a P ⁺ junction region 130 in the exposed high voltage P well region 105. The P ⁺ junction region 130 is formed to apply a voltage to the high voltage P well region 105.

Subsequently, as shown in FIG. 8M, a strip process is performed to remove the photoresist pattern 128 (see FIG. 8L).

Subsequently, an interlayer insulating layer 131 is deposited on the entire surface of the substrate 100 to cover the gate electrode 123. In this case, the interlayer insulating layer 131 is formed of an oxide-based material. For example, HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, PECVD (Plasma Enhanced Chemical Vapor Deposition) film, USG It is formed as a single layer film or a laminated film in which these layers are formed using any one of an un-doped silicate glass (FSG) film, a fluorinated silicate glass (FSG) film, a carbon doped oxide (CDO) film, and an organic silicate glass (OSG) film.

Subsequently, the interlayer insulating film 131 may be planarized by performing a CMP process.

Subsequently, a photo mask process is performed to form a photoresist pattern (not shown). Next, an etching process using a photoresist pattern is performed to etch the interlayer insulating layer 131 to expose the N ⁺ source and drain regions 127a and 127b and the P ⁺ junction region 130, respectively. As a result, a plurality of contact holes (not shown) are formed in the interlayer insulating layer 131.

Subsequently, a strip process is performed to remove the photoresist pattern, and then a metal layer (not shown) is deposited to fill the plurality of contact holes. At this time, the metal layer may be any one selected from the group of Al, W, Cu, Pt, Ti, TiN, main Ta and TaN.

Subsequently, after forming a photoresist pattern (not shown) by performing a photo mask process, an etching process using the same is used to etch the metal layer. Then, a strip process is performed to remove the photoresist pattern.

Thus, the source pad 132a connected to the N + source region 127a, the gate pad 132d serving as a part of the gate electrode of the NMOSFET element, the drain pad 132b connected to the N ⁺ drain region 127b, and P ^+. Body pads 132c connected to the junction region 130 are formed, respectively.

The gate pad 132d is formed to overlap the N ⁻ drift region 109 exposed to both sides of the gate electrode 123 through the interlayer insulating layer 131.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following various effects can be obtained.

 First, in a MOSFET device having an STI device isolation film, it is possible to prevent the breakdown voltage from decreasing on both sides of the gate oxide film.

Second, the field stress dispersion and relaxation effects obtained in MOSFET devices with an offset-STI structure can be obtained.

Third, as the gate pads are formed together during the metallization forming process, the process may be performed by changing the mask process without any additional process. Therefore, the manufacturing process is easy by that much.

Claims (8)

A well region formed in the substrate; STI device isolation layers formed in the well regions to define active and field regions A drift region formed in the well region corresponding to an active region; A gate electrode formed on the substrate between the drift regions so as not to overlap the drift region; A source / drain region formed in the drift region spaced apart from the gate electrode by a predetermined distance; An insulating film formed on the entire surface of the substrate to cover the gate electrode; And A gate pad formed on the insulating film to overlap the drift region between the source / drain region and the gate electrode and electrically connected to the gate electrode Semiconductor device comprising a. The method of claim 1, The gate pad is formed with the same width as the gate electrode. The method of claim 2, The drift region is formed in the same conductivity type as the source / drain region. The gate electrode according to any one of claims 1 to 3, wherein A gate insulating film formed on the substrate between the drift regions so as not to overlap the drift region; And A gate conductive film formed on the gate insulating film so as to be spaced a predetermined distance from both sides of the gate insulating film Semiconductor device comprising a. Forming a well region in the substrate; Forming a drift region in the well region; Forming an STI isolation layer for defining an active region and a field region in the well region; Forming a gate electrode on the substrate between the drift regions so as not to overlap with the drift regions; Forming a source / drain region in the drift region to be spaced apart from the gate electrode by a predetermined distance; Depositing an insulating film on the entire surface of the substrate to cover the gate electrode; Selectively etching the insulating layer to form a contact hole exposing the source / drain region; Depositing a metal layer to fill the contact hole; A source pad and a drain pad connected to the source / drain region by etching the metal layer, and a gate pad on the insulating layer to be separated from the source / drain pad and overlap the drift region between the source / drain region and the gate electrode. Forming a; And Connecting the gate pad and the gate electrode Semiconductor device manufacturing method comprising a. The method of claim 5, And the gate pad is formed to have the same width as the gate electrode. The method of claim 6, And forming the drift region in the same conductivity type as the source / drain regions. The method of any one of claims 5 to 7, wherein the forming of the gate electrode, Forming a gate insulating film and a gate conductive film on the substrate between the drift regions so as not to overlap the drift region; And Etching the gate conductive film up to a predetermined distance from both sides of the gate insulating film Semiconductor device manufacturing method comprising a.

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