KR20070065525A - Hybrid automatic repeat request apparatus using single port memory in a high data-rate wireless communication system and memory allocation method thereof - Google Patents

Abstract

A hybrid automatic repeat request apparatus using a single port memory in a high data-rate wireless communication system and a memory allocation method thereof are provided to improve a data process rate by reducing process speed lowering caused by a memory clear time. A hybrid automatic repeat request apparatus using a single port memory in a high data-rate wireless communication system includes a plurality of memory banks(310-340), an H-ARQ controller(350), a plurality of registers(301-303), a demultiplexer(360), and a multiplexer(370). The plurality of memory banks(310-340) operates as a buffer for storing H-ARQ bursts which consist of information data(Systematic A,B) and a parity data(Parity Y,W). The H-ARQ controller(350) generally controls the apparatus according to dynamic memory allocation algorithm. The plurality of registers(301-303) stores information for a dynamic memory allocation. The demultiplexer(360) demultiplexes the H-ARG burst inputted for each ACQ channel. The multiplexer(370) multiplexes H-ARQ processed data and outputs the H-ARQ processed data to a decoder.

Description

HYBRID AUTOMATIC REPEAT REQUEST APPARATUS USING SINGLE PORT MEMORY IN A HIGH DATA-RATE WIRELESS COMMUNICATION SYSTEM AND MEMORY ALLOCATION METHOD THEREOF}

1 is a view showing a conventional H-ARQ processing process

2 is a block diagram illustrating a configuration of an H-ARQ apparatus 200 of a mobile terminal in a conventional high speed packet data system.

3 is a block diagram illustrating a configuration of an H-ARQ apparatus of a mobile terminal in a high speed packet data system according to an exemplary embodiment of the present invention.

4 is a flowchart illustrating a dynamic memory allocation algorithm performed in the H-ARQ apparatus of FIG. 3 according to an embodiment of the present invention.

5 is a diagram illustrating an example of a dynamic memory allocation process performed in an H-ARQ apparatus according to an embodiment of the present invention.

6 is a block diagram illustrating an example of a memory bank structure of a conventional H-ARQ device;

7 is a block diagram illustrating an example of a memory bank structure of an H-ARQ device according to an embodiment of the present invention.

8 is a timing diagram of data, an address, and a control signal input to a memory bank of FIG. 7 according to an exemplary embodiment of the present invention.

The present invention relates to a packet data receiving apparatus and method thereof in a mobile communication system, and more particularly to a hybrid automatic repeat request (H-ARQ) apparatus and a method of operating the mobile terminal of a high speed packet data system. will be.

In general, a mobile communication system uses a time division multiple access (TDMA) system in which a plurality of subscribers share time in one frequency channel, and a plurality of subscribers use the same frequency band in the same time zone, but different subscribers. Code Division Multiple Access (CDMA), etc., which allocate codes and communicate with each other. Such a mobile communication system has reached the stage of providing a packet data service capable of high-speed, high-quality digital data transmission and multimedia services such as video to a mobile terminal as well as a general voice call service according to the rapid development of current communication technology. have. Representative examples of the high-speed packet data system include the HSDPA system proposed by the Third Generation Partnership Project (3GPP), the EV-DO and EV-DV systems proposed by the 3GPP2, and WiBro, a broadband wireless communication system that provides a mobile Internet service. In addition, preparation for commercialization of each system is actively progressing.

In the fast packet data system, a mobile terminal receiving a packet from a base station informs the base station whether the packet has been successfully received, and the mobile terminal requests the base station to retransmit the packet when there is an error in the received packet. H-ARQ is used as a link control protocol to increase transmission throughput. In addition, the high-speed packet data system uses the H-ARQ method together with a turbo code to increase the reliability of received data since the state of the communication channel is severe and supports multiple access.

For example, in the WiBro system, which is a new standard of the current mobile Internet, when a base station transmits data to a mobile terminal, it generally attaches a CRC and performs convolutional turbo-encoding. The mobile terminal turbo decodes the received data and then performs CRC check, and if there is no error, transmits the received data from the physical layer to the upper layer and requests retransmission to the base station if an error occurs.

In addition, in order to increase the efficiency of H-ARQ, the transmission / retransmission through multiple channels is supported without processing only one transport packet, thereby reducing the time delay for the base station waiting for a response. In order to simultaneously process a plurality of channels, the mobile terminal needs a memory to store the received data for each channel, and this memory is a major cause of increasing the size of the terminal as the size of the transport packet increases. In addition, the retransmitted received data is combined with the received data of the same channel.

In general, since it is practically impossible for a mobile terminal to receive a packet transmitted through a wireless network without any distortion or noise, various packet retransmission schemes have been proposed in H-ARQ to solve this problem. Among these retransmission schemes, for example, using an incremental redundancy (IR) type H-ARQ requires a process of initializing a buffer that stores an H-ARQ burst with a null symbol as much as Nep (encoder packet size) during a new transmission. do.

Because the code rate of the encoder packet is less than 1/3, self-combining must be performed even within one burst. Therefore, the combiner of the mobile station should always operate. After reading and combining the corresponding ARQ channel buffer, the process of writing to the same position is repeated. Therefore, when a H-ARQ burst is input according to a new transmission, a process of clearing a buffer allocated with the corresponding ARQ channel is required before reading the buffer, and this buffer clear operation reduces the throughput of a high-speed packet data system. Generates.

FIG. 1 is a diagram illustrating a conventional H-ARQ method. When a new H-ARQ burst is input as described above, the process of clearing the corresponding buffer (11), reading a buffer, and performing combining, A series of steps 13 of writing data at the same position in the buffer and 15 steps of decoding the stored data proceed in succession.

FIG. 2 is a block diagram illustrating a configuration of an H-ARQ apparatus 200 of a mobile terminal in a conventional high speed packet data system, which assumes a high speed packet data system using four channels.

The H-ARQ device of FIG. 2 corresponds to each ARQ channel (channels 0 to 3) and stores a plurality of H-ARQ bursts including information data (Systematic A, B) and parity data (Parity Y, W). Buffers 210 to 240 are provided. The buffers 210 to 240 are fixed to each ARQ channel (channels 0 to 3). The controller 250 demultiplexes the LLR (ie, H-ARQ burst) input through the demultiplexer 260 according to the ARQ channel number (ACID) transmitted through the MAP information, and buffers 210 for the corresponding channel. After reading the data of ˜240), the data is stored after being combined with the H-ARQ burst. Data output from each of the buffers 210 to 240 are multiplexed through the multiplexer 270 and transferred to a channel decoder (not shown).

In a high speed packet data system, packet data must be processed at high speed, and for this purpose, there is a demand for processing one H-ARQ data symbol per operation clock. To this end, the existing H-ARQ device uses dual port memory (DPSRAM) to continuously perform read / combine / write operations of the buffers 210 to 240. . However, when the dual port memory (DPSRAM) is used, the required memory occupancy area increases by 50 to 70% compared to the single port memory (SPRAM). In addition, since the existing H-ARQ device can self-combine the new H-ARQ burst only when the new H-ARQ burst is input, the existing data stored in the buffers 210 to 240 must be deleted. The operation must be preceded, which results in a large amount of processing time.

The present invention provides an H-ARQ apparatus and a memory allocation method of a mobile terminal capable of improving data throughput in a high speed packet data system.

The present invention also provides an H-ARQ device and a memory allocation method of a mobile terminal using a single port memory that can reduce the occupied volume of the memory.

In addition, the present invention provides an H-ARQ device and a memory allocation method of a mobile terminal capable of reducing the clear time of a buffer by performing dynamic memory allocation.

The apparatus of the present invention is a compound automatic retransmission request (H-ARQ) apparatus of a high-speed packet data system, comprising: a plurality of memory banks alternately performing read and write operations of even and odd symbols, and each memory; A plurality of registers that store information on bank current availability and availability, and information indicating which memory bank a burst of each ARQ channel is stored in, and an H input based on the information stored in the registers. And a controller for controlling the operation of the plurality of memory banks such that an operation of writing an ARQ burst to a currently available memory bank and an operation of clearing a memory bank to store the next input H-ARQ burst are performed at the same time. .

The method of the present invention is a memory allocation method of a compound automatic retransmission request (H-ARQ) device having a plurality of memory banks in a high-speed packet data system, wherein the received H-ARQ burst is received and the received H-ARQ burst is new. Checking whether it is a burst, checking whether the H-ARQ burst is currently used in each memory bank in which the H-ARQ burst is buffered, writing the H-ARQ burst into a currently available memory bank, and inputting the next input. And simultaneously performing an operation of clearing a memory bank to store an H-ARQ burst to be performed.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

First, the basic concept of the present invention will be described. In the present invention, a single port memory (SPSRAM) is used as a buffer memory instead of a dual port memory (DPSRAM) in the H-ARQ device to reduce the occupied volume of the memory in the terminal. In order to use the single port memory (SPSRAM), the H-ARQ burst is divided into even-numbered data and odd-numbered data, and the odd-numbered data is read when the even-numbered data is read by distinguishing the memory for storing the even-numbered data and the odd-numbered data. Suggest a way to write.

In addition, the H-ARQ apparatus of the present invention does not fix each memory bank for each ARQ channel to improve data throughput, and performs a dynamic memory allocation so that the next burst is simultaneously stored when a write operation is performed in one memory bank. In other memory banks, a clear operation is performed to reduce time delays caused by individual performance of the conventional clear operation.

3 is a block diagram illustrating a configuration of an H-ARQ apparatus 300 of a mobile terminal in a high speed packet data system according to an exemplary embodiment of the present invention.

The configuration of FIG. 3 assumes a high speed packet data system using four ARQ channels for convenience of description, and it should be noted that the contents of the present invention are not limited to four ARQ channels. Therefore, the present invention is applicable to various high speed packet data systems such as EV-DO, EV-DV system, HSDPA system or WiBro system using a plurality of ARQ channels.

The apparatus of FIG. 3 includes a plurality of memory banks 310 to 340 which act as a buffer for storing H-ARQ bursts composed of information data System A and Parity data Parity Y and W, and the present invention. H-ARQ controller 350 to control the overall device according to the dynamic memory allocation algorithm of the plurality of registers for storing information for dynamic memory allocation, and the input LLR (H-ARQ burst) The demultiplexer 360 demultiplexes each ARQ channel, and the multiplexer 370 multiplexes the H-ARQ processed data and outputs the same to the channel decoder.

First, terms used for describing the present invention are defined as follows.

1. Memory Usage Map (MUM): A memory usage map that indicates the memory bank currently in use.

2. NAM (Next Available Memory): Indicates the memory bank currently available when a new burst is entered as available memory information.

3. ACQ (ARQ Channel Memory Pointer): Indicates to which memory bank each ARQ channel is assigned.

4. ACID (ARQ Channel ID): It indicates the number (ID) of each ARQ channel.

The values of the MUM, NAM, and ACMP are stored in the first to third registers 301, 302, and 303 of FIG. 3, respectively.

In the conventional H-ARQ apparatus of FIG. 2, each buffer 210 to 240 buffers only a burst of a designated ARQ channel. However, in the present invention, “ACID” is not fixed to the ARQ channel, and the H-ARQ controller 350 is ARQ. Memory banks 310 to 340 that buffer H-ARQ bursts per channel are dynamically allocated. 3, the memory banks 310 to 340 are divided into memory blocks 310a to 340a to store even-numbered data and memory blocks 310b to 340b to store odd-numbered data, respectively. Therefore, the H-ARQ device of the present invention can use a single port memory (SPSRAM) instead of the dual port memory (DPSRAM) as a buffer, and can reduce the size and power consumption of the chip.

Looking at the registers of the present invention, the first register 301 stores memory usage map (MUM) information indicating whether each of the memory banks 310 to 340 is currently used, and the MUM information corresponds to the number of ARQ channels used. It consists of bits, and each bit of the MUM information indicates whether the memory banks 310 to 340 are used. For example, assuming four ARQ channels (Ch # 0 to Ch # 3), MUM information consists of 4 bits, "0001" indicates that Ch # 0 is in use, and "0010" indicates that Ch # 1 is in use. "0011" indicates that Ch # 0 and Ch # 1 are in use.

The second register 302 stores available memory (NAM) information indicating memory banks 310 to 340 currently allocated when a new H-ARQ burst is input. For example, four ARQ channels (Ch #) are stored. Assuming 0 to Ch # 3), each channel has a value of 0 to 3 corresponding to each channel. The third register 303 stores memory pointer (ACMP) information indicating in which memory bank the burst of each ARQ channel is allocated (stored). Therefore, referring to ACMP [ACID], it can be seen that memory banks 310 to 340 in which corresponding H-ARQ bursts are stored. Here, "ACID" means ID (number) of each ARQ channel. For example, assuming four ARQ channels (Ch # 0 to Ch # 3), each of the ARQ channels has a value of 0 to 3 corresponding to each channel.

The role of the H-ARQ controller 350 in FIG. 3 is to set and refer to the values of the first to third registers 301, 302, and 303 described above to allocate a new burst to the currently empty memory banks 310 to 340. The memory banks 310 to 340 are cleared to be used for the next burst, and a read / write address of the corresponding memory banks 310 to 340 is generated to perform a combining operation. In addition, it transmits and receives an interface signal for decoding, such as a turbo decoder (not shown) located at the output of the H-ARQ device.

In the present invention, the clear operation of the memory bank is briefly described. When the H-ARQ controller 350 writes data to the memory bank 0 310, the memory bank 1 320 is cleared for the next input burst. The write operation of the bank 0 310 and the clear operation of the memory bank 1 320 may be simultaneously performed to reduce the time delay according to the individual progress of the clear operation.

Hereinafter, an operation of the H-ARQ device having the configuration of FIG. 3 will be described with reference to the flowchart of FIG. 4.

FIG. 4 illustrates a dynamic memory allocation algorithm performed in the H-ARQ apparatus of FIG. 3 according to an embodiment of the present invention. First, in step 401 of FIG. 4, the power of the mobile terminal is turned on. When reset, the first to third registers 301, 302, 303 are initialized, and in step 403, the H-ARQ controller 350 clears the memory bank 0 310, and a new H-ARQ burst is input. Is set to 0, which indicates the available memory bank. In the present embodiment, in step 403, only one memory bank in which the current H-ARQ burst is stored is cleared, but all or one or more memory banks may be cleared.

When the H-ARQ burst LLR is received in step 405 and input to the demultiplexer 360, the H-ARQ controller 350 determines whether the currently input H-ARQ burst is a new burst or previously stored in the memory bank. Determines whether a burst is to be combined with an H-ARQ burst. As a result of the determination in step 407, if it is a new bus, it can be stored in the memory bank indicated by " NAM " Set the corresponding bit in the MUM [NAM] information to '1' to indicate that an empty memory bank is in use. For example, if "NAM" is 2, it corresponds to memory bank 2, so "MUM" is set to "0 1 00" (assuming that the remaining memory banks are not in use).

In addition, since the H-ARQ burst is designated as "ACID", which is the number of the ARQ channel, the H-ARQ controller 350 refers to "ACID" in step 409, and sets "ACM [ACID]" to the third register 303. Set to "." The reason for setting ACMP [ACID] to "NAM" is to find in which memory bank the burst corresponding to "ACID" is stored when subsequent bursts are entered.

Whether the input H-ARQ burst is a new burst or a continuous burst can be confirmed by the following method. For example, in the WiBro system, an H-ARQ sequence number called "AI_SN" is included in MAP information and received. The "AI_SN" is 1-bit information to be toggled every time a base station transmits a new H-ARQ burst. That is, if the consecutive H-ARQ, the base station transmits the "AI_SN" to the same value, the terminal processes the H-ARQ burst and sends ACK information, when the base station transmits a new H-ARQ burst is different from the previous "AI_SN" A new burst can be identified by sending "AI_SN". One "AI_SN" exists for each channel, and the terminal stores the corresponding "AI_SN" of the H-ARQ channel. If the value is different from the previous "AI_SN", it is determined as a new burst.

Thereafter, in step 411, the H-ARQ controller 350 checks a value of “MUM” indicating whether the memory bank is currently used from the first register 301, and allocates a memory bank that can be allocated when the next new burst is input from “MUM”. Is obtained, and the " NAM " value stored in the second register 302 is updated. Preferably, in step 413, the H-ARQ controller 350 clears the memory bank indicated by "NAM" for storage of the next H-ARQ burst, and at the same time MEM [ACMP] the H-ARQ burst currently input in step 415. It is buffered in a memory bank corresponding to [ACID]] and stored in a self-combining manner. That is, if the H-ARQ device of the present invention is implemented in real hardware, the clear operation of step 413 and the combined operation of step 415 can be simultaneously performed, thereby improving the processing speed of the conventional H-ARQ device structure.

On the other hand, if it is determined in step 407 that the consecutive bursts are input, the H-ARQ controller 350 proceeds to step 417 and immediately reads a memory bank corresponding to MEM [ACMP [ACID]], and then combines them with the input H-ARQ bursts. After doing so, write back. According to the above process, when all new bursts or consecutive bursts are stored in the corresponding memory bank, in step 419, the H-ARQ controller 350 stores the data stored in the memory bank such that data decoding is performed through a channel decoder such as a turbo decoder. To control the output. In operation 421, the H-ARQ controller 350 performs a CRC to decode data correctly and transmits the decoded information to a higher layer if the CRC result is good, and if the CRC result is bad, the base station. Retransmission is requested, and the flow proceeds to step 405 to receive the H-ARQ burst again.

In addition, when the CRC result is good in step 421, the H-ARQ controller 350 sets MUM [ACMP [ACID]] to 0 in step 423 to allocate the corresponding memory bank to another burst. The H-ARQ apparatus of the present invention may repeatedly perform the above operation every burst to improve the processing speed of the present invention.

5 illustrates an example of a dynamic memory allocation process performed in an H-ARQ apparatus according to an embodiment of the present invention.

In FIG. 5, the horizontal axis represents time and illustrates a process of changing the values of "MUM", "NAM", and "ACMP [ACID]" stored in the first to third registers 301, 302, and 303 as time passes. .

Wi, Ri, Ci (0≤i≤3, i is an integer) of FIG. 5 indicate write (Wi), read (Ri), and clear (Ci) operations in the i-th memory bank, respectively. Referring to the case in which “MUM” is “0001” and “NAM” is 1 in FIG. 5, memory bank 0 310 is a memory bank currently being used, and when a burst of Ch # 0 is input, memory bank 0 310 is input. A write (W0) operation and a clear (C1) operation for the memory bank 1 320 are performed at the same time, and then a read (R0) operation for the memory bank 0 310 is performed. At this time, since ACID of "ACMP" is "0" and ACMP [0] = 0, it can be seen that a burst of Ch # 0 is currently allocated to memory bank 0 310.

Subsequently, in FIG. 5, "MUM" is "0010" and "NAM" is 0. The memory bank 1 320 is a memory bank currently being used, and when a burst of Ch # 1 is input, the memory bank 1 320 is input. ) And a clear (C0) operation for memory bank 0 310 are performed at the same time, and a read (R1) operation for memory bank 1 320 is performed at the same time. At this time, since ACMP [0] = 0 and ACMP [1] = 1, it can be seen that a burst of Ch # 1 is currently allocated to memory bank 1 320.

Referring to the case where “MUM” is “0011” and “NAM” is 2 in FIG. 5, the memory bank 0 310 and the memory bank 1 320 are currently used memory banks, and the burst of Ch # 2 is When input, a write (W1) operation for the memory bank 0 310 and a clear (C2) operation for the memory bank 2 330 are simultaneously performed, and a read (R0) operation for the memory bank 0 310 is performed. do. At this time, since ACMP [0] = 0, ACMP [1] = 1, and ACMP [2] = 0, the burst of Ch # 0 is currently allocated to memory bank 0 (310), and the burst of Ch # 2 is allocated to memory bank 0 ( It can be seen that it is assigned to (310).

Hereinafter, since the description of FIG. 5 is similar to the above operation, a detailed description thereof will be omitted. By performing dynamic memory allocation as shown in FIG. 5, since the clear operation and the write operation can be performed simultaneously in different memory banks, time waste due to the clear operation during H-ARQ processing can be reduced. In addition, the H-ARQ processing speed can be increased by dynamically allocating memory banks, but the conventional H-ARQ method requires the use of dual port memory (DPSRAM), which increases the memory occupied area and power consumption. Not suitable for

FIG. 6 is a block diagram illustrating an example of a structure of a memory bank 600 of a conventional H-ARQ device. For example, in order to process the maximum H-ARQ burst proposed by the WiBro system standard, for example, as shown in FIG. Two 2400x8 bit dual port memory (DPSRAM) (610, 620) and two 4800x8 bit dual port memory (DPSRAM) (630, 640) are required per ARQ channel.

7 is a block diagram illustrating an example of a structure of a memory bank 700 of an H-ARQ device according to an exemplary embodiment of the present invention, which may reduce an area occupied by a memory while maintaining a high H-ARQ burst processing speed. The structure is proposed.

In FIG. 7, instead of dual port memory (DPSRAM), a single port memory (SPRAM) for dividing and processing even / odd symbols is used. In this case, as shown in FIG. 7, four 1200x8-bit single port memory (SPSRAM) for processing even-numbered symbols per channel (710 to 740) and four 2400x8-bit single-port memory (SPSRAM) for processing odd-numbered symbols (750 ~ 780) is required. In addition, in FIG. 7, each multiplexer MUX generates a control signal at the controller.

On the other hand, although the structure of FIG. 7 seems to require more memory per channel, it should be noted that the memory bank size of the present invention is smaller when the actual H-ARQ device is implemented.

8 is a timing diagram of data, an address, and a control signal input to the memory bank 700 of FIG. 7 according to an exemplary embodiment of the present invention.

In FIG. 8, "Even WE" and "Odd WE" are toggled per clock for even-numbered symbols and odd-numbered symbols, respectively, and control a read point and a write point. When A0 and L0, which are the first inputs for the even symbol, are inputted, the data D0 corresponding to A0 is output from the next clock, and L'0, which is a value obtained by delaying L0 by one clock to combine D0 and L0, is combined. Get the result C0. Since C0 is generated during the read operation, storing C'0, which is delayed by one clock, in A'0 completes processing of one symbol. If the above operation is performed in the odd numbered manner, the result as shown in FIG. 8 can be seen.

As described above, according to the present invention, the H-ARQ apparatus provided in the mobile terminal of the high speed packet data system can reduce the processing speed due to the memory clear time, thereby improving the data throughput.

In addition, according to the present invention, the memory area and power consumption of the device can be simultaneously reduced by using a single port memory as a buffer of the H-ARQ device instead of the dual port memory. In practice, the memory area was reduced by about 40%.

Claims (7)

In a compound automatic retransmission request (H-ARQ) apparatus of a high speed packet data system, A plurality of memory banks alternately performing read and write operations on even and odd symbols; A plurality of registers for storing information on the current availability and availability of each memory bank and information indicating which memory bank a burst of each ARQ channel is stored in; Writing the input H-ARQ burst to the currently available memory bank based on the information stored in the registers and clearing the memory bank to store the next H-ARQ burst to be performed simultaneously. And a controller for controlling the operation. The method of claim 1, And the controller clears at least one of the plurality of memory banks during an initial reset operation. The method of claim 1, And each of the plurality of memory banks comprises a first memory block for processing the even-numbered symbols and a second memory block for processing the odd-numbered symbols. The method of claim 1, And the plurality of memory banks each use a plurality of single port memories. The method of claim 1, The plurality of registers A first register for storing MUM information indicating whether the respective memory banks are currently used; A second register for storing usable memory (NAM) information indicating whether the respective memory banks are available; And a third register for storing memory pointer (ACMP) information indicating in which memory bank a burst of each ARQ channel is stored. A memory allocation method of a compound automatic retransmission request (H-ARQ) device having a plurality of memory banks in a high speed packet data system, Receiving an H-ARQ burst and checking whether the received H-ARQ burst is a new burst; Determining whether the H-ARQ burst currently uses each memory bank buffered in the case of the new burst; Simultaneously performing an operation of writing the H-ARQ burst into a currently available memory bank and an operation of clearing the memory bank to store the next input H-ARQ burst (H-ARQ). ) Dynamic memory allocation of the device. The method of claim 6, And the plurality of memory banks each use a plurality of single port memories.

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