KR20070056750A - Method of degassing the via hole in the semiconductor device - Google Patents

Method of degassing the via hole in the semiconductor device Download PDF

Info

Publication number
KR20070056750A
KR20070056750A KR1020050115800A KR20050115800A KR20070056750A KR 20070056750 A KR20070056750 A KR 20070056750A KR 1020050115800 A KR1020050115800 A KR 1020050115800A KR 20050115800 A KR20050115800 A KR 20050115800A KR 20070056750 A KR20070056750 A KR 20070056750A
Authority
KR
South Korea
Prior art keywords
via hole
lower metal
semiconductor device
metal film
insulating film
Prior art date
Application number
KR1020050115800A
Other languages
Korean (ko)
Inventor
김현필
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020050115800A priority Critical patent/KR20070056750A/en
Publication of KR20070056750A publication Critical patent/KR20070056750A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H01L21/76894—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern using a laser, e.g. laser cutting, laser direct writing, laser repair

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for degassing a via hole in a semiconductor device is provided to improve burial characteristics in a burial process for burying the via hole with a metal layer by forming a surface of a lower metal layer pattern having a changed level of surface energy. An outgassing process is performed to outgas foreign materials from a via hole by maintaining a state of high temperature in a semiconductor device. A level of surface energy is increased on a lower metal layer pattern(110) and an exposed surface of an inter-metal dielectric layer(120) by using laser beams. An absorption layer(170) is formed on the lower metal layer pattern and the exposed surface of the inter-metal dielectric layer.

Description

반도체소자의 비아홀 디개싱 방법{Method of degassing the via hole in the semiconductor device}Method for degassing the via hole in the semiconductor device

도 1 내지 도 5는 본 발명에 따른 반도체소자의 비아홀 디개싱 방법을 설명하기 위하여 나타내 보인 단면도들이다.1 to 5 are cross-sectional views illustrating a method of degassing a via hole of a semiconductor device according to the present invention.

본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 반도체소자의 비아홀 디개싱 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a via hole degassing method for a semiconductor device.

통상적으로 반도체소자는 금속배선구조를 포함하고 있으며, 더욱이 최근에는 소자의 집적도 증가에 따라 다층 금속배선구조가 채용되고 있다. 이와 같은 다층금속배선구조에 있어서, 하부금속막패턴과 상부금속막패턴은 비아컨택(via contact)에 의해 전기적으로 연결되는데, 이와 같은 비아컨택을 형성하기 위해서는 하부금속막패턴과 상부금속막패턴 사이의 금속간절연막의 일부를 제거하여 하부금속막패턴의 일부 표면을 노출시키는 비아홀을 형성하고, 이 비아홀 내부를 금속막으로 채워야 한다.In general, a semiconductor device includes a metal wiring structure, and more recently, a multilayer metal wiring structure has been adopted as the degree of integration of devices increases. In such a multi-layered metal wiring structure, the lower metal film pattern and the upper metal film pattern are electrically connected by via contacts. In order to form the via contact, the lower metal film pattern and the upper metal film pattern are formed. A portion of the intermetallic insulating film is removed to form a via hole exposing a part surface of the lower metal film pattern, and the inside of the via hole must be filled with a metal film.

그런데 비아홀 내부를 금속막으로 채우기 전에, 통상적으로 디개싱 (degassing) 공정이 수행된다. 이 디개싱 공정은, 선행된 공정에 의해서 형성된 막질에 포함되어 있는 이물질이 후속공정 진행중에 아웃개싱(outgassing)되면서 스텝커버리지(step coverage) 불량, 보이드(void) 형성 등과 같은 공정불량을 유발하는 것을 방지하기 위하여, 비아홀 내의 이물질을 제거하는 공정이다.However, before filling the inside of the via hole with a metal film, a degassing process is usually performed. This degassing process prevents foreign substances contained in the film quality formed by the preceding process outgassing during the subsequent process, causing process defects such as poor step coverage and void formation. In order to prevent this, the foreign matter in the via hole is removed.

종래에는 비아홀이 형성된 웨이퍼를 고온에서 장시간동안 유지시켜 웨이퍼 내의 이물질을 제거함으로써 상기 디개싱 공정을 수행하고 있다. 그러나 최근 소자가 고집적화됨에 따라 비아홀의 크기 또한 감소하고, 그 결과 비아홀 내를 금속막으로 채우는 과정에서 매립특성이 취약해지고 있기 때문에, 기존의 디개싱 방법을 사용할 경우 매립특성을 향상시키는데 한계를 나타내고 있다는 문제가 있다.Conventionally, the degassing process is performed by maintaining a wafer having a via hole at a high temperature for a long time to remove foreign substances in the wafer. However, as the device becomes more integrated in recent years, the size of the via hole also decreases, and as a result, the filling property becomes weak in the process of filling the via hole with a metal film. Therefore, the existing degassing method has a limitation in improving the filling property. there is a problem.

본 발명이 이루고자 하는 기술적 과제는, 고집적화에 따라 크기가 작아진 비아홀 내부를 금속막으로 채우는 과정에서의 매립특성을 향상시킬 수 있는 반도체소자의 비아홀 디개싱 방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a via hole degassing method of a semiconductor device capable of improving a buried property in a process of filling a via hole having a reduced size with a metal film due to high integration.

상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 반도체소자의 비아홀 디개싱 방법은, 하부절연막 위에 형성된 하부금속막패턴과, 상기 하부금속막패턴의 상부 일부표면을 노출시키는 비아홀을 갖는 금속간절연막을 구비하는 반도체소자의 비아홀 디개싱 방법에 있어서, 상기 반도체소자를 고온상태로 유지하여 상기 비아홀 내의 이물질을 아웃개싱하는 단계; 레이저빔을 이용하여 상기 하부금속막패턴 및 금속간절연막의 노출표면에서의 표면에너지를 증가시키는 단계; 및 상기 표면에 너지가 증가된 하부금속막패턴 및 금속간절연막 표면에 흡착층을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above technical problem, a method of degassing a via hole of a semiconductor device according to the present invention includes an intermetallic insulating film having a lower metal film pattern formed on a lower insulating film and a via hole exposing a portion of an upper surface of the lower metal film pattern. A via hole degassing method of a semiconductor device, the method comprising: maintaining the semiconductor device at a high temperature state to outgas the foreign material in the via hole; Increasing surface energy at an exposed surface of the lower metal film pattern and the intermetallic insulating film using a laser beam; And forming an adsorption layer on the lower metal film pattern and the intermetallic insulating film surface having increased energy on the surface.

상기 레이저빔으로 상기 하부금속막패턴보다 큰 광자에너지를 갖는 레이저빔을 사용하는 것이 바람직하다.It is preferable to use a laser beam having a photon energy larger than the lower metal film pattern as the laser beam.

상기 흡착층을 형성하는 단계는 스퍼터링방법을 사용하여 수행하는 것이 바람직하다.Forming the adsorption layer is preferably carried out using a sputtering method.

이하 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안된다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

도 1 내지 도 5는 본 발명에 따른 반도체소자의 비아홀 디개싱 방법을 설명하기 위하여 나타내 보인 단면도들이다.1 to 5 are cross-sectional views illustrating a method of degassing a via hole of a semiconductor device according to the present invention.

먼저 도 1을 참조하면, 반도체기판(미도시) 위의 하부절연막(100) 위에 하부금속막패턴(110)을 형성한다. 반도체기판과 하부절연막(100) 사이에는 다른 막들 또는 소자들이 배치될 수도 있다. 다음에 하부절연막(100) 및 하부금속막패턴(110) 위에 금속간절연막(120)을 형성한다. 이 금속간절연막(120)은 하부의 제1 금속간절연막(121)과 상부의 제2 금속간절연막(122)이 순차적으로 적층되는 구조를 갖는다. 상기 제1 금속간절연막(121)은 SOG(Silicon On Glass) 계열의 산화막일 수 있고, 제2 금속간절연막(122)은 SROX(Semi-Recessed Oxidation) 계열의 산화막일 수 있다. 그러나 상기 금속간절연막(120)은, 단일 절연막구조일 수도 있으며, 경우에 따 라서는 3개 이상의 복합 절연막구조일 수도 있다. 다음에 상기 금속간절연막(120)의 일부를 제거하여 하부금속막패턴(110)의 일부표면을 노출시키는 비아홀(130)을 형성한다. 이와 같이 비아홀(130)을 형성한 후에는, 그 결과물을 고온이 유지되는 챔버 내로 로딩하고, 일정 시간동안 고온상태로 유지되도록 한다. 이 과정에서, 도면에서 화살표로 나타낸 바와 같이, 비아홀(130)에 의해 노출되는 표면상의 이물질들이 아웃개싱된다.First, referring to FIG. 1, a lower metal film pattern 110 is formed on a lower insulating film 100 on a semiconductor substrate (not shown). Other films or devices may be disposed between the semiconductor substrate and the lower insulating film 100. Next, an intermetallic insulating film 120 is formed on the lower insulating film 100 and the lower metal film pattern 110. The intermetallic insulating film 120 has a structure in which a lower first intermetallic insulating film 121 and a second intermetallic insulating film 122 are sequentially stacked. The first intermetallic insulating layer 121 may be a silicon on glass (SOG) -based oxide film, and the second intermetallic insulating layer 122 may be a semi-recessed oxide (SROX) -based oxide film. However, the intermetallic insulating film 120 may have a single insulating film structure, or in some cases, three or more composite insulating film structures. Next, a portion of the intermetallic insulating layer 120 is removed to form a via hole 130 exposing a portion of the lower metal layer pattern 110. After the via hole 130 is formed as described above, the resultant is loaded into a chamber in which a high temperature is maintained and maintained at a high temperature for a predetermined time. In this process, as indicated by the arrows in the figure, foreign matter on the surface exposed by the via hole 130 is outgassed.

다음에 도 2 및 도 3을 참조하면, 고온상태에서의 아웃개싱이 이루어진 결과물 전면에 레이저빔(140)을 조사한다. 이 레이저빔(140)은, 도 2에서 화살표(150)로 나타낸 바와 같이, 일정 방향으로 스캐닝하면서 조사한다. 상기 레이저빔(140)으로는 하부금속막패턴(110)보다 큰 광자에너지를 갖는 레이저빔을 사용하여, 레이저빔(140)에 의해 하부금속막패턴(110)의 막질이 손상되는 것을 방지한다. 또한 조사되는 에너지밀도도 막질의 손상이 없는 정도의 에너지밀도로 설정한다. 이와 같은 레이저빔(140)의 조사에 의해 하부금속막패턴(110) 및 금속간절연막(120)의 노출표면에서는, 도 3에서 굵게 표시한 바와 같이, 막질의 표면에너지가 증가되며, 따라서 후속의 흡착층(adhesion layer)이 균일하게 증착될 수 있도록 한다.2 and 3, the laser beam 140 is irradiated on the entire surface of the resultant outgassing at a high temperature. This laser beam 140 is irradiated while scanning in a fixed direction, as indicated by arrow 150 in FIG. As the laser beam 140, a laser beam having a photon energy greater than that of the lower metal film pattern 110 is used to prevent the film quality of the lower metal film pattern 110 from being damaged by the laser beam 140. In addition, the energy density to be irradiated is also set to the energy density of the extent that there is no damage to the film quality. As a result of the irradiation of the laser beam 140, the surface energy of the film quality is increased on the exposed surfaces of the lower metal film pattern 110 and the intermetallic insulating film 120, as shown in bold in FIG. 3. The adsorption layer can be deposited uniformly.

다음에 도 4 및 도 5를 참조하면, 스퍼터링(sputtering)방법을 사용하여 하부금속막패턴(110) 및 금속간절연막(120) 표면에 흡착층(170)을 형성한다. 앞서 언급한 바와 같이, 레이저빔(140) 조사에 의해 하부금속막패턴(110) 및 금속간절연막(120) 표면에서는 막질의 표면에너지가 증가되었으므로, 스퍼터링 장비의 타겟(target)으로부터 발생되는 흡착층 소스(160)는 하부금속막패턴(110) 및 금속간절 연막(120) 표면상에 균일하게 증착되며, 따라서 스퍼터링 공정이 끝나면 흡착층(170)이 형성된다. 이와 같은 상태에서 비아컨택 형성을 위한 금속막 매립공정을 수행하게 되면, 상기 흡착층(170)으로 인하여 비아홀의 크기가 작더라도 금속막의 매립특성이 향상된다.Next, referring to FIGS. 4 and 5, the adsorption layer 170 is formed on the surface of the lower metal film pattern 110 and the intermetallic insulating film 120 by using a sputtering method. As mentioned above, since the surface energy of the film quality was increased on the surfaces of the lower metal film pattern 110 and the intermetallic insulating film 120 by the laser beam 140, the adsorption layer generated from the target of the sputtering equipment. The source 160 is uniformly deposited on the surfaces of the lower metal film pattern 110 and the intermetallic film 120, and thus, after the sputtering process, the adsorption layer 170 is formed. In this state, when the metal film filling process for forming the via contact is performed, the embedding property of the metal film is improved even though the via hole is small due to the adsorption layer 170.

지금까지 설명한 바와 같이, 본 발명에 따른 반도체소자의 비아홀 디개싱 방법에 의하면, 레이저빔 조사로 하부금속막패턴 표면에너지를 변화시키고, 이어서 변화된 표면에너지를 갖는 하부금속막패턴 표면 위에 흡착층을 형성시킴으로써, 고집적화에 따라 크기가 작아진 비아홀 내부를 금속막으로 채우는 과정에서의 매립특성을 향상시킬 수 있다는 이점이 제공된다.As described so far, according to the via hole degassing method of the semiconductor device according to the present invention, the lower metal film pattern surface energy is changed by laser beam irradiation, and then an adsorption layer is formed on the lower metal film pattern surface having the changed surface energy. As a result, the buried property in the process of filling the inside of the via hole, which has been reduced in size due to high integration, with a metal film is provided.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능함은 당연하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (3)

하부절연막 위에 형성된 하부금속막패턴과, 상기 하부금속막패턴의 상부 일부표면을 노출시키는 비아홀을 갖는 금속간절연막을 구비하는 반도체소자의 비아홀 디개싱 방법에 있어서,In the via hole degassing method of a semiconductor device having an intermetallic insulating film having a lower metal film pattern formed on the lower insulating film and a via hole for exposing a portion of the upper surface of the lower metal film pattern, 상기 반도체소자를 고온상태로 유지하여 상기 비아홀 내의 이물질을 아웃개싱하는 단계;Maintaining the semiconductor device at a high temperature to outgas the foreign matter in the via hole; 레이저빔을 이용하여 상기 하부금속막패턴 및 금속간절연막의 노출표면에서의 표면에너지를 증가시키는 단계; 및Increasing surface energy at an exposed surface of the lower metal film pattern and the intermetallic insulating film using a laser beam; And 상기 표면에너지가 증가된 하부금속막패턴 및 금속간절연막 표면에 흡착층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 비아홀 디개싱 방법.And forming an adsorption layer on the surface of the lower metal film pattern and the intermetallic insulating film having the increased surface energy. 제1항에 있어서,The method of claim 1, 상기 레이저빔으로 상기 하부금속막패턴보다 큰 광자에너지를 갖는 레이저빔을 사용하는 것을 특징으로 하는 반도체소자의 비아홀 디개싱 방법.And a laser beam having a photon energy greater than that of the lower metal layer pattern as the laser beam. 제1항에 있어서,The method of claim 1, 상기 흡착층을 형성하는 단계는 스퍼터링방법을 사용하여 수행하는 것을 특징으로 하는 반도체소자의 비아홀 디개싱 방법.Forming the adsorption layer is a via hole degassing method of a semiconductor device, characterized in that performed using a sputtering method.
KR1020050115800A 2005-11-30 2005-11-30 Method of degassing the via hole in the semiconductor device KR20070056750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050115800A KR20070056750A (en) 2005-11-30 2005-11-30 Method of degassing the via hole in the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050115800A KR20070056750A (en) 2005-11-30 2005-11-30 Method of degassing the via hole in the semiconductor device

Publications (1)

Publication Number Publication Date
KR20070056750A true KR20070056750A (en) 2007-06-04

Family

ID=38354471

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050115800A KR20070056750A (en) 2005-11-30 2005-11-30 Method of degassing the via hole in the semiconductor device

Country Status (1)

Country Link
KR (1) KR20070056750A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11318561B1 (en) 2017-06-14 2022-05-03 United States Of America As Represented By The Secretary Of The Air Force Laser surface melting for outgassing reduction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11318561B1 (en) 2017-06-14 2022-05-03 United States Of America As Represented By The Secretary Of The Air Force Laser surface melting for outgassing reduction

Similar Documents

Publication Publication Date Title
US8716130B2 (en) Method of manufacturing semiconductor device
JP5355892B2 (en) Wiring structure, semiconductor device and manufacturing method thereof
TWI544576B (en) Methods of forming fully clad interconnects
EP0720212A2 (en) Method of manufacturing semiconductor devices
JP2005072384A (en) Method for manufacturing electronic device
WO2016039223A1 (en) Structural body and method for manufacturing same
JP2011222948A (en) Method of manufacturing wiring board
JP2009176886A (en) Production method of semiconductor device
JP2009147096A (en) Semiconductor device and method of manufacturing same
JPH10303295A (en) Manufacture of semiconductor device
US10332850B2 (en) Method for producing contact areas on a semiconductor substrate
JP2010182946A (en) Semiconductor device and method for manufacturing same
US6645864B1 (en) Physical vapor deposition of an amorphous silicon liner to eliminate resist poisoning
KR20070056750A (en) Method of degassing the via hole in the semiconductor device
US7482275B2 (en) Plasma treatment method and method of manufacturing semiconductor device
JP2009117743A (en) Semiconductor device and method of manufacturing same
US20220028803A1 (en) Method of making an individualization zone of an integrated circuit
JP2010245235A (en) Semiconductor device, and manufacturing method of the same
JP2006073612A (en) Resist removing method
WO2011039898A1 (en) Semiconductor device manufacturing method and semiconductor device
JP6639732B2 (en) Electronic component manufacturing method
US7338899B2 (en) Method of forming contact plug in semiconductor device
KR100724271B1 (en) Method of manufacturing semiconductor device
KR100226253B1 (en) Forming method of metal wire for semiconductor chip
TWI825975B (en) Method of manufacturing cleaned packaging substrate and cleaned packaging substrate

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination