KR20070056446A - Apparatus for generating of strobe signal - Google Patents

Abstract

An apparatus for generating a strobe signal is provided to assure margin of a strobe signal easily and accurately, by controlling a memory bank by providing the strobe signal to each column control part in a peripheral circuit region. An apparatus(100) for generating a strobe signal is installed in a peripheral circuit region in order to provide the strobe signal to a column control part connected to each of memory banks, and outputs the strobe signal by assembling a read/write strobe signal and a bank information acquisition signal to the column control part connected to a corresponding memory bank. The read/write strobe signal is generated from a column enable signal output from a command decoder(110). The bank information acquisition signal is generated from the result of predecoding an external column address in a column address pre-decoder(130).

Description

Strobe signal generator {Apparatus for Generating of Strobe Signal}

1 is a schematic configuration diagram of a semiconductor memory device;

2 is a configuration diagram of the column control unit shown in FIG. 1;

3 is a configuration diagram of a strobe signal generator according to the present invention;

FIG. 4 is a detailed circuit diagram of an embodiment of the main strobe signal generator shown in FIG. 3.

<Description of the symbols for the main parts of the drawings>

100: strobe signal generator 110: command decoder

120: RD / WT strobe signal generation unit 130: column address pre decoder

140; Column start section 150: bank selection section

160: main strobe signal generator

The present invention relates to a strobe signal generator, and more particularly, to a strobe signal generator capable of securing a margin between strobe signals in a high speed semiconductor memory device.

As the strobe signal for generating the column selection signal is accelerated as the semiconductor memory device becomes faster, it becomes difficult to secure an accurate margin between the strobe signals. Therefore, a considerable number of delay elements are required to secure a margin between strobe signals, and even in this case, there is a problem in that a margin cannot be accurately secured due to a variable factor.

1 is a schematic configuration diagram of a semiconductor memory device.

As illustrated, the semiconductor memory device may be configured to include at least one bank (banks 0 to 3), and each bank includes a column controller and an X-hole. In addition, when the bank information acquisition signal CAST10 and the read / write strobe signal RDWTSTBP are transmitted to each column controller in the peripheral circuit area separate from the memory bank, the column selection signal YI and the write enable may be performed in each column controller. A strobe signal such as a signal BWEN, a local input / output line precharge signal LIOPCG, and the like are generated.

FIG. 2 is a configuration diagram of the column control unit shown in FIG. 1.

As shown in the drawing, a general column controller includes a column tuning controller 20 and a column-hole 30.

The command decoder 10 receives the bank information acquisition signal CAST10 and the read / write strobe signal RDWTSTBP received from the peripheral circuit area and decodes the received information into an internal command to read the read cas signal CASP_RD, the write cas signal CASP_WT, Output the internal CAS signal ICASP.

The column tuning controller 20 outputs a plurality of column control signals for controlling the respective banks by adjusting the pulse widths of the plurality of column control signals corresponding to the command signal inputted as the column-based command.

The column-hole 30 outputs a strobe signal such as a column selection signal, a write enable signal, a local input / output line precharge signal, and the like according to a plurality of column control signals and internal address signals.

As described above, since the column tuning controller 20 is configured to control the timing and pulse width of the column control signal for each memory bank 40, the general column controller controls the redundancy margin of the memory bank 40. In order to adjust the timing and pulse width of the strobe signal, the entire column tuning control unit 20 operates to generate the same column control signal. That is, since a plurality of column tuning signals having the same timing and pulse width are output from the plurality of column tuning controllers 20, power consumption may occur.

In addition, since the strobe signal is determined by a combination of the bank information acquisition signal CAST10 and the read / write strobe signal RDWTSTBP transmitted to the column controller in the peripheral circuit area, the higher the clock frequency, the higher the strobe. It is difficult to secure a signal margin, and it is difficult to tune the delay time in each column controller.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and generates a strobe signal in a peripheral circuit region, and provides the strobe signal to each column controller to control a memory bank, thereby generating a strobe signal that can easily and accurately secure a strobe signal margin. There is a technical problem in providing a device.

Another object of the present invention is to reduce the layout of a semiconductor memory device by controlling the memory bank by the strobe signal generated in the peripheral circuit region.

The strobe signal generator according to an embodiment of the present invention for achieving the above technical problem is provided in the peripheral circuit region to provide a strobe signal to the column control unit connected to each of the plurality of memory banks, the read / write strobe signal And a strobe signal by a combination of the bank information acquisition signals, and provide the strobe signal to a column controller connected to the corresponding memory bank.

Here, the read / write strobe signal is generated from the column activation signal output from the command decoder, the bank information acquisition signal is generated from the result of pre-decoding the external column address in the column address pre decoder, and the strobe signal generating device is When the write strobe signal is enabled and the bank information acquisition signal indicating any one of a plurality of memory banks is enabled, the strobe signal is output to a column controller connected to the corresponding bank.

In addition, the apparatus for generating strobe signals according to another embodiment of the present invention includes a read / write strobe signal generator for outputting a read / write strobe signal in response to a column activation signal decoded as an internal command signal by the command decoder; A column start section for outputting a column address strobe signal for driving a column of a corresponding bank from bank information output from the column address free decoder; A bank selector for identifying bank information from the column address strobe signal and outputting a bank information acquisition signal; And outputting a strobe signal by a combination of a read / write strobe signal output from the read / write strobe signal generator and a bank information acquisition signal output from the bank selector, and providing the strobe signal to a column controller connected to the corresponding memory bank. It includes; main strobe signal generator.

Here, the strobe signal generator is preferably provided in the peripheral circuit region of the semiconductor memory device.

The main strobe signal generation unit receives a plurality of bank information acquisition signals and read / write strobe signals, respectively, and outputs a strobe signal when both signals are enabled, and provides a plurality of comparison units to provide a column controller of a corresponding memory bank. Each of the plurality of comparison units may be configured as a logic element that receives one of the plurality of bank information acquisition signals and a read / write strobe signal and outputs a comparison result between the two signals. In addition, the logic device may be implemented as a NAND gate or a NOR gate, and when implemented as a NAND gate, the comparator further includes an inverting device connected to an output terminal of the NAND gate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram of a strobe signal generator according to the present invention.

The strobe signal generating device according to the present invention is installed in the peripheral circuit region, and outputs the strobe signal MAIN_STROBE by a combination of the read / write strobe signal RDWTSTBP and the bank information acquisition signal CAST10 and is connected to the corresponding memory bank. Provided to the column controller.

Here, the read / write strobe signal RDWTSTROBE is generated from the column activation signal output from the command decoder, and the bank information acquisition signal CAST10 is obtained from the result of predecoding the external column address in the column address predecoder.

In addition, the strobe signal MAIN_STROBE is a column controller connected to the bank when the read / write strobe signal RDWTWTRBP is enabled and the bank information acquisition signal CAST10 indicating one of the n memory banks is enabled. Is provided.

More specifically described as follows.

As shown in FIG. 3, the strobe signal generator 100 according to the present invention responds to the column activation signals CASP6_RD, CASP6_WT, and ICASP6 decoded as an internal command signal by the command decoder 110 to read / write strobes. The column address received from the RD / WT strobe signal generation unit 120 and the command decoder 110 outputting the signal RDWTSTBP and the external column address signal decoded as the internal command signal from the command decoder 110 and the column address. As the predecoder 130 outputs the bank information and the global column address GAY, the column start unit 140 and the column which output the column address strobe signal CASP8 for driving the column of the bank from the bank information. The bank selector 150 which obtains bank information from the address strobe signal CASP8 and outputs the bank information acquisition signals CAST10 <0: n>, generates an RD / WT strobe signal. The strobe signal MAIN_STROBE <0: n> is output from the read / write strobe signal RDWTSTBP output from the unit 120 and the bank information acquisition signal CAST10 <0: n> output from the bank selector 150. And a main strobe signal generator 160 provided to the column controller connected to the corresponding memory bank.

As described above, in the present invention, since the strobe signal is generated in the peripheral circuit region and provided to the column controller of the corresponding memory bank, the bank information acquisition signal CAST10 <0: n> and the read / write strobe signal RDWTSTBP are more accurate. And easy to control. In addition, the column controller of each memory bank does not perform a separate operation to generate a strobe signal such as a column select signal YI, a write enable signal BWEN, a local input / output line precharge signal LIOPCG, or the like. Since only the delay operation for timing control is performed, the configuration is simple and the layout of the semiconductor memory device can be reduced.

On the other hand, conventionally, by delaying the two signals until the bank information acquisition signal (CAST10 <0: n>) and the read / write strobe signal (RDWTSTBP) is matched in each column controller, unnecessary current is consumed, but in the present invention, Since the strobe signal is generated using the bank information acquisition signals CAST10 <0: n> and the read / write strobe signal RDWTSTBP in the circuit area, the amount of current consumed by each column controller can be reduced.

FIG. 4 is a detailed circuit diagram of an embodiment of the main strobe signal generator shown in FIG. 3.

As illustrated, the main strobe signal generator 160 may read / write n bank information acquisition signals CAST10 <0> to CAST10 <n> in a semiconductor memory device including, for example, n memory banks. A plurality of comparison units 162-0 to 162- which receive the strobe signal RDWTSTBP and output the strobe signal MANI_STROBE <0: n> when both signals are enabled and provided to the column controller of the corresponding memory bank. n).

Here, each of the plurality of comparison units 162-0 to 162-n receives the bank information acquisition signals CAST10 <0: n> and the read / write strobe signal RDWTSTBP and outputs a comparison result between the two signals. The logic device may be configured, and the logic device may be configured of a NAND gate or a NOR gate. In addition, when the logic element is configured as a NAND gate, it is preferable to further include an inverting element at an output terminal of the NAND gate.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

According to the present invention described above, the strobe signal is generated in the peripheral circuit region instead of being generated by the column controller, and thus, the layout of the semiconductor memory device can be reduced.

In addition, the strobe signal generator in the peripheral circuit region generates the strobe signal using the bank information acquisition signal and the read / write strobe signal, so that the strobe signal is easily tuned and excessively consumed to generate the strobe signal in the column controller. It can significantly reduce the amount of current that has been used.

Claims (11)

It is installed in the peripheral circuit area to provide the strobe signal to the column controller connected to each of the plurality of memory banks, and outputs the strobe signal by a combination of the read / write strobe signal and the bank information acquisition signal, and is connected to the corresponding memory bank. A strobe signal generator, characterized in that provided to the column control unit. The method of claim 1, And the read / write strobe signal is generated from a column activation signal output from the command decoder. The method of claim 1, And the bank information acquiring signal is generated from a result of pre-decoding the external column address in the column address predecoder. The method of claim 1, The strobe signal generator is configured to output a strobe signal to a column controller connected to a corresponding bank when the read / write strobe signal is enabled and the bank information acquisition signal indicating any one of a plurality of memory banks is enabled. Strobe signal generator, characterized in that. A read / write strobe signal generation unit configured to output a read / write strobe signal in response to the column activation signal decoded into the internal command signal by the command decoder; A column start section for outputting a column address strobe signal for driving a column of a corresponding bank from bank information output from the column address predecoder; A bank selector for identifying bank information from the column address strobe signal and outputting a bank information acquisition signal; And A strobe signal is output by a combination of a read / write strobe signal output from the read / write strobe signal generator and a bank information acquisition signal output from the bank selector, and provided to the column controller connected to the corresponding memory bank. A main strobe signal generator; Strobe signal generation device comprising a. The method of claim 5, The strobe signal generator is installed in the peripheral circuit region of the semiconductor memory device. The method of claim 5, The main strobe signal generation unit receives a plurality of bank information acquisition signals and a read / write strobe signal, respectively, and when both signals are enabled, a plurality of comparison units for outputting a strobe signal and providing the strobe signal to a column controller of a corresponding memory bank. Strobe signal generation device comprising a. The method of claim 7, wherein And each of the plurality of comparison units is a logic element that receives any one of the plurality of bank information acquisition signals and a read / write strobe signal and outputs a comparison result between the two signals. The method of claim 8, The logic device is a strobe signal generator, characterized in that the NAND gate. The method of claim 9, And the comparing unit further comprises an inverting element connected to an output terminal of the NAND gate. The method of claim 8, The logic device is a strobe signal generator, characterized in that the noah gate.

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