JP3188593B2 - Image data memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates are those which relate to the image data memory for storing the image data of one frame composed of an odd and even fields.

[0002]

2. Description of the Related Art Conventionally, a general-purpose DRA is used for storing image data.
M (dynamic random access memory) has been used.

FIG. 28 shows how data is stored in a conventional image data memory (DRAM). The DRAM 101 stores one frame of pixel data. Each pixel data is composed of, for example, 8 bits (256 gradations).
A plurality of pixel data forming one word corresponding to one scanning line are stored on one word line so as to be designated by the same row address. One frame data is composed of a plurality of words of pixel data, and is divided into odd field data and even field data in accordance with the interlaced system. Moreover, the odd field data and the even field data are stored in adjacent words. For example, the first line data (even 1) of the even field data is arranged in the adjacent word of the first line data (odd 1) of the odd field data, and the first adjacent line word of the odd field data is arranged in the latter adjacent word. Is arranged in the second line data (odd 2).

For high-speed processing of image data by a processor, it is necessary to read out individual pixel data from the DRAM 101 at high speed. Therefore, instead of the normal mode access in which a column address must be supplied for each pixel data, a page mode access in which only the column address of the access leading pixel data in one word is supplied is adopted. If the latter page mode access is adopted, D
Access to the RAM 101 is sped up.

In order to compress and decompress an image, FIG.
As shown in FIG. 8, the processor needs to read out pixel data in a rectangular area (block) having a size of N lines × n pixels (N and n are arbitrary) among all the pixel data in the DRAM 101 at a high speed. Further, a frame access mode for sequentially accessing both line data (eg, odd 1, even 1, odd 2, even 2,...) Of the odd field data and the even field data in the block, and the odd field data in the block There is a field access mode for sequentially accessing only (eg, odd 1, odd 2,...) Or even even fields (eg, even 1, even 2,...).

FIGS. 29A to 29C show the DRAM 101 of FIG. 28 in each mode of frame access, odd field access, and even field access.
It is a figure which shows the access procedure.

According to FIG. 29A, the time T _fx required for frame access of a block of N lines × n pixels in the DRAM 101 is T _fx = N × (t _PC × n) + N × t _RC (1a) Here, t _PC is the access time per pixel in the page mode, and t _RC is the precharge time. The precharge time t _RC is required every time the row address is changed, that is, for each word (one line).

According to FIGS. 29 (b) and 29 (c), DRA
The time T _ox required for odd field access and the time T _ex required for even field access of a block having a size of N lines × n pixels in M101 are: T _ox = (N / 2) × (t _PC × n) + (N / 2) × t _RC (1b) T _ex = (N / 2) × (t _PC × n) + (N / 2) × t _RC (1c)

[0009] Now, Nikkei Micro Device, April 1992
Article in the monthly issue "DRAM new era operating frequency is 100MHZ
“Z Zouhe” (pages 158 to 161) is a synchronous DR
It is about AM. Synchronous DRAM is based on the operating speed of a microprocessor (MPU) and general-purpose DRAM.
High-speed DRA to bridge the gap with access time
It has appeared as M. Synchronous DRA
If a two-bank configuration is adopted for M, while one bank is being accessed, the other bank is precharged,
Both banks can be accessed alternately. This is known to hide the precharge time.

[0010]

As described above, the conventional image data memory has a configuration in which pixel data is stored in a format in which the pixel arrangement in one image is kept as it is, so that frame access and odd / even numbers are used. In any case of the field access, the precharge time t _RC was required every time the row address was changed. Precharge time t
_Since pixel data is not read during _RC , much improvement in the access speed of the conventional image data memory could not be expected even if high-speed page mode access was adopted.

An object of the present invention is to improve the access speed of an image data memory for storing one frame of image data composed of odd fields and even fields.

[0012]

In order to achieve the above-mentioned object, the present invention provides an image data memory having at least two banks, and devises a method of storing pixel data in each bank.

To speed up frame access, odd field data is stored in a first bank, and even field data is stored in a second bank.

In order to speed up the frame access and the odd / even field access, the odd-numbered line data of the odd-numbered field data and the even-numbered line data of the even-numbered field data are stored in the first bank. The odd-numbered line data of the even-numbered field data and the even-numbered line data of the odd-numbered field data are stored in the second bank. However, a buffer memory for temporarily holding even-numbered line data of the even-numbered field data is provided outside the image data memory so that a correct access order of the line data is secured in the frame access mode.

When a four-bank configuration is adopted, the odd-numbered line data of the odd-numbered field data is stored in the first bank and the even-numbered field data is stored in order to speed up the frame access and the odd-numbered / even-numbered field access. The odd-numbered line data of the odd-numbered field data is stored in the second bank, the even-numbered line data of the odd-numbered field data is stored in the third bank, and the even-numbered line data of the even-numbered field data is stored in the fourth bank. Store.

If an increase in the number of pixel data contained in one word is allowed, a two-bank configuration is adopted, and in order to speed up frame access and odd / even field access, odd-numbered field data in the odd-numbered field data is used. The odd-numbered line data and the odd-numbered line data of the even-numbered field data are placed on the same word line of the first bank,
The even line data of the odd field data and the even line data of the even field data are stored on the same word line of the second bank.

In order to further speed up rectangular area access (block access), not only column addresses but also row addresses are continuously and automatically generated.

[0018]

According to the present invention, by precharging another bank while one bank is being accessed, the precharge time t _RC which was conventionally required every time a row address is changed can be reduced. Continuous access to line data is realized.

In addition, the continuous automatic generation of row addresses eliminates the need to fetch a row address from the outside for each word, thereby further improving the speed of block access.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a block diagram of a one-chip DRAM as a two-bank image data memory according to a first embodiment of the present invention. DRAM of FIG.
Is a memory cell array 11 of A bank for storing only odd field data (odd 1, odd 2, odd 3, odd 4,...) In one frame data, and even field data (even 1, even 2, even). 3, even 4,...) Are provided. A,
In each of the B banks 11 and 21, line data corresponding to one scanning line is stored on one word line. 12, 13, 14, 15, and 16 are each A bank 1
1 are a row address buffer, a row decoder, a column address buffer, a column address counter, and a column decoder provided as peripheral circuits. 22,2
Reference numerals 3, 24, 25, and 26 denote a row address buffer, a row decoder, a column address buffer, a column address counter, and a column decoder, respectively, provided as peripheral circuits for the B bank 21.

AX and AY are a row address and a column address supplied from outside to access the A bank 11, respectively. The row address AX is taken into the row address buffer 12. The fetched row address AX is decoded by the row decoder 13 so as to select one of the word lines of the A bank 11. The column address AY is the column address buffer 1
4 The column address counter 15 sequentially increments the input column address of the column decoder 16 so as to realize the page mode access using the fetched column address AY as an initial value. The column decoder 16 selects individual pixel data from one line data selected by the row decoder 13.

BX and BY are a row address and a column address supplied from outside to access the B bank 21 independently of the A bank 11. The functions of the row address buffer 22, row decoder 23, column address buffer 24, column address counter 25, and column decoder 26 are the same as in the case of the A bank 11. Further, similarly to a conventional DRAM, signals (not shown) of a row address strobe (/ RAS), a column address strobe (/ CAS) and a write enable (/ WE) are externally supplied.

The pixel data in the block having the size of N lines × n pixels (N and n are arbitrary) explained in FIG. 28 are stored in the A bank 11 as shown in FIG.
And the B bank 21 are stored in two divided states. 2A to 2D are timing charts showing a method of reading pixel data in one block in the frame access mode of the DRAM of FIG. As shown, the row address AX for the A bank 11 is taken into the row address buffer 12 at the falling timing of / RAS. Next, the column address AY for the A bank 11 is taken into the column address buffer 14 at the falling timing of / CAS. Then, by the page mode operation by the column address counter 15, A
The n pixel data of one line data (odd 1) are sequentially read from the bank 11 at high speed. In this way, while one line data (odd 1) is being read from the A bank 11, the precharge of the B bank 21 is completed. The row address BX for the B bank 21 is fetched into the row address buffer 22 at the next fall timing of / RAS, and the column address BY for the B bank 21 is stored in the column address buffer at the next fall timing of / CAS. Take in 24. As a result, n pixel data of the next one-line data (even) can be read from the B-bank 21 at high speed in the page mode without interruption after reading of one-line data from the A-bank 11 is completed.

FIGS. 3A to 3C are diagrams showing the access procedure of the DRAM of FIG. 1 in each mode of frame access, odd field access and even field access.

According to FIG. 3A, the time T _f1 required for frame access of a block having a size of N lines × n pixels.
_Can be expressed as: T _f1 = N × (t _PC × n) (2a) Here, t _PC is the access time per pixel in the page mode. T _f1 of the equation (2a) is _calculated by the equation (1).
Compared to the conventional T _fx represented in a), the required time is N
× t _RC (t _RC : precharge time) is reduced, and the access speed is improved. That is, according to the present embodiment, the odd field data is stored in the A bank 11 and the even field data is stored in the B bank 21, respectively.
Since one of the banks 11 and 21 is accessed and the other bank is alternately accessed while the other bank is precharged, high-speed frame access is realized. .

However, as shown in FIGS. 3B and 3C, in the odd / even field access mode, only the A bank 11 or only the B bank 21 is accessed, so that the row address (AX or BX) is A precharge time t _RC is still required for each change. That is, the N lines × n pixels in size blocktime takes an odd field access of T _o1, the time T _e1 required for even field _{access, T o1 = (N / 2} ) × (t PC × n) + (N / 2) × t _RC (2b) T _e1 = (N / 2) × (t _PC × n) + (N / 2) × t _RC (2c), and the access speed is improved. Absent.

(Embodiment 2) FIG. 4 is a block diagram of a one-chip DRAM as a two-bank image data memory according to a second embodiment of the present invention. DRAM of FIG.
Is A bank 1 to be accessed in the DRAM of FIG.
Focusing on the fact that the relative position of the word in 1 and the relative position of the word in the B bank 21 match, the method of supplying the row address is changed. In FIG. 4, 31 is a row address buffer common to both the A and B banks 11 and 21, 32 is an inverter, and 33 is a delay circuit. In addition,
Only the odd field data (odd 1, odd 2, odd 3, odd 4,...) In one frame data are stored in the A bank 11, and only the even field data (even 1, even 2, even 3, even 4,...) Are stored. B
The points stored in the banks 21 are the same as in the case of the DRAM of FIG.

AX is a common row address supplied from the outside to access both the A and B banks 11 and 21. The supplied row address AX is taken into the row address buffer 31. The fetched row address AX is decoded by the row decoder 13 for the A bank 11, as in the case of FIG. Also, the row address AX captured in the row address buffer 31
Is input to the row decoder 23 for the B bank 21 via the inverter 32 and the delay circuit 33. All bits of the row address AX except for the least significant bit are directly input to the row decoder 23 for the B bank 21.

FIGS. 5A to 5D are timing charts showing a method of reading pixel data in one block of N lines × n pixels in the frame access mode of the DRAM of FIG. As shown, the row address AX for both the A and B banks 11 and 21 is taken into the row address buffer 31 at the falling timing of / RAS. The fetched row address AX (including the least significant bit) is decoded by the row decoder 13, and
One of the word lines of the A bank 11 is selected by the row decoder 13. On the other hand, the row decoder 23 for the B bank 21 selects one of the word lines of the B bank 21 after a fixed time (for example, several ns) determined by the configuration of the delay circuit 33. That is, the word line selection circuit 35 including the two row decoders 13 and 23, the inverter 32, and the delay circuit 33 works to supply the row address AX for selecting the A bank 11 to the row address buffer 31 only. , B row 21 is automatically generated with a certain delay with a row address different only in the least significant bit. Therefore, as shown in FIGS. 5A to 5D, the column address AY for the A bank 11 is set at the fall timing of / CAS.
After supplying /, the next / C without falling / RAS
If the column address BY for the B bank 21 is supplied at the fall timing of the AS, both the A and B banks 11 and 21 are accessed without interruption in the page access mode in the frame access mode as in the case of the DRAM of FIG. can do.

According to the present embodiment, the time T _f2 required for frame access of a block having a size of N lines × n pixels,
Time T _e2 required for time T _o2 and even field access required for odd field _{access, T f2 = N × (t} PC × n) (3a) T o2 = (N / 2) × (t PC × n) + ( N / 2) × t _RC (3b) _{Te 2} = (N / 2) × (t _PC × n) + (N / 2) × t _RC (3c), and high-speed frame access is realized. Moreover, according to the present embodiment, unlike the case of FIG. 1, there is no need to supply the row address BX for only the B bank 21, so that the supply timing of the column address AY for the A bank 11 and the B bank It is possible to provide a margin between the supply timing of the column address BY and the supply timing of the column address BY.

(Embodiment 3) FIG. 6 shows a two-bank image data memory (DRAM) according to a third embodiment of the present invention.
FIG. 2 is a block diagram of a system including This image data memory system realizes not only high-speed frame access but also high-speed access to odd / even fields, and includes a one-chip DRAM 40 and a processor 5.
0.

The DRAM 40 stores the odd-numbered line data (odd 1, odd 3,...) Of the odd field data in the frame data and the even-numbered line data (even 2, even 4,...) Of the even field data. ), And the odd-numbered line data (even 1, even 3,...) Of the even field data.
..) And even-numbered line data (odd 2, odd 4,...) Of the odd-numbered field data. First and second
In this embodiment, as in the case of the first embodiment, the line data corresponding to one scanning line is stored on one word line in each of the A and B banks 41 and 42. However,
The storage order of line data in the A bank 41 is “odd 1, even 2, odd 3, even 4,...”, And in the B bank 42, “even 1, odd 2, even 3, odd 4,...”. Also, DRA
Peripheral circuits (not shown) similar to FIG. 1 are further provided on the M40 chip. Thus, while accessing one of the A and B banks 41 and 42, the other bank can be alternately accessed while precharging the other bank.

The processor 50 includes a CPU (central processing unit) 51, an SRAM (static random access memory) 52, and a DMAC (direct memory access controller) 53. SRAM 52
Is a small-capacity buffer memory capable of high-speed access for temporarily storing a maximum of one line data. DMAC
Reference numeral 53 controls the DMA transfer of data between the DRAM 40 and the SRAM 52. The CPU 51 uses D
By supplying a row address and a column address to the RAM 40, data transfer with the DRAM 40 is performed. However, in the case of DMA transfer, the DMAC 53 controls the supply of addresses to the DRAM 40.

The pixel data in the block having the size of N lines × n pixels described with reference to FIG. 28 is also divided into A bank 41 and B bank 42 in this embodiment as shown in FIG. It is stored in the state where it was set. FIG. 7 is a flowchart showing a method of reading out pixel data in one block by the processor 50 in each access mode (frame access mode and odd / even field access mode) of the DRAM 40 of FIG.

As shown in FIG. 7, the CPU 51 first determines whether or not a frame access mode is set (step S).
1). If it is not the frame access mode, that is, if it is the odd / even field access mode, the CPU 5
1 is a normal process that does not pass through the SRAM 52 (step S
6) Execute immediately. That is, by alternately accessing the A bank 41 and the B bank 42 of the DRAM 40, the odd field data (odd 1, odd 2, odd 3, odd 4,
..) Or even field data (even 1, even 2, even 3, even 4,...) Only.

On the other hand, in the case of the frame access, if the A bank 41 and the B bank 42 are alternately accessed, the line data is read in the order of "odd 1, even 1, even 2, odd 2,...". As a result, the correct access order “odd 1, even 1, odd 2, even 2,...” Cannot be secured. Therefore, it is determined whether or not it is a specific timing to access the even-numbered line data (for example, even 2) of the even-numbered field data (step S2). If not, the normal processing without passing through the SRAM 52 is performed. While executing (Step S6), if it is the specific timing, special processing (Steps S3 to S5) via the SRAM 52 is executed. According to this special processing, for example, following the reading of the line data “even 1” from the B bank 42 by the CPU 51, the DMAC 5
3, the line data "even 2" is transferred from the A bank 41 to the SRAM 52 incorporated in the processor 50 (step S3). Then, the B bank 42 by the CPU 51
The CPU 51 reads the line data “odd 2” from the SRAM 52 after waiting for the end of reading the line data “odd 2” (step S4). By using the SRAM 52, which can be accessed at high speed, as a buffer memory for temporary storage,
While realizing alternate access of both the A and B banks 41 and 42 in the AM 40, the line data is transferred to the CPU 5 in the correct order.
1 can be read.

FIGS. 8A to 8C are diagrams showing the access procedure of the DRAM 40 in FIG. 6 in each mode of frame access, odd field access and even field access. According to FIG. 8A, the time T _f3 required to access a frame of a block having a size of N lines × n pixels is: T _f3 = N × (t _PC × n) + (N / 4) × (t _PCS × n) (4a). Here, t _PC is an access time per pixel in the page mode of the DRAM 40, and t _PCS is S
This is the access time per pixel of the RAM 52. Also,
According in FIGS. 8 (b) and (c), and the time T _o3 required for odd field access block size of N lines × n pixels, the time T _e3 required for even field access, T _o3 = (N / 2) × (t _PC × n) (4b) _{Te 3} = (N / 2) × (t _PC × n) (4c)

Regarding the above frame access, equation (4a)
If the T _f3 compared to conventional T _fx represented by the formula (1a), the required time is _{T fx -T f3 = N × t} RC - (N / 4) × (t PCS × n) (4d) It can be seen that only As shown in FIG. 9, the larger the number N of lines in one block, the more the equation (4)
d) T _fx -T _f3, that is, the effect of improving the reading speed of the DRAM 40 is increased. In the quantitative comparison shown in FIG. 9, t _RC = 100 ns, t _PCS = 10 ns, and n =
Condition 4 was adopted.

Further, it relates the odd / even field access, respectively compared with conventional T _ox and T _ex of the T _o3 and T _e3 represented by the formula (1b) and (1c) of the formula (4b) and (4c) Then, the required time is (N / 2) × t _RC
(T _RC : precharge time) is reduced, and the access speed is improved.

As described above, according to this embodiment, not only high-speed frame access but also high-speed odd / even field access can be realized. Therefore, in an image data memory system in which a plurality of access modes coexist, one DRAM 40 can be used for the plurality of access modes. In other words, there is no need to prepare a different DRAM for each access mode, which can contribute to a reduction in the cost of the system. In this embodiment, the SRAM 52 is provided separately from the CPU 51 as a small-capacity buffer memory for temporarily storing data.
A register in the PU 51 may be used.

(Embodiment 4) FIG. 10 is a circuit diagram showing a four-bank image data memory according to a fourth embodiment of the present invention.
It is a block diagram of DRAM of a chip. DRA of FIG.
M is a memory cell array 61 of bank A for storing only odd-numbered line data (odd 1, odd 3,...) Of odd-numbered field data in frame data, and odd-numbered line data of even-numbered field data. The memory cell array 62 of the B bank for storing only the line data (even 1, even 3,...) And only the even-numbered line data (odd 2, odd 4,...) Of the odd field data are stored. And a D-bank memory cell array 64 for storing only even-numbered line data (even 2, even 4,...) Of even-numbered field data. Further, on the DRAM chip of FIG. 10, a peripheral circuit (not shown) obtained by extending the configuration of the peripheral circuit for two banks in FIG. 1 or 4 to four banks is further provided. Thereby, for example, in the odd field access mode, while accessing one of the A bank 61 and the C bank 63, the other bank is precharged while the other bank 61, 6 is being precharged.
3 can be accessed alternately.

The pixel data in the block having the size of N lines × n pixels described in FIG. 28 is stored in the A to D banks 61 to 64 in this embodiment as shown in FIG.
It is stored in a divided state. FIG.
11C is a diagram showing an access procedure of the DRAM of FIG. 10 in each mode of frame access, odd field access, and even field access. According to FIG. 11A, the time T _f4 required for frame access of a block having a size of N lines × n pixels can be expressed by T _f4 = N × (t _PC × n) (5a). Also, according to FIGS. 11B and 11C, N
A time T _o4 required for odd field access size of the block of lines × n pixels, the time T _e4 required for even field _{access, T o4 = (N / 2} ) × (t PC × n) (5b) T _e4 = (N / 2) × (t _PC × n) (5c) That is, according to the present embodiment, the access speed can be improved in both frame access and odd / even field access compared to the related art.

FIG. 12 is a graph showing the effect of the number of banks in the DRAM on the chip area. As the number of banks increases, the area of the DRAM chip increases. For example, in the case of the four-bank configuration shown in FIG. 10, the chip area is increased by 20% as compared with the case of one bank. In addition, the cost of the DRAM increases as the chip area increases.
However, in consideration of the improvement of the access speed in all access modes in the case of the 4-bank configuration (this embodiment), one DRAM can be used for a plurality of access modes, contributing to a reduction in the price of the entire image memory system. it can. FIG. 13 shows a conventional T _fx represented by the equation (1a) and a T T of the equation (4a) regarding the frame access.
₁₅ is a graph showing a comparison between _f3 (third embodiment) and T _f4 of the formula (5a) (fourth embodiment). According to the fourth embodiment, not only the access speed is greatly improved compared to the conventional one, but also an improvement is seen as compared with the case of the third embodiment. However, when quantitative comparison shown in FIG. 13, t _PC =
40 ns, t _RC = 100 ns, t _PCS = 10 ns, n =
Condition 4 was adopted.

As in the case of FIG. 4 (second embodiment), a peripheral circuit having a common row address buffer for A to D banks 61 to 64, and both A and C banks 61 and 63
Peripheral circuits that share a row address buffer for
Alternatively, if a peripheral circuit that shares a row address buffer for both the B and D banks 62 and 64 is adopted, a margin can be provided between supply timings of column addresses.

(Embodiment 5) FIG. 14 shows an example of a two-bank image data memory according to a fifth embodiment of the present invention.
It is a block diagram of DRAM of a chip. DRA in FIG.
M represents the odd-numbered line data (odd 1, odd 3,...) Of the odd-numbered field data in the frame data and the odd-numbered line data (even, even 3,...) Of the even-numbered field data. A memory cell array 71 of bank A for storing data on the same word line and even-numbered line data (odd 2, odd 4,.
..) And even-numbered line data (even 2, even 4,...) Of the even-numbered field data on the same word line. That is, in each of the A and B banks 71 and 72, two line data (for example, odd 1 + even 1) corresponding to two scanning lines is stored on one word line. Further, a peripheral circuit (not shown) similar to that of FIG. 1 or 4 is further provided on the DRAM chip of FIG. Thus, while accessing one of the A and B banks 71 and 72, the other bank can be alternately accessed while precharging the other bank.

The pixel data in the block having the size of N lines × n pixels described with reference to FIG. 28 includes the A bank 71 and the B bank 72 in this embodiment as shown in FIG.
And stored in two divided states. However, the number of pixel data included in one word is twice that in the first and second embodiments. FIGS. 15A to 15C show D in FIG. 14 in each mode of frame access, odd field access, and even field access.
FIG. 6 is a diagram showing a procedure for accessing a RAM.

According to FIG. 15A, the time T required for frame access of a block having a size of N lines × n pixels is obtained.
_f5 is expressed by _{T f5 = N × (t PC} × n) (6a). Further, according to FIGS. 15B and 15C, N
A time T _o5 required for odd field access size of the block of lines × n pixels, the time T _e5 required for even field _{access, T o5 = (N / 2} ) × (t PC × n) (6b) T _e5 = (N / 2) × (t _PC × n) (6c) That is, according to the present embodiment, the access speed can be improved in both frame access and odd / even field access compared to the related art. Therefore, this embodiment is very effective when the increase in the number of pixel data included in one word, that is, the increase in the capacitance attached to one word line is allowed.

As in the case of FIG. 4 (second embodiment), if a peripheral circuit that shares a row address buffer for both the A and B banks 71 and 72 is employed, the supply timing of the column address can be improved. It is possible to have a margin in between.

(Embodiment 6) FIG. 16 shows one example of a two-bank image data memory according to a sixth embodiment of the present invention.
It is a block diagram of DRAM of a chip. DRA of FIG.
M is obtained by adding a row address counter 36 to the next stage of the row address buffer 31 so as to reduce the number of times the row address AX is supplied in the DRAM of FIG.
The row address counter 36 sequentially increments the input addresses of the row decoders 13 and 23 with the row address AX taken into the row address buffer 31 as an initial value. Only the odd field data (odd 1, odd 2, odd 3, odd 4,...) In one frame data is stored in the A bank 11, and the even field data (even 1, even 2,.
..) Are stored in the B bank 21 as in the case of the DRAM of FIG.

FIG. 17 is a flowchart showing the operation of the row address counter 36 and the column address counter 15 in the DRAM of FIG. Since the operation of the column address counter 25 for the B bank 21 is the same as the operation of the column address counter 15 for the A bank 11, the description of the former operation is omitted.

As shown in FIG. 17, first, an initial value AX of the row address is set in the row address counter 36 (step S11), and then an initial value AY of the column address is set in the column address counter 15 (step S11).
12). The output of the row address counter 36 is input to the row decoder 13, and the output of the column address counter 15 is input to the column decoder 16 (step S13). Then, while incrementing the output of the column address counter 15 (step S14), one word line (1
After the access of the n pieces of pixel data on the line is completed (step S15), the process proceeds to step S16. Next, the output of the row address counter 36 is incremented (step S16), and the same access to the next line is executed (steps S12 to S15), and the access to the pixel data on the N / 2 word lines is completed. (Step S1
7) Terminate the memory access. That is, while the column address counter 15 repeats counting up n times, the row address counter 36 is set to N / 2 at a cycle of n times.
It counts up times.

FIGS. 18A to 18C show the DRA of FIG.
FIG. 9 is a timing chart showing a parameter setting method when a frame having a size of N lines × n pixels (N = 8, n = 3) in M is accessed in a frame. However, A bank 11
Only the parts related to are shown. As shown, /
At the fall timing t ₀ of the RAS, a 12-bit address supplied from outside through 12 address input pins (external pins) A _{0 to} A ₁₁ is taken into the row address buffer 31. Lower 9 bits A of 12-bit address taken into row address buffer 31
_{0 to} A ₈ are row addresses AX for selecting one of the 512 word lines of the A bank 11, and are set as initial values in the row address counter 36. The upper three bits A _{9 to} A ₁₁ represent the number of lines N / 2 (= 4) of the block to be accessed in the A bank 11, and are used for increment control of the row address counter 36. At the fall timing t ₁ of / CAS, a 12-bit address externally supplied through the same twelve address input pins A _{0 to} A ₁₁ is taken into the column address buffer 14. The lower 9 bits A _{0 to} A ₈ of the 12-bit address fetched by the column address buffer 14 correspond to 512 memory cells (× 8 bit configuration) on one selected word line of the A bank 11. Column address AY for selecting one of the sets, and is set in the column address counter 15 as an initial value. The upper three bits A _{9 to} A ₁₁ are A
It represents the width n (= 3) in the word line direction of the block to be accessed in the bank 11 and is used for increment control of the column address counter 15.

Only by supplying a row address AX for selecting the A bank 11 to the row address buffer 31, a row address which differs only in the least significant bit for selecting the B bank 21 is automatically generated with a certain delay. Is the same as that of the DRAM of FIG. The timing t
If the column address BY for the B bank 21 is supplied at the next fall timing of / CAS without falling of / RAS after ₁ , both the banks A and B 11 and 21 in the frame access mode are set in the page mode. You can access without interruption.

Now, in the DRAM of FIG. 4, N lines × n
Frame access and odd /
In each of the even-numbered field accesses, N / 2 row addresses are sequentially read from the row address buffer 3 from the outside.
I had to take it into 1. Therefore, improvement in access speed is limited. In addition, since the address supplied from the outside must be changed at high speed and frequently, power consumption increases due to the wiring capacitance of the address input pin. On the other hand, in the DRAM of FIG. 16, since one row address AX only needs to be taken into the row address buffer 31, the access speed is further improved. In addition, the frame access of a block having a size of N lines × n pixels can be realized only by supplying a 12-bit address for controlling each of the three address counters 15, 25, and 36 from the outside. Reduction is possible. The same applies to odd / even field accesses.

When the size of the block is limited to, for example, four types, the parameters relating to the size of the block are set according to Table 1 on the basis of information supplied from outside through the two address input pins A ₉ and A _10. It can also be generated.

[0057]

[Table 1]

It should be noted that the above configuration in which pixel data in one block can be accessed at high speed and with low power consumption using the row address counter and the column address counter is not limited to the two-bank configuration shown in FIG. The present invention is also applicable to an image data memory such as a bank configuration.

(Embodiment 7) FIG. 19 shows one example of a two-bank image data memory according to a seventh embodiment of the present invention.
It is a block diagram of DRAM of a chip. DRA in FIG.
M is a modification of the bank selection method in the DRAM of FIG. Only the odd field data (odd 1, odd 2, odd 3, odd 4,...) In one frame data are stored in the A bank 11, and only the even field data (even 1, even 2, even 3, even 4,...) Are stored. The points stored in the B banks 21 are as shown in FIG.
6 is the same as that of the DRAM.

In FIG. 19, reference numeral 31 denotes both banks 11 and
1 is a row address buffer common to 36, 36 is both banks 1
A row address counter common to 1 and 21, 13 is a row decoder for A bank 11, and 23 is a row decoder for B bank 21. 37 is both banks 11,
A column address buffer common to 21, 38 is a column address counter common to both banks 11 and 21, 16 is A
Column decoder for bank 11, 26 bank B
1 is a column decoder.

The capacity of the DRAM shown in FIG. 19 is 16 Mb, and the A and B banks 11 and 21 each have a configuration of 1 Mb × 8. When a block of N lines × n pixels (for example, N = 4, n = 8) related to the frame access starts from the A bank 11, RA1 is supplied as the row address X and CA1 is supplied as the column address Y from the outside.
The block related to the frame access is stored in the B bank 21.
, RB1 is supplied from the outside as the row address X, and CB1 is supplied from the outside as the column address Y. RA1 and RB1 are 12 bits, the least significant bit (LSB) of RA1 is 0, and the LSB of RB1 is 1. CA1 and CB1 each have 10 bits,
The most significant bit (MSB) of 1 is 0, and the MSB of CB1 is 1
It is. The MSBs of CA1 and CB1 are added to a 9-bit column selection address for bank selection.

The row address X supplied from the outside is taken into the row address buffer 31. The row address counter 36 sequentially increments the input addresses of the row decoders 13 and 23 with the acquired row address X as an initial value. This row address counter 36
In, carry from the LSB to the upper 11 bits is permitted. The LSB of the count value of the row address counter 36 is given as a bank select signal, and the upper 11 bits of the count value are given to both row decoders 13 and 23 as a row select address. The row decoder 13 includes a row address counter 3
6 operates on the condition that the LSB of the count value of the counter 6 is 0.
One of the word lines in bank 11 is selected. The row decoder 23 calculates the count value L of the row address counter 36 as L.
The operation is performed on the condition that SB is 1, and one of the word lines of the B bank 21 is selected according to the upper 11 bits of the count value.

The column address Y supplied from the outside is
The data is taken into the column address buffer 37. The column address counter 38 stores the acquired column address Y
Is used as an initial value, the input addresses of the column decoders 16 and 26 are sequentially incremented. When the count value of the column address counter 38 reaches a predetermined value, the column address Y is reset in the column address counter 38. However, the carry from the lower 9 bits to the MSB is prohibited in the column address counter 38, and the MSB is inverted every time the column address Y is reset.
The MSB of the count value of the column address counter 38 is given as a bank select signal, and the lower 9 bits of the count value are given to both column decoders 16 and 26 as a column select address. The column decoder 16 operates on the condition that the MSB of the count value of the column address counter 38 is 0. According to the lower 9 bits of the count value, the column decoder 16 operates on the selected word line of the A bank 11. Select one of the memory cells. The column decoder 26 operates under the condition that the MSB of the count value of the column address counter 38 is 1, and according to the lower 9 bits of the count value, the selected word line of the B bank 21 Select one of the memory cells.

According to this embodiment, a single row address X
And a single column address Y from the outside, line data in one block can be continuously accessed in the order of “odd 1, even 1, odd 2, even 2”. When starting from “even 1”, the carry from the LSB to the upper 11 bits occurs in the row address counter 36 instead of “even 1, odd 1, even 2, odd 2”. , Odd 2, even 2, odd 3 ", the line data can be successively accessed.

In the case of an odd field access, the LSB of the count value of the row address counter 36 is fixed to 0, and the upper 11 bits thereof are sequentially incremented by one. The MSB of the count value of the column address counter 38 is fixed to 0, and the lower 9 bits are sequentially set to 1
It is incremented by one. In the case of even field access, the LSB of the count value of the row address counter 36 is used.
Is 1, the MSB of the count value of the column address counter 38
Are respectively fixed to 1.

(Embodiment 8) FIG. 20 shows one embodiment of an image data memory having a two-bank configuration according to an eighth embodiment of the present invention.
It is a block diagram of a synchronous DRAM of a chip. The configuration of FIG. 20 embodies the configuration of a sequence control circuit for controlling the operations of the row address counter and the column address counter in the DRAM of FIG.
However, in this embodiment, the row address buffer 31 and the column address buffer 37 in FIG. In the following description, N
A mode of frame access for a block having a size of line × n pixels is called a block access mode. Also,
The number n of pixel data to be accessed on one line is called a burst length.

In FIG. 20, 84 is a control signal buffer, 85 is a command decoder, 86 is a mode set register, 87 is a column address counter control circuit, 88 is a burst length control counter, 89 is a block access control circuit, and 90 is an internal stage. The control circuit 91 is a precharge circuit.

The mode data, the row address, and the column address are supplied to the address buffer 81 through the address input pins in a time-division manner. Address buffer 81
The mode set register 8 stores the mode data, row address and column address supplied from the outside.
6, to the row address counter 36 and the column address counter control circuit 87.

The control signal buffer 84 includes a clock signal CLK and a row address strobe signal supplied from outside.
/ RAS, column address strobe signal / CAS and write enable signal / command signal CM corresponding to WE
Generate D. In response to the command signal CMD from the control signal buffer 84, the command decoder 85 outputs the mode set register setting signal MRS and the row initial value load signal E
An NTBAM1 and a column initial value load signal LDH are generated. / RAS, / C at rising edge of CLK
If both AS and / WE are at the “L” level, the external address ADR fetched into the address buffer 81 is stored as mode data in the mode set register 86 that has received the MRS. If / RAS is at the “L” level and / WE is at the “H” level at the rising timing of CLK, the external address ADR fetched into the address buffer 81 is set as the row initial address and ENTB
AM1 is received and stored in the row address counter 36. If / CAS is at the “L” level and / WE is at the “H” level at the rising edge of the CLK, the external address ADR captured by the address buffer 81 is supplied to the column address counter control circuit 87 via the column address counter control circuit 87. It is stored in the address counter 38. On this occasion,
Column address counter control circuit 87 receiving LDH
Sets the external address ADR supplied from the address buffer 81 as the column initial address ICA in the column address counter 38 and stores the column initial address ICA.

The mode set register 86 sends a block access mode enable signal BLKEN for instructing continuous access to pixel data in one block to the block access control circuit 89 to send a parameter signal relating to the block size (N lines × n pixels). It is supplied to the burst length control counter 88, respectively.

Burst length control counter 88 counts internal clock signal ICLK0 generated from external clock signal CLK after the count value is reset to 0 in response to column initial value load signal LDH from command decoder 85. . Count value CRNX of burst length control counter 88
T is sequentially supplied to the block access control circuit 89. The burst length control counter 88 sets the carry signal CRO every time the page access of the burst length n is completed.
The UT is generated, and at the end of the last page access, the block carry signal BLKCR is generated together with the carry signal CROUT. CROUT and BLKCR are
It is supplied to the block access control circuit 89.

The block access control circuit 89 supplies a precharge control signal CR to be supplied to the precharge circuit 91.
APRE, a column initial value reload signal BLDH to be supplied to the column address counter control circuit 87, a row address update signal ENTBAM2 to be supplied to the row address counter 36, and a burst stop signal CR to be supplied to the internal stage control circuit 90. And a circuit for respectively generating. The internal configuration of the block access control circuit 89 will be described later.

The internal stage control circuit 90 is a circuit for generating a column address update signal I1D to be supplied to the column address counter 38. However, when receiving the burst stop signal CR from the block access control circuit 89, the generation of I1D is stopped.

The precharge circuit 91 receives the precharge control signal CRAPR from the block access control circuit 89.
A circuit for alternately precharging the A bank 11 and the B bank 21 according to E and the LSB of the row address from the row address counter 36. At this time, the B bank 21 is precharged while the A bank 11 is being accessed, and the A bank 11 is precharged while the B bank 21 is being accessed.

The column address counter control circuit 87
When the column initial value reload signal BLDH is supplied from the block access control circuit 89, the stored column initial address ICA is reset in the column address counter 38.

The internal clock signal ICLK0 is supplied not only to the burst length control counter 88 but also to a block access control circuit 89, an internal stage control circuit 90 and the like. The internal stage control circuit 90 is also supplied with another internal clock signal for a pipeline operation of a plurality of stages. However, FIG. 20 shows the supply of ICLK0 only to the burst length control counter 88 and the block access control circuit 89 for simplification of the drawing.

FIG. 21 shows a block access control circuit 89.
FIG. 2 is a block diagram showing an internal configuration of the device. In FIG.
92 is a first shift register, 93 is a second shift register, 94 is a carry signal inhibit circuit, 95 is an inverter, 96 is a CR generation circuit, 97 is a BLDH generation circuit, 9
8 is an ENTBAM2 generation circuit. Carry signal inhibit circuit 94 is formed of a flip-flop having a set terminal, a reset terminal, and an enable terminal.

First and second shift registers 92 and 93
Is supplied with an internal clock signal ICLK0. First
Shift register 92 includes a burst length control counter 88.
A signal obtained by delaying carry signal CROUT from
The signal is supplied to the generation circuit 96 and the BLDH generation circuit 97. Further, the first shift register 92 carries the carry signal CRO.
By delaying the UT, the precharge control signal C
Generate RAPRE. The second shift register 93 is
A signal obtained by delaying the block carry signal BLKCR from the burst length control counter 88 is transferred to a carry inhibit circuit 94.
Supply to the reset terminal. A column initial value load signal LDH from the command decoder 85 is supplied to a set terminal of the carry inhibition circuit 94. Carry prohibition circuit 9
4 is provided with a block access mode enable signal BLKEN from the mode set register 86.
Is supplied.

Carry inhibit circuit 94 outputs a signal BLKEX indicating that block access is being executed. This signal BLKEX (block access execution signal)
Is supplied to the CR generation circuit 96 via the inverter 95. The CR generation circuit 96 generates the burst stop signal CR in response to the delayed carry signal CROUT from the first shift register 92 only when BLKEX is at "L" level. The BLDH generation circuit 97 has a BL
Only when KEX is at "H" level, delayed carry signal CROUT from first shift register 92 is output.
, A column initial value reload signal BLDH is generated. The ENTBAM2 generating circuit 98 outputs the count value output CRNXT (for example, CRNXT0 to CRNXT0) of the burst length control counter 88 only when BLKEX is at “H” level.
CRNXT3), and generates a row address update signal ENTBAM2 at a desired timing.

Next, a data read operation of a block of 4 lines × 8 pixels (see FIG. 19) in the synchronous DRAM of FIG. 20 will be described. FIGS. 22 (a) to 22 (k), FIGS. 23 (a) to 23 (k), and FIG.
(A) to (k), FIGS. 25 (a) to (l), and FIG.
(A) to (l). Cycles 1 to 40 are shown in these figures. Mode set register 86
It is assumed that required mode data is stored in advance through the address buffer 81. Where N = 4,
n = 8. Block access mode enable signal BLKEN is at "H" level. Both the RAS-CAS delay t _RCD and the CAS latency t _CAC are 3
It is assumed to be a clock.

At the rising timing of the external clock signal CLK in cycle 1, the external address RA1 is supplied together with the row address strobe signal / RAS of "L". The command decoder 85 includes a row address counter 3
6 is supplied with a row initial value load signal ENTBAM1.
As a result, the address RA1 supplied from the outside is set in the row address counter 36, and the row address RA1 output from the row address counter 36 is latched by the two row decoders 13 and 23. At this time, RA1
Since (LSB = 0) is an address specifying the A bank 11, the row decoder 13 operates to select one word line of the A bank 11.

At the rising timing of the external clock signal CLK in cycle 4 after t _RCD , the external address CA is output together with the column address strobe signal / CAS of “L”.
1 is given. The command decoder 85 performs cycle 4
In the first half, the column initial value load signal LDH is supplied to the column address counter control circuit 87, the burst length control counter 88, and the block access control circuit 89. As a result of the LDH being supplied to the column address counter control circuit 87, an externally supplied address CA1 is set in the column address counter 38, and the column address CA1 output from the column address counter 38 is supplied to the two column decoders 16 and 26. Supplied to At this time, CA1
Since (MSB = 0) is an address designating the A bank 11, the column decoder 16 operates to select one memory cell on the selected word line of the A bank 11. The data DA1-1 stored in the memory cell becomes output data of the synchronous DRAM at the rising timing of the external clock signal CLK in cycle 7 after t _CAC .

The burst length control counter 88 is reset to 0 when the column initial value load signal LDH is supplied, and then starts counting the internal clock signal ICLK0. Block access mode enable signal BLKE
Since N is at “H” level, carry signal inhibit circuit 94
Sets the block access execution signal BLKEX to "H" level when the column initial value load signal LDH is supplied. As a result, even if carry signal CROUT is output from burst length control counter 88, CR generation circuit 96 is prohibited from generating burst stop signal CR.
If BLKEN is at “L” level, BLKEX holds “L” level, so that generation of burst stop signal CR in CR generating circuit 96 is not prohibited.

The internal stage control circuit 90 sends the column address update signal I1D to the column address counter 38 every clock until the burst stop signal CR is supplied.
Continue to supply. As a result, the column address counter 3
8 output column addresses from CA1 to CA2,
CA3,... Are sequentially updated, and output data DA1-2, DA1-3,. On the other hand, when the data reading of the burst length n is almost completed, the burst length control counter 88 sets the carry signal CRO
Output UT. More specifically, as shown in FIG.
Is output over the first half. First shift register 92
Is the precharge control signal CRAPRE in cycle 11
And the BLDH generation circuit 97 outputs the column initial value reload signal BLDH in the first half of the cycle 12, respectively. E
The NTBAM2 generation circuit 98 determines the burst length n and RAS-
Considering the CAS delay t _RCD , the cycle _12-3
A row address update signal ENTBAM2 is output before the cycle, that is, in cycle 9. That is, in cycle 9, the count value of the row address counter 36 is updated to RB1 in time for the operation after cycle 12. Then, in cycle 12, the column initial value reload signal BLD
When H is supplied to the column address counter control circuit 87, the column address counter control circuit 87 sets CB1 in the column address counter 38. At this time, the column address counter control circuit 87 inverts the stored most significant bit of CA1 to perform CB
Get 1.

When the access of the column address CA8 related to the row address RA1 is completed in the cycle 11, the accesses of the column addresses CB1 to CB8 related to the next row address RB1 are executed in the cycles 12 to 19. Similarly, in cycles 20 to 27, access to column addresses CA1 to CA8 related to row address RA2 is performed, and in cycles 28 to 35, access to column addresses CB1 to CB8 related to row address RB2 is performed. In response to the above operation, in cycles 7 to 14, the output data DA1-1 to DA1-8 of bank A are output in cycles 15 to
At 22, the output data DB1-1 to DB1-8 of the B bank
However, in cycles 23 to 30, output data DA of bank A
2-1 to DA2-8, and in cycles 31 to 38, output data DB2-1 to DB2-8 of bank B are obtained, respectively.

When the reading of the data of the number of lines N is almost completed in the middle of the above series of operations, the burst length control counter 88 outputs the block carry signal BCKCR together with the carry signal CROUT. Specifically, FIG.
As shown in FIG. 5 (h), BLKCR is output from the second half of cycle 26 to the first half of cycle 27. The second shift register 93 outputs the block carry signal BLKC
The signal whose R is delayed is supplied to the reset terminal of the carry inhibition circuit 94. As a result, in the first half of cycle 28, B
The LDH generation circuit 97 outputs the column initial value reload signal BLD.
After outputting H, the block access execution signal BLKE
X is reset to "L" level. Thus, B
When LKEX becomes “L” level, the CR generation circuit 96 is permitted to generate the burst stop signal CR, and the BLDH generation circuit 97 and the ENTBAM2 generation circuit 98 are prohibited from operating. Then, from the second half of the cycle 34 to the cycle 35
When the carry signal CROUT is output from the burst length control counter 88 in the first half of the period, the burst generation signal 96 is generated by the CR generation circuit 96 in the cycle 35 as shown in FIG. In response, internal stage control circuit 90 stops supplying column address update signal I1D to column address counter 38.

FIG. 27 is a flowchart showing the above operation in the case where the number of lines is N and the burst length is n. Of the steps S21 to S31, n1 (= nt _RCD -1) referred to in step S25 is used for controlling the output timing of the row address update signal ENTBAM2. N2 (= n-1) referred to in step S30
Is used for end control of one-line access, and n3 (= N-1) referred to in steps S26 and S31 is used for end control of block access.

As described above, according to this embodiment, a single row address and a single column address are set to / RAS and
The line data in the block at an arbitrary position can be continuously accessed only by supplying from outside together with / CAS.

[0089]

As described above, according to the present invention, the image data memory is constituted by at least two banks, the way of storing pixel data in each bank is devised, and one bank is accessed. Since other banks are precharged during the operation, continuous access to line data is realized, and as a result, the access speed of the image data memory is improved.

Further, by introducing a row address counter and a column address counter, high speed and low power consumption block access can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a two-bank image data memory (DRAM) according to a first embodiment of the present invention.

FIGS. 2A to 2D are timing charts showing a data reading method in a frame access mode of the DRAM of FIG. 1;

3 is a sequence diagram showing an access procedure of the DRAM of FIG. 1, wherein (a) corresponds to each mode of frame access, (b) corresponds to each mode of odd field access, and (c) corresponds to each mode of even field access. .

FIG. 4 is a block diagram of a two-bank image data memory (DRAM) according to a second embodiment of the present invention.

FIGS. 5A to 5D are timing charts showing a data reading method in the frame access mode of the DRAM of FIG. 4;

FIG. 6 is a block diagram of an image data memory system including a two-bank image data memory (DRAM) according to a third embodiment of the present invention.

FIG. 7 is a flowchart showing a method of reading a DRAM by a processor in FIG. 6;

8 is a sequence diagram showing a DRAM access procedure by the processor in FIG. 6, wherein (a) corresponds to each mode of frame access, (b) corresponds to an odd field access, and (c) corresponds to an even field access mode. Things.

FIG. 9 is a graph showing the effect of improving the DRAM read speed in the frame access mode of the image data memory system of FIG. 6;

FIG. 10 is a block diagram of a 4-bank image data memory (DRAM) according to a fourth embodiment of the present invention.

FIGS. 11A and 11B are sequence diagrams showing an access procedure of the DRAM of FIG. 10, wherein FIG.
In the figure, (c) corresponds to each mode of odd field access, and (c) corresponds to each mode of even field access.

12 is a graph showing the effect of the number of banks on the chip area in the DRAM of FIG.

FIG. 13 is a graph showing that the DRAM read speed in the frame access mode is further improved by the DRAM configuration of FIG. 10 (fourth embodiment) as compared with the case of the third embodiment.

FIG. 14 is a block diagram of an image data memory (DRAM) having a two-bank configuration according to a fifth embodiment of the present invention.

15A and 15B are sequence diagrams showing an access procedure of the DRAM of FIG. 14, wherein FIG.
In the figure, (c) corresponds to each mode of odd field access, and (c) corresponds to each mode of even field access.

FIG. 16 is a block diagram of a two-bank image data memory (DRAM) according to a sixth embodiment of the present invention.

FIG. 17 is a flowchart illustrating the operation of a row address counter and a column address counter in the DRAM of FIG. 16;

FIGS. 18A to 18C are timing charts showing a parameter setting method for accessing the DRAM of FIG. 16;

FIG. 19 is a block diagram of a two-bank image data memory (DRAM) according to a seventh embodiment of the present invention.

FIG. 20 is a block diagram of a two-bank image data memory (synchronous DRAM) according to an eighth embodiment of the present invention.

21 is a block diagram showing an internal configuration of a block access control circuit in the synchronous DRAM of FIG.

22 (a) to (k) show synchronous D in FIG.
FIG. 4 is a timing chart showing a data reading method in a block access mode of a RAM.

23 (a) to (k) show synchronous D of FIG.
FIG. 22 is a timing chart showing a method of reading data in the block access mode of the RAM, which is shown in FIGS.
It represents the period following (k).

24 (a) to (k) show synchronous D of FIG.
FIG. 23 is a timing chart showing a method of reading data in the block access mode of the RAM, which is shown in FIGS.
It represents the period following (k).

25 (a) to (l) show synchronous D in FIG.
FIG. 24 is a timing chart showing a method of reading data in the block access mode of the RAM, which is shown in FIGS.
It represents the period following (k).

26 (a) to (l) show synchronous D of FIG.
FIG. 26 is a timing chart showing a method of reading data in the block access mode of the RAM, which is shown in FIGS.
This represents a period following (l).

FIG. 27 is a flowchart showing an operation of a row address counter and a column address counter in the synchronous DRAM of FIG. 20;

FIG. 28 is a diagram illustrating a state of data storage in a conventional image data memory (DRAM) and three types of access modes.

29 is a sequence diagram showing an access procedure of the DRAM of FIG. 28, where (a) is a frame access and (b)
In the figure, (c) corresponds to each mode of odd field access, and (c) corresponds to each mode of even field access.

[Explanation of symbols]

11 A bank memory cell array (first memory area) 12, 22, 31 Row address buffer 13, 23 Row decoder 14, 24, 37 Column address buffer 15, 25, 38 Column address counter 16, 26 Column decoder 21 B bank Memory cell array (second memory area) 35 word line selection circuit 36 row address counter 40 DRAM (image data memory) 41 memory cell array of A bank (first memory area) 42 memory cell array of B bank (second memory) Area) 50 processor 51 CPU 52 SRAM (buffer memory) 53 DMAC 61 memory cell array of A bank (first memory area) 62 memory cell array of B bank (second memory area) 63 memory cell array of C bank (third memory area) Note Memory cell array of D bank (fourth memory area) 71 memory cell array of A bank (first memory area) 72 memory cell array of B bank (second memory area) 81 address buffer 84 control signal buffer 85 Command decoder (first means, second means) 86 mode set register 87 column address counter control circuit (third means) 88 burst length control counter (fifth means, eighth means) 89 block access control circuit (Sixth means, seventh means, ninth means) 90 Internal stage control circuit (fourth means) 91 precharge circuit 92, 93 shift register 94 carry signal inhibit circuit (ninth means, second Circuit) 95 inverter 96 CR generation circuit (ninth means, first circuit) 97 BLDH generation circuit ( Sixth Means) 98 ENTBAM2 Generation Circuit (Seventh Means) 101 DRAM (Image Data Memory) BLDH Column Initial Value Reload Signal BLKCR Block Carry Signal BLKEN Block Access Mode Enable Signal / CAS Column Address Strobe Signal CR Burst Stop Signal CRAPRE Precharge control signal CROUT Carry signal ENTBAM1 Row initial value load signal ENTBAM2 Row address update signal I1D Column address update signal LDH Column initial value load signal / RAS Row address strobe signal

Continuation of the front page (56) References JP-A-61-233495 (JP, A) JP-A-5-151177 (JP, A) JP-A-4-259998 (JP, A) JP-A-63-136394 (JP) , A) JP-A-64-76496 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/40-11/41

Claims (10)

(57) [Claims] A first memory area for storing odd-numbered line data of the odd-numbered field data in the frame data and an even-numbered line data of the even-numbered field data; A second memory area for storing the odd-numbered line data and the even-numbered line data of the odd field data; and one of the first and second memory areas. An image data memory comprising, on the same chip, a peripheral circuit for alternately accessing the first and second memory areas while precharging the other memory area during access. . 2. An image data memory system comprising: the image data memory according to claim 1; and a processor that manages data transfer between the image data memory and the image data memory, wherein the processor temporarily stores data. Transfer of odd-numbered line data of the odd-numbered field data between the buffer memory and the first memory area, and odd-numbered of the even-numbered field data between the second memory area Transfer of line data, transfer of even-numbered line data of even-numbered field data between the first memory area and the buffer memory, and odd-numbered data between the second memory area. Transfer of the even-numbered line data of the field data and the even-numbered line data of the even-numbered field data with the buffer memory. Image data memory system characterized by comprising a control circuit for sequentially executing the transfer of data. 3. A first memory area for storing odd-numbered line data of odd field data in frame data, and a second memory area for storing odd-numbered line data of even field data. A third memory area for storing even-numbered line data of odd field data, a fourth memory area for storing even-numbered line data of even field data, While accessing one of the first to fourth memory areas while precharging another one of the memory areas, at least two of the first to fourth memory areas are precharged. Peripheral circuits for sequentially accessing the two memory areas are provided on the same chip, and in the frame access mode, the first to fourth memory areas are provided .
Area is accessed sequentially, odd field access mode
In the first and third memory areas are accessed alternately.
And in the even field access mode,
And the fourth memory area are alternately accessed
Image data memory, characterized in that the. 4. A first memory area for storing the odd-numbered line data of the odd-numbered field data in the frame data and the odd-numbered line data of the even-numbered field data on the same word line. A second memory area for storing even-numbered line data of the odd-numbered field data and even-numbered line data of the even-numbered field data on the same word line; and the first and second memory areas. A peripheral circuit for alternately accessing the first and second memory areas is provided on the same chip while precharging the other memory area while accessing one of the memory areas. An image data memory, comprising: 5. A first memory area for storing odd field data in frame data, a second memory area for storing even field data, and among the first and second memory areas. Image data comprising, on the same chip, a peripheral circuit for alternately accessing the first and second memory areas while precharging the other memory area while accessing one of the memory areas A memory, wherein the peripheral circuit is configured such that a row address supplied from the outside is initialized as a binary count value, and is sequentially updated while being allowed to carry from the least significant bit to a plurality of upper bits. A counter, and the least significant bit of the count value of the row address counter is 0.
And a first row decoder for selecting a word line of the first memory area in accordance with a plurality of upper bits of a count value of the row address counter, and a total of the row address counter. The least significant bit of the number is 1
The condition that is, and in accordance with the upper multiple bits of the count value of the row address counter, and the second second row decoder for selecting the word lines of the memory area, the column supplied from the outside If the address is a binary count and
Initialized, from lower multiple bits to most significant bit
The count value is updated sequentially while carry is prohibited, and
Inverts the most significant bit every time the number of updates reaches a predetermined value.
Column address count that resets the column address
And the most significant bit of the count value of the column address counter is
0 and the column address
The first counter according to a plurality of lower bits of the counter value of the counter.
Select a memory cell on the selected word line in the memory area
A first column decoder and the most significant bit of the count value of the column address counter.
1 and the column address
In response to the plurality of lower-order bits of the counter value, the second
Select a memory cell on the selected word line in the memory area
And a second column decoder for performing the operation. 6. The image data memory according to claim 5 , wherein each time the number of updates of the column address counter reaches a predetermined value, the peripheral circuit responds to the least significant bit of the count value of the row address counter. An image data memory further comprising a circuit for generating a precharge control signal so that alternate precharge of the first and second memory areas is performed. 7. A memory area for storing one frame of image data composed of an odd field and an even field, and row addresses are successively generated so as to sequentially designate at least a part of word lines of the memory area. Address counter for sequentially generating at least a part of memory cells on the specified word line, and a column address counter for continuously generating a column address so as to sequentially specify the memory cells on the specified word line. Operation of the row address counter and the column address counter provided on the same chip and a sequence control circuit for controlling the sequence control circuit, said row address mosquito row address supplied from the outside
Counter to be loaded as the default value.
Generate row initial value load signal from strobe signal
And a column address externally supplied to the column address.
Column to be loaded into the counter as an initial value
Column initial value load signal from address strobe signal
Second means for generating, and loading as an initial value into the column address counter.
A third means for storing the column address, and a command for updating the column address counter.
Fourth means for generating a column address update signal, and when the number of updates of the column address counter reaches a predetermined value.
Fifth means for generating a carry signal when
And when the carry signal is generated by the fifth means.
Means that the column address stored in the third means is
The column address counter is loaded so that
Sixth means for generating a system initial value reload signal, and a decoding result of the count value of the column address counter.
Accordingly, the update of the row address counter is commanded.
Means for generating a row address update signal
The number of updates of the row address counter has reached a predetermined value
Sometimes an eighth signal to generate the block carry signal
Means, and a block carry signal is generated by said eighth means.
The column address update signal by the fourth means.
Ninth means for stopping generation of a signal.
One, the ninth means, responsive to the carry signal generated by said fifth means
And generating the column address update signal in the fourth means.
A second step to generate a burst stop signal to stop
1 and the block access mode enable signal is given.
The column initial value generated by the second means.
Burst stop by the first circuit in response to a load signal
Generation of the stop signal is prohibited, and the stop signal is generated by the eighth means.
The first circuit in response to the applied block carry signal
To allow generation of a burst stop signal by the
An image data memory comprising a circuit . 8. The image data memory according to claim 7 , wherein the row address counter and the column address counter are respectively controlled by the sequence control circuit so as to start a counting operation using an address supplied from outside as an initial value. An image data memory characterized by being performed. 9. The image data memory according to claim 7 , wherein the row address counter and the column address counter each terminate the counting operation according to a parameter relating to the size of the rectangular access area supplied from outside. An image data memory controlled by a circuit. 10. The image data memory according to claim 7 , wherein the row address counter and the column address counter each perform a counting operation in accordance with a parameter internally generated based on information on the size of a rectangular access area supplied from outside. The image data memory is controlled by the sequence control circuit so as to end the operations.