KR20070053010A - Method for fabricating fuse in semiconductor devices - Google Patents

Abstract

The present invention relates to a method for manufacturing a fuse of a semiconductor device. The disclosed method provides a semiconductor substrate. A fuse, a pad, and a metal wiring are formed on the semiconductor substrate at the same level, and a capping pattern is formed on the uppermost layer of the fuse, the pad, and the metal wiring. An interlayer insulating film is formed on the substrate having the fuse, pad and metal wiring. The interlayer insulating layer is selectively etched to form a via hole exposing the metal wiring and a preliminary fuse window exposing the fuse. The capping pattern of the fuse and the capping pattern of the metal wiring are selectively removed. A passivation film is formed on the substrate having the via hole and the preliminary fuse window. The passivation film is selectively etched to form respective pad windows and fuse windows exposing the pad and the fuse from which the capping pattern has been removed.

Description

Method for fabricating fuse in semiconductor devices

1A to 1E are cross-sectional views illustrating processes for manufacturing a fuse of a semiconductor device according to the related art.

2A to 2E are cross-sectional views of processes for describing a method of manufacturing a fuse of a semiconductor device according to the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a fuse of a semiconductor device.

In general, an extra redundancy cell is disposed near a memory cell of a semiconductor device in preparation for a defective memory cell, and the redundancy cell has a structure connected to the memory cell by a fuse disposed adjacent to the memory cell. Have The defective memory cell is found through a test process, and a fuse connected to the defective memory cell is cut through the repair process and replaced with the redundancy cell. The repair process is performed by laser beam irradiation to cut the fuse. The fuses are formed in the same layer as the metal wires of the semiconductor device on the peripheral region. The fuse may have a capping pattern disposed on the uppermost layer. The capping pattern prevents the fuse from corroding by inhibiting a reaction with moisture in the atmosphere.

1A to 1E are cross-sectional views illustrating processes for manufacturing a fuse of a semiconductor device according to the related art.

As shown in Fig. 1A, a semiconductor substrate 1 having a predetermined substructure is provided. The semiconductor substrate 1 may be a silicon substrate in which a fuse region I, a pad region II, and a metal wiring region III are defined. The metallization region III is defined in the ferry region of the cell. A first interlayer insulating film 3 is formed on the semiconductor substrate 1. The first interlayer insulating film 3 may be formed of an oxide film. A first metal film and a first capping film are sequentially formed on the first interlayer insulating film 3. The first metal film may be formed of an aluminum film. The first capping film may be formed by sequentially stacking Ti and TiN films. The first capping layer and the first metal layer may be etched to form respective fuses 7 and pads on the first interlayer insulating layer 3 in the fuse region I, the pad region II and the metal wiring region III. Field 8 and first metal wires 9 are formed. As such, the fuses 7, the pads 8, and the first metal wires 9 may be formed on the same level. The fuses 7 may have a double stacked structure of the first metal pattern 5a and the first capping pattern 6a. Similarly, the pads 8 may be formed in a double stacked structure of the first metal pattern 5b and the first capping pattern 6b. In addition, the first metal wires 9 may be formed in a double stacked structure of the first metal pattern 5c and the first capping pattern 6c.

As shown in FIG. 1B, a second interlayer insulating film 15 is formed on the substrate having the fuses 7, the pads 8, and the first metal wires 9. The second interlayer insulating film 15 may be formed of the same material as the first interlayer insulating film. The second interlayer insulating layer 15 in the metal wiring region III is etched to form a via hole 16 exposing at least a portion of the first metal wirings 9.

As shown in FIG. 1C, a via plug 17 filling the via hole 16 is formed. The via plug 17 may be formed of a tungsten film. A second metal film and a second capping film are sequentially formed on the substrate having the via plug 17. The second capping layer and the second metal layer are selectively etched to form second metal interconnections 21 covering at least a portion of the via plug 17. The second metal wires 21 may be formed in a double stacked structure of the second metal pattern 19 and the second capping pattern 20.

As shown in FIG. 1D, a passivation film 23 is formed on the substrate having the second metal wires 21. The passivation film 23 and the second interlayer insulating film 15 in the fuse region I are etched to form fuse windows 24w1 exposing the fuse. The first capping pattern of the fuses exposed by the fuse windows 24w1 is removed. Since the first capping pattern of the fuses is relatively hard, it is difficult to open the first capping pattern in a subsequent laser repairing process. Therefore, the first capping pattern of the fuses is to be removed using a separate etching gas after the fuse window 24w1 is formed. In FIG. 1D, reference numeral 7 ′ not shown in FIG. 1D illustrates fuses remaining after the first capping pattern is removed.

As shown in FIG. 1E, the passivation film 23 and the second interlayer insulating film 15 in the pad region II are etched to form pad windows 24w2 exposing the pads 8.

However, in such a conventional method, in the opening of the fuse windows and the pad windows, the capping pattern of the fuses must be removed, so that the fuse windows and the pad windows are formed, respectively. Accordingly, there is a problem in that the number of photo processes increases accordingly, resulting in a complicated process.

In order to solve the above problems, an object of the present invention is to provide a fuse manufacturing method of a semiconductor device that can simplify the photo process by opening the fuse window and the pad window at the same time.

In order to achieve the above object, the present invention provides a fuse manufacturing method of a semiconductor device. The method provides a semiconductor substrate. A fuse, a pad, and a metal wiring are formed on the semiconductor substrate at the same level, and a capping pattern is formed on the uppermost layer of the fuse, the pad, and the metal wiring. An interlayer insulating film is formed on the substrate having the fuse, pad and metal wiring. The interlayer insulating layer is selectively etched to form a via hole exposing the metal wiring and a preliminary fuse window exposing the fuse. The capping pattern of the fuse and the capping pattern of the metal wiring are selectively removed. A passivation film is formed on the substrate having the via hole and the preliminary fuse window. The passivation film is selectively etched to form respective pad windows and fuse windows exposing the pad and the fuse from which the capping pattern has been removed.

And selectively removing the capping pattern of the fuse and the capping pattern of the metal wiring, forming a via plug to fill the via hole, and forming a second metal wiring connected to the via plug.

Forming the via plug includes forming a conductive film on a substrate having the via hole, and polishing the conductive film to fill the via hole.

It is preferable that the said conductive film is a tungsten film.

Preferably, the capping pattern is a Ti film and a TiN film that are sequentially stacked.

After forming the pad window and the fuse window, further comprising forming a moisture barrier film on the substrate having the pad window and the fuse window, and selectively etching the moisture barrier film to expose the pad window.

The moisture barrier film is preferably formed of any one of an oxide film and a nitride film.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the length and thickness of the film and the region may be exaggerated for convenience of description. Like numbers refer to like elements throughout.

2A and 2E are cross-sectional views of processes for describing a method of manufacturing a fuse of a semiconductor device according to the present invention.

As shown in Fig. 2A, a semiconductor substrate 51 having a predetermined substructure is provided. The semiconductor substrate 51 may be a silicon substrate in which a fuse region (IV), a pad region (V), and a metal wiring region (VI) are defined. The metallization region VI is defined in the ferry region of the cell. A first interlayer insulating film 53 is formed on the semiconductor substrate 51. The first interlayer insulating film 53 may be formed of an oxide film. A first metal film and a first capping film are sequentially formed on the first interlayer insulating film 53. The first metal film may be formed of an aluminum film. The first capping film may be formed by sequentially stacking Ti and TiN films. The first capping layer and the first metal layer may be etched to form respective fuses 57 and pads on the first interlayer insulating layer 53 in the fuse region IV, the pad region V, and the metal wiring region VI. Field 58 and first metal wires 59 are formed. As such, the fuses 57, the pads 58, and the first metal wires 59 may be formed on the same level. In addition, the fuses 57 may have a double stacked structure of the first metal pattern 55a and the first capping pattern 56a. The pads 58 may be formed in a double stacked structure of the second metal pattern 55b and the second capping pattern 56b. The first metal wires 59 may have a double stacked structure of a third metal pattern 55c and a third capping pattern 56c.

As shown in FIG. 2B, a second interlayer insulating film 65 is formed on the substrate having the fuses 57, the pads 58, and the first metal wires 59. The second interlayer insulating film 65 may be formed of the same material as the first interlayer insulating film. The second interlayer insulating film 65 may be an intermetallic insulating film. The preliminary fuse windows 66w and the via holes 66h exposing the fuses and the first metal wires are etched by etching the second interlayer insulating layer 65 in the fuse area IV and the metal wiring area III. Form. Subsequently, the etching gas is changed to selectively remove the first capping pattern of the fuses exposed by the preliminary fuse windows 66w and the first capping pattern of the first metal wires exposed by the via hole 66h. As described above, the first capping pattern of the fuses must be removed because the film quality is relatively hard and difficult to open in a subsequent laser repairing process. On the other hand, reference numeral 57`, which is not described in FIG. 2B, shows the fuses remaining after the first capping pattern is removed.

As shown in FIG. 2C, a via plug 67 for filling the via hole 66h is formed. The via plug 67 may be formed by forming a via plug conductive film on a substrate having the via hole 66h and then polishing the conductive film. The via plug conductive film may be a tungsten film. While the via plug 67 is formed, the conductive layer may be formed inside the preliminary fuse window 66w. A second metal film and a second capping film are sequentially formed on the substrate having the via plug 67. The second metal film and the second capping film may be formed of the same material as the first metal film and the first capping film. The second metal wires 71 may be formed in a double stacked structure of the second metal pattern 69 and the second capping pattern 70. The second capping layer and the second metal layer are selectively etched to form second metal interconnections 71 covering at least a portion of the via plug 67. The second metal wires 71 may be electrically connected to the first metal wires 59 through the via plug 67. In the process of patterning the second metal wires 71, the conductive film formed in the preliminary fuse window 66w may be removed.

As shown in FIG. 2D, a passivation film 73 is formed on the substrate having the second metal interconnections 71. The passivation film 73 may be formed of any one structure of an oxide film or a double stacked structure of a nitride film and an oxide film. The oxide film may be a high density plasma oxide film. The nitride layer may be formed by a plasma enhanced chemical vapor deposition (PECVD) process. Fuse windows 74w1 and pad windows 74w2 exposing the fuse 57 ′ by etching the passivation film 73 and the second interlayer insulating film 65 in the fuse region IV, the pad region V, and the like. ) At the same time.

As shown in FIG. 2E, a moisture barrier film is formed on the substrate having the fuse windows 74w1 and the pad windows 74w2. The moisture barrier has a shape surrounding the upper surface and the exposed side surface of the fuses 57 ′. The moisture barrier serves to prevent the fuses 57 ′ exposed by the fuse windows 74w1 from being corroded by reacting with moisture in the atmosphere. The moisture barrier layer is etched to form a moisture barrier pattern 75 exposing the pads 58 in the pad windows 74w2. The moisture proof pattern 75 may be formed of an oxide film or a nitride film. As described above, since the moisture proof pattern 75 surrounds the upper surface and some side surfaces of the fuses 74w1, the moisture penetration path in the air may be completely blocked.

According to the present invention, by forming a preliminary fuse window for opening the fuse with the via hole in the metal wiring area, and selectively removes the capping pattern of the fuse exposed by the preliminary fuse window, the fuse window at the time of forming the pad window Can be formed together. Therefore, the present invention also has the advantage that the photo process is simplified once by opening the fuse window and the pad window at the same time. In addition, in the present invention, by forming the moisture-proof pattern to expose the pad while covering the upper surface and some side surface of the fuse, it is possible to prevent the fuse is corroded due to reaction with moisture in the atmosphere. This improves the reliability of the product.

Claims (7)

A fuse, a pad and a metal wiring are formed on the semiconductor substrate at the same level, but the capping pattern is formed on the uppermost layer. Forming an interlayer insulating film on the substrate having the fuse, pad and metal wiring; Selectively etching the interlayer insulating layer to form a via hole exposing the metal wiring, and forming a preliminary fuse window exposing the fuse; Selectively removing the capping pattern of the fuse and the capping pattern of the metal wiring; Forming a passivation film on the substrate having the via hole and the preliminary fuse window, And selectively etching the passivation layer to form respective pad windows and fuse windows exposing the pad and the fuse from which the capping pattern has been removed. The method of claim 1, wherein the capping pattern is a Ti film and a TiN film that are sequentially stacked. The via plug of claim 1, further comprising selectively removing a capping pattern of the fuse and a capping pattern of the metal wiring, and then forming a via plug filling the via hole. And forming a second metal wiring connected to the via plug. 4. The method of claim 3, wherein forming the via plug is Forming a conductive film on the substrate having the via hole, And manufacturing the via hole by polishing the conductive film. The method of manufacturing a semiconductor device according to claim 4, wherein the conductive film is a tungsten film. The method of claim 1, wherein after forming the pad window and the fuse window, Forming a moisture barrier film on the substrate having the pad window and the fuse window; Selectively etching the moisture barrier to expose the pad window. The method of manufacturing a semiconductor device according to claim 6, wherein the moisture proof film is formed of any one of an oxide film and a nitride film.

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