KR20070050668A - Cmos image sensor and method for fabricating thereof - Google Patents

Abstract

The present invention maximizes the efficiency of the photodiode (PD) by increasing the area of the photodiode (PD) to increase the generation of EHP by the light, narrowing the distance between the micro lens (PD) and the photodiode (PD) light ( It is to provide a CMOS image sensor suitable for increasing the EHP generation by minimizing the amount of light lost during light transmission by shortening the transmission distance of the light and a method of manufacturing the same. In the method of manufacturing a CMOS image sensor according to the present invention, a stepped floating diffusion region is formed, a transfer transistor gate is formed on the stepped floating diffusion region, and a pixel gate is formed on the semiconductor substrate. And forming a stepped photodiode formed on one side and an upper portion of the floating diffusion region and extending above the pixel transistor.

Image sensor, photodiode, fluting diffusion

Description

CMOS image sensor and its manufacturing method {CMOS IMAGE SENSOR AND METHOD FOR FABRICATING THEREOF}

1 is a cross-sectional view showing a four-transistor CMOS CMOS sensor manufactured according to the prior art,

2 is a cross-sectional view showing a CMOS image sensor manufactured according to the first embodiment of the present invention;

3 to 19 are process cross-sectional views illustrating a method of manufacturing the CMOS image sensor shown in FIG. 2.

* Explanation of symbols for the main parts of the drawings

11: first conductive semiconductor substrate 12: photo resistor

13 oxide film 14 doped polysilicon (poly-1)

15: LDD oxide film 16: source-drain junction

17 source-drain junction 18 Sub-Contact

19: gate oxide film

20: undoped silicon (poly-2)

21: undoped silicone (poly-3)

20 ': first conductivity type silicon

21 ': second conductivity type silicon

31: photodiode 32: floating diffusion

33: transfer gate 34: reset gate

35: drive gate 36: select gate

37: transfer transistor

38: reset transistor

39: drive transistor

40: select transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a CMOS (Image Complementary Metal-Oxide-Silicon, CMOS) image sensor and a method of manufacturing the same.

The pixel of a conventional CMOS image sensor is composed of one photodiode (PD) and four NMOS, and these four NMOSs are photo-generated charges focused on the photodiode (PD). Transfer transistor (Transfer Tr) for transporting to Floatingg Diffusion (FD), reset the floating diffusion (FD) by setting the potential of the node to the desired value and discharging the charge (Cpd) Reset transistor (Reset Tr), drive transistor (Drive Tr) acting as source follower buffer amplifier (Source Follower Buffer Amplifier), select transistor for addressing by switching (Select transistor: Select Tr).

Among the transistors of the CMOS image sensor, the transfer transistor and the reset transistor use a native NMOSFET, and the drive transistor and the select transistor use a general NMOSFET.

The unit pixel of the CMOS image sensor uses a native NMOSFET to detect light in the visible wavelength range in the photodiode PD and then converts the detected photogenerated charge into floating diffusion FD. The amount transferred to the drive transistor gate Dx is output as an electrical signal at the output terminal Vout.

1 is a cross-sectional view illustrating a 4-transistor CMOS image sensor pixel manufactured according to the related art, and an operation principle thereof is as follows.

In the first step, as the reset transistor is turned on, the output floating diffusion node potential becomes Vdd, and the driver transistor gate Dx node becomes potential Vdd, at which time the select transistor gate Sx The potential of the signal line is detected by turning on the voltage.

In the second step, when light enters the photodiode PD from the outside while the reset gate Rx is turned off, the ERON (Electron-Hole Pair) within the photodiode PD is proportional thereto. Is generated.

In a third step, the potential of the photodiode PD is changed in proportion to the amount of the generated signal charge by the signal charge generated in the photodiode PD.

In the fourth step, when the transfer transistor is turned on at this time, the signal charge accumulated in the photodiode PD is transferred to the floating diffusion node, and the potential of the output floating diffusion node changes in proportion to the amount of signal charge transferred, thereby driving the gate. The node potential is changed to change the source potential of the drive transistor, thereby causing a voltage change of the signal line when the select gate Sx is turned on.

In the fifth step, when the reset gate Rx is turned on again, the potential of the floating diffusion node becomes Vdd, and the operation is repeated.

At this time, the efficiency of the photodiode PD is determined by the amount of EHP generated according to the amount of incident light. In order to increase the generation efficiency of the EHP, the area of the photodiode PD must be increased.

However, in order to obtain a clearer and better image quality, the memory density of pixels must be increased. In order to increase the memory density, a problem arises in that the pixel size must be reduced, in which case the area of the photodiode (PD) is reduced. As a result, a problem arises that the efficiency of the photodiode PD is deteriorated.

The present invention has been made to solve the above problems in the prior art, in particular, by increasing the area of the photodiode (PD) to increase the generation of EHP by light to maximize the efficiency of the photodiode (PD), CMOS image sensor that can increase EHP generation by minimizing the amount of light lost during light transmission by narrowing the distance between micro lens and photodiode (PD) to shorten the transmission distance of light The purpose is to provide a method.

The pixel of the CMOS image sensor of the present invention proposed to achieve the above object is four pixel transistors, which are a transfer transistor, a reset transistor, a driver transistor, and a select transistor, formed in a first conductive semiconductor substrate, and grown on the substrate. A second conductive floating diffusion region formed in the first conductive semiconductor substrate located under the photodiode and located on one side of the floating diffusion region, and formed on one side of the step shape; And a photodiode formed extending over the pixel transistor.

Meanwhile, in a preferred embodiment of the present invention, after implanting the second conductivity type ions into the first conductivity type semiconductor substrate, silicon etching is performed to form a stepped floating diffusion region. Forming a transfer transistor gate over the fusion region, forming a reset transistor gate, a driver transistor gate, and a select transistor gate on the semiconductor substrate, and forming one side and an upper portion of the floating diffusion region above the pixel transistor. A method of manufacturing a CMOS image sensor is provided, comprising forming an extended stepped photodiode.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a CMOS image sensor according to a first exemplary embodiment of the present invention.

The pixel of the CMOS image sensor of FIG. 2 includes four pixel transistors, which are a transfer transistor, a reset transistor, a driver transistor, and a select transistor, and a second conductive formed in the first conductive semiconductor substrate 11 and formed in a step shape grown on the substrate. A floating diffusion (FD) region, a photodiode 31 formed on one side of the step shape and extending above the pixel transistor, and the photodiode 31 is formed of a first conductivity type silicon 20 '. And a second conductivity type silicon 21 'inside the first conductivity type silicon 20' and positioned below the photodiode 31 on one side of the floating diffusion 32. A sub-contact 18 is shown, which is a first conductivity type source-drain junction formed in the first conductivity type semiconductor substrate 11 located.

A photodiode 31 having a depletion layer formed on the pixel transistor as shown in part A of FIG. 2 can occupy a wide photodiode (PD) full factor compared to the same pixel area, thereby increasing the EHP to light. It is possible to increase the efficiency by generating a photodiode 31 formed on the upper portion of the pixel transistor can reduce the loss of light by reducing the transmission distance of the light can increase the EHP generation efficiency.

In addition, the photodiode 31 is formed on the top of the pixel transistor, thereby obtaining a structure capable of increasing the area of the photodiode 31 during the sub-micron process.

3 to 19 are process cross-sectional views illustrating a method of manufacturing the CMOS image sensor illustrated in FIG. 2.

First, as shown in FIG. 3, an ion implantation oxide film 13 is formed on the first conductivity type semiconductor substrate 11, a pattern is formed using a photo resistor 12, and then a second conductivity type ion implantation is performed. .

In this case, the ion implantation performs a high concentration of the second conductivity type ion implantation region, and the second conductivity type ion implantation region later serves as a node of the transfer transistor and is used as the floating diffusion 32 region, thereby providing a photodiode ( In order to increase the junction capacitor capacity with the first conductivity type Sub to sufficiently receive the electrons formed in the PD), high energy is applied during the second conductivity type ion implantation to make the junction depth as deep as possible. High Doping is used to perform the operation.

Next, as shown in FIG. 4, a pattern is formed using the photoresist 12 and silicon etching is performed. At this time, as shown in FIG. 4, silicon etching is performed such that the second diffusion type region previously implanted is formed in a step shape.

Also note that the etching is performed so that the floating diffusion 32 layer remains sufficiently after silicon etching.

Next, as shown in FIG. 5, after performing Vt ion implantation to adjust Vt of the pixel transistors (transfer transistor, reset transistor, drive transistor, and select transistor), an oxide film 13 to be used as a gate oxide film of the pixel transistor is formed.

Next, doped polysilicon (poly-1) 14 for use as the gate of the pixel transistor is deposited as shown in FIG.

Subsequently, a pattern is formed using the photoresist 12 to pattern the pixel gate as shown in FIG. 7, and then the poly-1 14 is etched.

In order to form the source-drain junctions 16 and 17 of the pixel transistors, the pixel transistor regions are patterned with the photoresist 12 as shown in FIGS. 8 and 9, and then ion implantation is performed. .

FIG. 8 shows a lightly doped drain (LDD) NMOS ion implantation (ie, a low doped second conductivity type), and FIG. 9 shows a high doped agent after deposition of LDD oxide 15 and etching of LDD oxide. 2 shows conductive ion implantation.

FIG. 10 shows a first doped ion implanted to form a sub-contact 18 (PMOS transistor other than pixel transistor) that is a first conductivity type source-drain junction. In this case, the LDD PMOS ion implantation (doped first conductivity type) is not shown in the figure, but is performed immediately after the LDD NMOS ion implantation of FIG. 8, and this sub contact is implanted together during the PMOS transistor source-drain ion implantation. This is done by forming a pattern as much as possible.

The sub contact 18 serves as a contact for sharing the doped first conductivity type sub-bias of the photodiode to be formed later.

Next, in order to isolate the pixel transistor and the photodiode, an oxide film 13 is formed thick, and a pattern is formed using the photoresist 12 to etch the oxide film 13 as shown in FIG. 11.

Thereafter, the oxide film 13 is etched as shown in FIG. 12, and the oxide film 13 is etched to expose the side surface of the transfer gate 33 and the silicon surface of the floating diffusion 32 as shown in the portion B. FIG.

Next, as shown in FIG. 13, the gate oxide film 19 is re-formed for the transfer gate oxide film deposition, and then the gate oxide film 19 is etched again as shown in FIG. 14.

In this case, the etching is performed to appropriately adjust the thickness of the oxide layer of the transfer gate 33 as shown in FIG. 14, and at the same time, the etching amount is adjusted to expose the silicon surface of the floating diffusion 32. When performing the etching, the silicon surface is etched to reveal the C part. This portion will then form a contact with the first conductivity type silicon. When etching is performed, the thickness of the transfer gate oxide film is determined as shown in part D. FIG.

Thereafter, as illustrated in FIG. 15, poly-2 (20), which is undoped silicon, is deposited, and then a first conductivity type ion implantation is performed to doping into the first conductivity type.

Next, when the heat treatment is performed, the doped first conductivity type silicon 20 ′ and the high doped first conductivity type bonding layer form buried contacts like the E portion.

When the poly-2 (20) is deposited, the thickness of the poly-2 is formed to be as thin as possible in order to increase the efficiency of the photodiode PD in consideration of the full depletion layer of the photodiode PD to be formed later. .

Thereafter, as shown in FIG. 16, poly-3 (21), which is undoped silicon, is deposited, and then a second conductivity type ion implantation is performed to doping into the second conductivity type.

After the pattern is formed using the photoresist 12 as shown in FIG. 17, the poly-3 (21) is etched, and then the undoped silicon is deposited as shown in FIG. The first conductivity type ion implantation is performed.

Next, a heat treatment process is performed to form a PN junction and depletion layer of the doped first conductivity type silicon and the doped second conductivity type, and then the photoresist 12 is removed as shown in FIG. 19. After the pattern is formed using the etching, a completeness as shown in FIG. 2 may be obtained.

After that, a general contact hole process and a wiring process are performed.

In the above-described embodiment of the present invention, it is more preferable that the first conductivity type is p-type and the second conductivity type is n-type.

Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes within the scope not departing from the technical spirit of the present invention. It should be understood that the present invention encompasses all of the obvious technical spirits to those skilled in the art, including the present invention.

As described above, in the CMOS image sensor of the present invention and a method of manufacturing the same, the area of the photodiode PD is increased to increase the generation of EHP due to light to maximize the efficiency of the photodiode PD, and Provides CMOS image sensor and manufacturing method that increases EHP generation by minimizing the amount of light lost during light transmission by shortening the distance between Micro Lens and photodiode (PD) to shorten the transmission distance of light do. In addition, the photodiode PD is formed on the pixel transistor even for a small pixel size and sub-micron, thereby maximizing the photodiode PD area.

Claims (7)

A pixel transistor composed of a transfer transistor, a reset transistor, a driver transistor, and a select transistor; A second conductivity type diffusion diffusion region formed in the first conductivity type semiconductor substrate and formed in a step shape grown on the substrate; A sub-contact formed under the photodiode and formed in a first conductivity type semiconductor substrate positioned on one side of the floating diffusion region; And And a photodiode formed on one side of the step portion of the second conductive floating diffusion region and extending above the pixel transistor. According to claim 1, And the photodiode comprises a first conductivity type silicon and a second conductivity type silicon formed inside the first conductivity type silicon. According to claim 1, And the transfer transistor is formed between the floating diffusion region and the photodiode. The method according to any one of claims 1 to 3, The first conductivity type is a p-type conductivity type, the second conductivity type CMOS image sensor, characterized in that the n-type conductivity. Implanting second conductivity type ions into the first conductivity type semiconductor substrate and then performing silicon etching to form a stepped floating diffusion region; Forming a transfer transistor gate over the stepped floating diffusion region, and forming a reset transistor gate, a driver transistor gate, and a select transistor gate on the semiconductor substrate; Forming a sub-contact under the photodiode and inside the substrate that is one side of the floating diffusion region; And And forming a stepped photodiode formed on one side and an upper portion of the floating diffusion region and extending to an upper portion of the pixel transistor. The method of claim 5, Forming the photodiode, Forming an oxide film on the entire substrate, forming a pattern using a photoresist, and then etching the oxide film enough to form a photodiode; Performing oxide etching to expose one side of the transfer transistor gate and the silicon surface of the floating diffusion region; After reforming the gate oxide layer, performing oxide etching to expose the silicon surface of the floating diffusion region; After depositing the undoped silicon, implanting the first conductivity type ions to produce a low doped first conductivity type silicon; After depositing the undoped silicon, implanting the second conductivity type ions to produce the doped second conductivity type silicon; After performing the second conductivity type silicon etching, depositing undoped silicon, and implanting the first conductivity type ions to generate the doped first conductivity type silicon; Performing a heat treatment process to form a PN junction and deflation layer of the doped first conductivity type silicon and the doped second conductivity type silicon; And And forming a stepped photodiode extended to an upper portion of the pixel transistor by performing silicon etching. The method according to claim 5 or 6, The first conductivity type is a p-type conductivity type, the second conductivity type is a manufacturing method of the CMOS image sensor, characterized in that the n-type conductivity.

Images