KR20070045653A - Display device - Google Patents

Abstract

The present invention relates to a display device. The display device according to the present invention includes a first pixel, a second pixel, and a third pixel defined by a plurality of gate lines and a plurality of data lines, respectively, wherein the first to third pixels each include a light emitting element, and First and second driving transistors connected to the light emitting device, and first and second switching transistors transmitting data signals to the first and second driving transistors, wherein the first pixel is connected to the light emitting device. It further comprises a third driving transistor.

Organic light emitting display, luminous efficiency, driving transistor, compensation circuit, channel length

Description

Display device {DISPLAY DEVICE}

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of a display device according to an exemplary embodiment of the present invention.

3 is a layout view of a display device according to an exemplary embodiment of the present invention.

4 and 5 are cross-sectional views of the display device shown in FIG. 3 taken along lines IV-IV and V-V.

6 is a schematic diagram of an organic light emitting diode of a display device according to an embodiment of the present invention.

<Description of Drawing>

85: connecting member

110: substrate 124a-e: control terminal electrode

125: protrusion 126, 176, 178: electrode member

140: insulating film 154a-e, 155: semiconductor

163a-e, 165a-e: contact member 173a-e: input terminal electrode

175a-e: output terminal electrode 180: protective film

184, 185a-c: contact hole 191: pixel electrode

270: common electrode 300: display panel

361: partition 370: organic light emitting member

400: scan driver 500: data driver

600: signal controller

The present invention relates to a display device, and more particularly, to an organic light emitting display device.

Recently, there is a demand for weight reduction and thinning of a monitor or a television, and according to such a demand, a cathode ray tube (CRT) has been replaced by a liquid crystal display (LCD).

However, the liquid crystal display device requires not only a separate backlight as a light emitting device, but also has many problems in response speed and viewing angle.

Recently, as a display device capable of overcoming such a problem, an organic light emitting diode display (OLED display) has attracted attention.

The organic light emitting diode display includes two electrodes and a light emitting layer interposed therebetween, and electrons injected from one electrode and holes injected from another electrode are combined in the light emitting layer to form an exciton. The excitons emit light while releasing energy.

The organic light emitting diode display is not only advantageous in terms of power consumption, but also excellent in response speed, viewing angle, and contrast ratio because it does not need a separate light source.

However, the light emitting efficiency of the organic light emitting diode display varies depending on the red, green, and blue light emitting materials. Therefore, in order to control red, green and blue light emission equally, the pixel should be designed based on the region having the lowest luminous efficiency, and in this case, the aperture ratio is greatly reduced.

The technical problem to be solved by the present invention is to solve such a problem, and to increase the aperture ratio while securing current driving characteristics of the organic light emitting diode display.

A display device according to an exemplary embodiment of the present invention includes a first pixel, a second pixel, and a third pixel, each of which is defined by a plurality of gate lines and a plurality of data lines, wherein the first to third pixels each include: A light emitting device, first and second driving transistors connected to the light emitting device, and first and second switching transistors which transmit data signals to the first and second driving transistors, wherein the first pixel is configured to emit the light. The device further includes a third driving transistor connected to the device.

The third driving transistor may be located in a region of a second pixel adjacent to the first pixel.

The display device may further include a plurality of driving voltage lines formed in parallel with the data lines.

The first to third driving transistors and the first and second switching transistors may each include a control terminal, an input terminal, and an output terminal.

The input terminal of the first driving transistor may be connected to the output terminal of the second switching transistor, and the input terminals of the second and third driving transistors may be connected to the driving voltage line.

Control terminals of the first to third driving transistors may be connected to each other.

Control terminals of the first to third driving transistors may be connected to output terminals of the first switching transistor.

Output terminals of the first and second driving transistors may be connected to each other.

Output terminals of the first to third driving transistors may be connected to the pixel electrode.

Control terminals of the first and second switching transistors may be connected to each other.

The first and second pixels may share one driving voltage line among the plurality of driving voltage lines.

The second and third driving transistors of the first pixel and the second driving transistor of the second pixel may be connected to one driving voltage line.

Two data lines may be positioned between the second pixel and the third pixel.

The second and third pixels may be mirror-symmetrically mirrored with respect to the two data lines.

The display device may further include a first storage capacitor formed between the control terminal of the second driving transistor and the driving voltage line, and a second storage capacitor formed between the control terminal of the third driving transistor and the driving voltage line.

The first to third pixels may operate in a first mode or a second mode.

In the first mode, a data voltage may be applied from the data line to the first to third pixels.

In the second mode, a data current may be applied from the data line to the first to third pixels.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, an organic light emitting diode display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a block diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of an organic light emitting diode display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, an organic light emitting diode display according to an exemplary embodiment includes a display panel 300, a scan driver 400 and a data driver 500 connected thereto, and a signal controller for controlling the display panel 300. And 600.

The display panel 300 is connected to a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of driving voltage lines (not shown) and arranged in an approximately matrix form in an equivalent circuit. A plurality of pixels PX is included.

The display signal lines G ₁ -G _n and D ₁ -D _m may include a plurality of scan signal lines G ₁ -G _n transmitting the scan signals and a plurality of data lines D ₁ -D _m transferring the data voltages. Include. The scan signal lines G ₁ -G _n extend substantially in the row direction and are separated from each other and are substantially parallel. The data lines D ₁ -D _m extend approximately in the column direction and are separated from each other and are substantially parallel.

The driving voltage line transfers the driving voltage Vdd to each pixel PX.

As shown in FIG. 2, the display device includes a plurality of signal lines 121, 171, and 172, a plurality of first pixels PX1, a second pixel PX2, which are connected to them and arranged in a substantially matrix form. The third pixel PX3 is included.

The signal line includes a plurality of scan signal lines 121, a plurality of data lines 171, and a plurality of driving voltage lines 172.

The first to third pixels PX1, PX2, and PX3 include the first and second driving transistors Qd1 and Qd2, the first and second switching transistors Qs1 and Qs2, the first storage capacitor Cs1, and the organic light emitting diode. An element LD is included. The first pixel PX1 further includes a third driving transistor Qd3 and a second storage capacitor Cs2.

Each first driving transistor Qd1 is a three-terminal element having a control terminal, an input terminal, and an output terminal. The control terminal is connected to the first switching transistor Qs1, and the input terminal is the second switching transistor Qs2. ) And the output terminal is connected to the organic light emitting element (LD).

Each second driving transistor Qd2 also has a control terminal, an input terminal, and an output terminal as a three-terminal element, the control terminal being connected to the first switching transistor Qs1, and the input terminal being connected to the driving voltage line 172. The output terminal is connected to the organic light emitting element LD. The second driving transistor Qd2 flows an output current whose magnitude varies depending on the voltage applied between the control terminal and the output terminal.

The third driving transistor Qd3 also has a control terminal, an input terminal and an output terminal as a three-terminal element, the control terminal being connected to the first switching transistor Qs1, and the input terminal being connected to the driving voltage line 172. The output terminal is connected to the organic light emitting element LD. The third driving transistor Qd3 is formed in the second pixel PX2 region. The third driving transistor Qd3 flows an output current whose magnitude varies depending on the voltage applied between the control terminal and the output terminal.

The first and second switching transistors Qs1 and Qs2 also have a control terminal, an input terminal and an output terminal as three-terminal elements, the control terminal being connected to the gate line 121, and the input terminal being the data line 171. The output terminal is connected to the control terminal of the first to third driving transistors Qd1, Qd2, and Qd3 and the input terminal of the first driving transistor Qd1, respectively. The switching transistors Qs1 and Qs2 transfer a data signal applied to the data line 171 to the driving transistors Qd1, Qd2 and Qd3 in response to a scan signal applied to the gate line 121.

The first / second storage capacitor Cs1 / Cs2 is connected between the control terminal of the first and second / third driving transistors Qd1 and Qd2 / Qd3 and the driving voltage line 172. The first / second sustain capacitor Cs1 / Cs2 charges a data signal applied to the control terminals of the first and second / third drive transistors Qd1, Qd2 / Qs3, and the first switching transistor Qs1 is turned on. Keep it even after it is off.

The organic light emitting element LD has an anode connected to the output terminal of the driving transistors Qd1, Qd2, and Qd3 and a cathode connected to the common voltage Vss. The organic light emitting element LD displays an image by emitting light at different intensities according to output currents from the driving transistors Qd1, Qd2, and Qd3.

The second and third driving transistors Qd2 and Qd3 of the first pixel and the second driving transistor Qd2 of the second pixel share one driving voltage line 172.

Two data lines 171 connected to the second and third pixels PX2 and PX3 are respectively disposed between the second and third pixels PX2 and PX3, and the second and third pixels PX2 and PX3. The first and second driving transistors Qd1 and Qd2, the first and second switching transistors Qs1 and Qs2, and the first sustain charger Cs1 may be symmetric about two data lines 171.

The switching and driving transistors Qs1-2 and Qd1-3 are composed of n-channel field effect transistors (FETs) including amorphous silicon or polycrystalline silicon. However, these transistors Qs1-2 and Qd1-3 may also consist of p-channel field effect transistors (FETs), in which case the p-channel field effect transistors (FETs) and n-channel field effect transistors (FETs) Complementary, the operation and voltage and current of the p-channel field effect transistor (FET) are opposite to that of the n-channel field effect transistor (FET).

Next, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 6.

3 is a layout view of a display device according to an exemplary embodiment. FIGS. 4 and 5 are cross-sectional views of the display device shown in FIG. 3 taken along lines IV-IV and V-V, respectively. Is a schematic diagram of an organic light emitting member of a display device according to an exemplary embodiment of the present invention.

2 and 3, the display device according to the present exemplary embodiment includes first to third pixels PX1-3, and each arrangement structure is different.

First, the first pixel PX1 will be described in detail.

A gate conductor including a gate line 121 including a protrusion 124 and a first electrode member 126 is formed on an insulating substrate 110 made of transparent glass or plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a wide end portion 129 for connection with another layer or an external driving circuit. The protrusion 124 extends upward from the gate line 121 and includes first and second control electrodes 124a and 124b. When a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The first electrode member 126 is separated from the gate line 121 and includes third to fifth control electrodes 124c, 124d, and 124e.

The gate conductors 121 and 124b are made of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, and molybdenum (Mo) It may be made of molybdenum-based metals such as molybdenum alloys, chromium (Cr), tantalum (Ta), and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. On the other hand, other conductive films are made of other materials, particularly materials having excellent physical, chemical and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum, and the like. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate conductors 121 and 124b may be made of various metals or conductors.

Side surfaces of the gate conductors 121 and 124b are inclined with respect to the substrate 110 surface, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiN _x ) or silicon oxide (SiO _x ) is formed on the gate conductors 121 and 124b.

On the gate insulating layer 140, first to fifth island-type semiconductors 154a, 154b, 154c, 154d, made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si), polycrystalline silicon, or the like. 154e) is formed. The third and fourth island semiconductors 154c and 154d are connected to each other to form one island semiconductor 155. The first and second island semiconductors 154a and 154b are positioned on the first and second control electrodes 124a and 124b, respectively, and the third to fifth island semiconductors 154c-e are respectively controlled to the third to fifth control. It is located above the electrodes 124c-e.

A plurality of pairs of first ohmic contacts 163a and 165a, a plurality of pairs of second ohmic contacts (not shown), and a plurality of pairs of third ohmic contacts (not shown) on the island semiconductors 154a-e, respectively. 163c and 165c, a plurality of pairs of fourth ohmic contacts (not shown) and a plurality of pairs of third ohmic contacts 163e and 165e are formed. The ohmic contacts 163a, 163c, 163e, 165a, 165c, and 165e have an island shape and are made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus (P) are heavily doped, or silicide. Can be made with The first to fifth ohmic contacts 163a, 163c, 163e, 165a, 165c, and 165e are paired and disposed on the first to fifth island semiconductors 154a, 154b, 154c, 154d, and 154e, respectively.

The data line 171, the driving voltage line 172, the first output electrode 175a, and the second electrode are disposed on the ohmic contacts 163a, 163c, 163e, 165a, 165c, and 165e and the gate insulating layer 140. A plurality of data conductors including the member 176 and the third electrode member 178 is formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 has a large area for connecting a plurality of first and second input electrodes 173a and 173b extending toward the first control electrode 124a with another layer or an external driving circuit. End portion 179. The first input electrode 173a partially overlaps the first island semiconductor 154a, and the second input electrode 173b partially overlaps the second island semiconductor 154b. When a data driving circuit (not shown) generating a data signal is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The first output electrode 175a is separated from the data line 171 and faces the first input electrode 173a with respect to the first island-type semiconductor 154a.

The second electrode member 176 is separated from the data line 171. One end of the second electrode member 176 includes a second output electrode 175b facing the second input electrode 173b about the second island semiconductor 154b and the other end of the third island semiconductor 154c. ) And a third input electrode 173c partially overlapped.

The third electrode member 178 is separated from the data line 171, and one end includes a third output electrode 175c facing the third input electrode 173c around the third island-type semiconductor 154c. And the other end includes a fourth output electrode 175d partially overlapping with the fourth island-type semiconductor 154d.

The driving voltage line 172 mainly extends in the vertical direction and intersects the gate line 121, and faces the fourth output electrode 175d and the fifth input electrode 173d and the fifth centering around the fourth island-type semiconductor 154d. The fifth input electrode 173e partially overlaps the island-like semiconductor 154e.

The data conductor includes a fifth output electrode 175e facing the fifth input electrode 173e around the fifth island-type semiconductor 154e.

The data conductors 171, 172, 173a-e, and 175a-e are preferably made of a refractory metal such as molybdenum, chromium, tantalum and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive material. It may have a multi-layer structure consisting of a film (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, a triple layer of molybdenum (alloy) lower layer and an aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data conductors 171, 172, 173a-e, and 175a-e may be made of various other metals or conductors.

Like the gate conductors 121 and 124b, the data conductors 171, 172, 173a-e, and 175a-e also preferably have their side surfaces inclined at an inclination angle of about 30 ° to 80 ° with respect to the substrate 110 surface. Do.

The ohmic contacts 163a, 163c, 163e, 165a, 165c, and 165e exist only between the semiconductors 154a-e below and the data conductors 171, 172, 173a-e, and 175a-e above. Lower the contact resistance. The semiconductors 154a-e have portions exposed between the data electrodes 171, 172, 173a-e, and 175a-e as well as between the input electrodes 173a-e and the output electrodes 175a-e.

A passivation layer 180 is formed on the data conductors 171, 172, 173a-e, and 175a-e and the exposed semiconductors 154a-e. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. Examples of the inorganic insulator include silicon nitride and silicon oxide. The organic insulator may have photosensitivity and preferably has a dielectric constant of 4.0 or less. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portions of the semiconductors 154a-e while maintaining excellent insulating properties of the organic layer.

The passivation layer 180 has a plurality of contact holes 182 exposing the end portion 179 of the data line 171 and the first, third, fourth, and fifth output electrodes 175a, 175c, and 175e, respectively. , 185a, 185b, and 185c, and a plurality of contact holes exposing the end portion 129 of the gate line 121 and the third input electrode 124c in the passivation layer 180 and the gate insulating layer 140, respectively. 181 and 184 are formed.

A plurality of pixel electrodes 191, a plurality of connecting members 85, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. These may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the third and fourth output electrodes 175c and 175d through the contact hole 185b and is physically connected to the fifth output electrode 175e through the contact hole 185c. It is electrically connected.

The connecting member 85 is connected to the third control electrode 124c and the first output electrode 175a through the contact holes 184 and 185a.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portions 129 and 179 of the gate line 121 and the data line 171 and the external device.

A partition 361 is formed on the passivation layer 180. The partition 361 surrounds the edge of the pixel electrode 191 like a bank to define an opening 365 and is made of an organic insulator or an inorganic insulator. The partition 361 may also be made of a photosensitive material containing black pigment, in which case the partition 361 serves as a light blocking member and the forming process is simple.

An organic light emitting member 370 is formed in the opening 365 on the pixel electrode 191 defined by the partition 361. The organic light emitting member 370 is made of an organic material that uniquely emits light of any one of primary colors such as three primary colors of red, green, and blue. The organic light emitting diode display displays a desired image by using a spatial sum of the primary color light emitted by the organic light emitting members 370. Pixels emitting red, green, and blue light in the future are referred to as red, green, and blue pixels, respectively, and are denoted by reference numerals R, G, and B, respectively. That is, for example, the first pixel PX1 may be a blue pixel B, the second pixel PX2 may be a green pixel G, and the third pixel PX3 may be a red pixel R.

As illustrated in FIG. 6, the organic light emitting member 370 has a multilayer structure including auxiliary layers for improving light emission efficiency of the light emitting layer EML in addition to the light emitting layer EML. The secondary layer contains an electron transport layer (ETL) and hole transport layer (HTL) to balance electrons and holes, and an electron injecting layer to enhance injection of electrons and holes. (EIL) and hole injecting layer (HIL). Subsidiary layers may be omitted.

The common electrode 270 is formed on the organic light emitting member 370. The common electrode 270 receives a common voltage Vss and is made of a reflective metal including calcium (Ca), barium (Ba), magnesium (Mg), aluminum, silver, or the like, or a transparent conductive material such as ITO or IZO. .

The opaque pixel electrode 190 and the transparent common electrode 270 are applied to a top emission type organic light emitting display device displaying an image in an upper direction of the display panel 300, and the transparent pixel electrode 190 The opaque common electrode 270 may be applied to a bottom emission organic light emitting display device that displays an image in a downward direction of the display panel 300.

In the organic light emitting diode display, the first control electrode 124a connected to the gate line 121, the first input electrode 173a and the first output electrode 175a connected to the data line 171 are linear. The first switching thin film transistor Qs1 is formed together with the protrusion 154a of the semiconductor 151 and is connected to the second control electrode 124b and the data line 171 connected to the gate line 121. The second input electrode 173b and the second output electrode 175b together with the second island type semiconductor 154b form a second switching thin film transistor Qs2.

In this case, a channel of the first switching thin film transistor Qs1 is formed in the first island-shaped semiconductor 154a between the first input electrode 173a and the first output electrode 175a and the second switching thin film transistor. A channel of Qs2 is formed in the second island-like semiconductor 154b between the second input electrode 173b and the second output electrode 175b.

In addition, the third control electrode 124c, the third input electrode 173c, and the third output electrode 175c form the first driving thin film transistor Qd1 together with the third island-type semiconductor 154c, and the fourth control electrode ( 124d, the fourth input electrode 173d and the fourth output electrode 175d connected to the driving voltage line 172 together with the fourth island-type semiconductor 154d form a second driving thin film transistor Qd2. The fifth control electrode 124e, the fifth input electrode 173e, and the fifth output electrode 175e form the third driving thin film transistor Qd3 together with the fifth island-type semiconductor 154e.

In this case, a channel of the first driving thin film transistor Qd1 is formed in the third island-type semiconductor 154c between the third input electrode 173c and the third output electrode 175c, and the second driving thin film transistor Qd2. Is formed in the fourth island semiconductor 154d between the fourth input electrode 173d and the fourth output electrode 175d, and the channel of the third driving thin film transistor Qd3 is formed of the fifth input electrode 173e and The fifth island semiconductor 154e is formed between the fifth output electrode 175e.

An arrangement structure of the second and third pixels PX2 and PX3 will now be described in detail.

As shown in FIGS. 2 to 4, the gate lines 121 and the second and third pixels PX2 and PX3 also include protrusions 124 on the insulating substrate 110 made of transparent glass or plastic. A gate conductor including the first electrode member 126 is formed. The protrusion 124 extends upward from the gate line 121 and includes first and second control electrodes 124a and 124b. The first electrode member 126 is separated from the gate line 121 and includes third and fourth control electrodes 124c and 124d. A gate insulating layer 140 is formed on the gate conductors 121 and 124b. First to fourth island semiconductors 154a, 154b, 154c, and 154d are formed on the gate insulating layer 140. A plurality of pairs of first to fourth ohmic contacts 163a, 165a, 163c, and 165c are formed on the island-like semiconductors 154a-d, respectively. The data line 171, the driving voltage line 172, the first output electrode 175a, and the second electrode member 176 are disposed on the ohmic contacts 163a, 163c, 163e, and 165a and the gate insulating layer 140. And a plurality of data conductors including a third electrode member 178. Each data line 171 includes a plurality of first and second input electrodes 173a and 173b extending toward the first control electrode 124a. The second output electrode 175b and the third input electrode 173c of the second electrode member 176 are included. The third electrode member 178 includes a third output electrode 175c, a fourth output electrode 175d, and a fourth input electrode 173d. A passivation layer 180 is formed on the data conductors 171, 172, 173a-d, and 175a-d and the exposed semiconductors 154a-d. The passivation layer 180 may include a plurality of contact holes 182, 185a, which expose end portions 179 of the data line 171 and first, third, and fourth output electrodes 175a, 175c, and 175d, respectively. 185b is formed, and a plurality of contact holes 181 and 184 exposing the end portion 129 of the gate line 121 and the third input electrode 124c are formed in the passivation layer 180 and the gate insulating layer 140, respectively. Formed. A plurality of pixel electrodes 191, a plurality of connection members 85, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. A partition 361 is formed on the passivation layer 180. An organic light emitting member 370 is formed in the opening 365 on the pixel electrode 191 defined by the partition 361. The common electrode 270 is formed on the organic light emitting member 370.

That is, unlike the first pixel PX1, the second and third pixels PX2 and PX3 do not include the third driving transistor Qd3, and each of the second and third pixels PX2 and PX3 is disposed between the second and third pixels PX2 and PX3. Two data lines 171 connected to the pixels are formed. Accordingly, the second and third pixels PX2 and PX3 are mirror-symmetrically around two data lines 171.

Also, the second pixel PX2 is connected to the other edge of the driving voltage line 172 connected to the first pixel PX1 without having a separate driving voltage line. That is, the fourth output electrode 175d of the second pixel PX2 shares the same driving voltage line 172 as the fourth output electrode 175d of the first pixel PX1.

The third driving transistor Qd3 of the first pixel PX1 is positioned in the second pixel PX2 area beyond the driving voltage line 172.

The reason why the arrangement structure of the first to third pixels PX1, PX2, and PX3 is different is that the luminous efficiency varies depending on the color light of the organic light emitting member 370 of each pixel. That is, the luminous efficiency of the organic light emitting diode LD varies depending on the luminous material. For example, luminous efficiency is lowered in the order of green, red, and blue. Here, the blue light emitting material has the lowest light emitting efficiency, and is described on the premise that the light emitting efficiency is high in the order of red and green. If the luminous efficiency is low, so much current is required, so that the channel width must be made large in order to emit the same light. 2 and 3, when the blue pixels B, the red pixels R, and the green pixels G are arranged adjacent to each other, the third driving transistor Qd3 is disposed in the blue pixels B having low luminous efficiency. It is further formed to make the total panel width of the blue pixel B largest. 3, the channel width of the second driving transistor Qd2 of the red pixel R is greater than the channel width of the second driving transistor Qd2 of the green pixel G. Therefore, the channel width of the blue pixel B is the largest, and the channel width of the driving transistor is small in the order of the red pixel R and the green pixel G.

In this case, the third driving transistor Qd3 of the blue pixel B is disposed in the area of the green pixel G that requires a relatively small channel width, thereby reducing the blue light emitting element area of the blue pixel B without reducing the blue light. The channel width of the pixel B can be sufficiently extended. In addition, in each pixel B, G, and R, the channel of the driving transistor is formed to be parallel to the long side of the pixel electrode 191, and is not formed around the short side, so that each pixel electrode 191 and the light emitting member 370 A wider area can be secured and the aperture ratio can be improved.

Although the light emission efficiency was described above in the order of the green pixel G, the red pixel R, and the blue pixel B, the order may be changed according to the light emitting material, and the present invention may be equally applicable. have.

Referring back to FIG. 1, the scan driver 400 is connected to the scan signal lines G ₁ -G _n to form a high voltage Von for turning on the switching transistor Qs and a low voltage Voff for turning off the switching transistor Qs. A scan signal consisting of a combination of the signals is applied to the scan signal lines G ₁ -G _n .

The data driver 500 is connected to the data lines (D ₁ -D _m) and applies the data voltages to the data lines (D ₁ -D _m).

The signal controller 600 controls operations of the scan driver 400 and the data driver 500, and corrects the input image data R, G, and B.

The scan driver 400 or the data driver 500 may be mounted directly on the display panel 300 in the form of at least one driver integrated circuit chip, or mounted on a flexible printed circuit film (not shown). The display panel 300 may be attached to the display panel 300 in the form of a tape carrier package (TCP). Alternatively, the scan driver 400 or the data driver 500 may be integrated in the display panel 300. Alternatively, the data driver 500 and the signal controller 600 may be integrated in one IC (one chip).

The signal controller 600 is configured to control input image data R, G, and B and its display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( Hsync, main clock MCLK, and data enable signal DE are provided. The signal controller 600 generates the output image data DAT by correcting the input image data R, G, and B based on the input image data R, G, and B and the input control signal, and generates the scan control signal CONT1. ) And the data control signal CONT2 and the like, the scan control signal CONT1 is sent to the scan driver 400, and the data control signal CONT2 and the output image data DAT are sent to the data driver 500. .

The scan control signal CONT1 includes a scan start signal STV for instructing the scan start of the high voltage Von and at least one clock signal for controlling the output of the high voltage Von.

The data control signal CONT2 is a load signal LOAD and a data clock signal HCLK for applying a corresponding data voltage to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating data transfer of one pixel row. ), And the like.

The data driver 500 sequentially receives the image data DAT for one row of pixels according to the data control signal CONT2 from the signal controller 600, converts each image data DAT into a data voltage, and then converts the image data DAT into a data voltage. Is applied to the data lines D ₁ -D _m .

The scan driver 400 applies the scan signal to the scan signal lines G ₁ -G _n in accordance with the scan control signal CONT1 from the signal controller 600 to switch the scan driver 400 to the scan signal lines G ₁ -G _n . The transistor Qs is turned on, and thus, the data voltage applied to the data lines D ₁ -D _m is applied to the control terminal of the driving transistor Qd through the turned-on switching transistor Qs.

The data voltage applied to the driving transistor Qd is charged in the capacitor Cst and the charged voltage is maintained even when the switching transistor Qs is turned off. The driving transistor Qd to which the data voltage is applied is turned on and outputs a current I _LD depending on this voltage. As the current I _LD flows through the organic light emitting member LD, the pixel PX displays an image.

After one horizontal period (or "1H") (one period of the horizontal synchronization signal Hsync and the data enable signal DE) has passed, the data driver 500 and the scan driver 400 are connected to the pixels PX of the next row. Repeat the same operation. In this manner, the scan signals are sequentially applied to all the scan signal lines G ₁ -G _n during one frame to apply the data voltage to all the pixels PX. When one frame ends, the next frame starts and the same operation is repeated for the next frame.

The operation of such a display device will now be described in detail with reference to FIG. 2 again.

Each pixel PX1, PX2, PX3 of this embodiment operates by dividing into a normal mode and a correction mode. In the normal mode, the normal display operation is performed, but in the correction mode, the data voltage according to the variation of the threshold voltage of the driving transistors Qd1, Qd2, and Qd3 is corrected.

The data signals applied to the pixels PX1, PX2, and PX3 are data voltages in the normal mode or data currents in the calibration mode. To this end, the organic light emitting diode display according to the present exemplary embodiment may include a driving device (not shown) connected to the data line 171 and capable of generating a data voltage and a data current.

In the normal mode, the pixel PX2 of the present embodiment operates substantially the same as the pixel PX1 shown in FIG. 1. That is, when the first switching transistor Qs1 is turned on by the scan signal, the data voltage applied to the data line 171 is applied to the control terminal of the second driving transistor Qd2 through the first switching transistor Qs1. The second driving transistor Qd2 sends the output current I _LD based on the data voltage to the organic light emitting element LD, and the organic light emitting element LD emits light to display an image.

The second switching transistor Qs2 is also turned on by the scan signal, and the data voltage is applied to the control terminal and the input terminal of the first driving transistor Qd1 through the first and second switching transistors Qs1 and Qs2, respectively. do. Therefore, even when the first driving transistor Qd1 is turned on, the voltage of the input terminal and the control terminal is the same, so that the first driving transistor Qd1 does not flow current. As a result, the image according to the data voltage is displayed by the first switching transistor Qs1 and the second driving transistor Qd2 in the normal mode.

Meanwhile, in order for the organic light emitting element LD to emit a constant luminance, the second or third driving transistors Qd2 and Qd3 need to flow a constant output current. However, when the threshold voltage of the second or third driving transistors Qd2 and Qd3 is changed, even if a constant data voltage is applied to the control terminal of the second or third driving transistors Qd2 and Qd3, the second or third driving transistor Qd2 is applied. , Qd3) does not flow a constant output current. Therefore, it is necessary to correct the data voltage according to the variation of the threshold voltage of the second driving or the third transistors Qd2 and Qd3. In the correction mode of the present embodiment, the data voltage is corrected according to the threshold voltage variation.

In the correction mode, the driving device transmits a predetermined data current to the data line 171. When the switching transistors Qs1 and Qs2 are turned on by the scan signal, charges due to a predetermined data current start to be charged in the first or second sustain capacitors Cs1 and Cs2 through the first switching transistor Qs1. Accordingly, the first driving transistor Qd1 starts to flow a current depending on the voltage charged in the first or second storage capacitors Cs1 and Cs2, and the charging voltage of the first or second storage capacitors Cs1 and Cs2 is decreased. As the voltage increases, the current flowing through the first driving transistor Qd1 also increases. The first or second sustain capacitors Cs1 and Cs2 have a voltage until the first driving transistor Qd1 flows an output current substantially equal to a predetermined data current flowing into the input terminal through the second switching transistor Qs2. To charge. At this time, the charging voltage (hereinafter referred to as “correction voltage”) has a one-to-one correspondence with a predetermined data current, and the correction voltage reflects the threshold voltage variation of the first driving transistor Qd1.

Since the control terminals of the driving transistors Qd1, Qd2, and Qd3 are connected to each other, the control terminal voltage is the same. Since the output terminals are also connected to each other, the output terminal voltage is the same. Since the variation of the threshold voltage depends on the voltage difference between the control terminal and the output terminal of the driving transistors Qd1, Qd2, and Qd3 regardless of the channel width and channel length ratio, the variation of the threshold voltage of the driving transistors Qd1, Qd2, and Qd3 Same as each other. Therefore, the correction voltage for the first driving transistor Qd1 may be applied to the second or third driving transistors Qd2 and Qd3.

Therefore, in the correction mode, the correction voltage for the predetermined data current is read and stored in a lookup table (not shown). Then, the data voltage is corrected with reference to the correction voltage in the normal mode, and the corrected data voltage is applied to the second or third driving transistors Qd2 and Qd3. Then, even if the threshold voltages of the second or third driving transistors Qd2 and Qd3 are changed, the second or third driving transistors Qd2 and Qd3 can flow a constant output current, so that the organic light emitting element LD has a constant luminance. I can make it.

Since the threshold voltage fluctuates over a long period of time, it operates in the correction mode at an appropriately long time interval for each pixel PX2. Therefore, even when the image is displayed in the normal mode and operated in the correction mode, the image is not substantially displayed.

Here, the first pixel PX1 may further include one driving transistor Qd3 operating in the correction mode to maintain the same luminance as the second and third pixels PX2-3 even though the luminous efficiency is low.

As described above, according to the present invention, the aperture ratio may be increased while securing the current driving characteristics of the organic light emitting diode display.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (18)

A first pixel, a second pixel, and a third pixel defined by a plurality of gate lines and a plurality of data lines, respectively, The first to third pixels, respectively A light emitting device, first and second driving transistors connected to the light emitting device, first and second switching transistors transferring data signals to the first and second driving transistors, The first pixel further includes a third driving transistor connected to the light emitting device. Display device. In claim 1, The third driving transistor is in a region of a second pixel adjacent to the first pixel. In claim 1, And a plurality of driving voltage lines formed in parallel with the data lines. In claim 3, The first to third driving transistors and the first and second switching transistors each include a control terminal, an input terminal, and an output terminal. In claim 4, And an input terminal of the first driving transistor is connected to an output terminal of the second switching transistor, and an input terminal of the second and third driving transistors is connected to the driving voltage line. In claim 4, A display device of which the control terminals of the first to third driving transistors are connected to each other. In claim 4, The control terminal of the first to third driving transistors is connected to the output terminal of the first switching transistor. In claim 4, A display device of which the output terminals of the first and second driving transistors are connected to each other. In claim 8, A display device of which the output terminals of the first to third driving transistors are connected to the pixel electrode. In claim 1, A display device of which the control terminals of the first and second switching transistors are connected to each other. In claim 3, And the first and second pixels share one driving voltage line among the plurality of driving voltage lines. In claim 11, The second and third driving transistors of the first pixel and the second driving transistor of the second pixel are connected to one driving voltage line. In claim 1, And two data lines positioned between the second pixel and the third pixel. In claim 13, And the second and third pixels are mirror-symmetrically mirrored with respect to the two data lines. In claim 1, And a first storage capacitor formed between the control terminal of the second driving transistor and the driving voltage line, and a second storage capacitor formed between the control terminal of the third driving transistor and the driving voltage line. In claim 1, The first to third pixels operate in the first mode or the second mode. The method of claim 16, In the first mode, a data voltage is applied from the data line to the first to third pixels. The method of claim 16, In the second mode, a data current is applied from the data line to the first to third pixels.

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