KR20070044698A - Bit line sensing amplifier - Google Patents

Abstract

The present invention relates to a bit line sense amplifier, and more particularly, to a bit line sense amplifier capable of efficiently screening cell defects when driven in a USD test mode. This circuit, when driven in USD test mode, leaks between the bitline (BL) and the bitline bar (/ BL) through a leak-proof NMOS transistor with a gate terminal connected between the pair of bitlines and connected to the dummy wordline. By reducing the amount of current, there is an effect that the defects in the cells can be screened efficiently.

Description

BIT LINE SENSING AMPLIFIER}

1 is a partial circuit diagram of a bit line sense amplifier according to the prior art.

2 is a partial circuit diagram of a bit line sense amplifier according to an exemplary embodiment of the present invention.

3 is a partial layout view of a bit line sense amplifier according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

210: sense amplifier 220: precharge unit

230A, 230B: Lighter 240A, 240B: Connection

250: output unit 260: NMOS transistor for leakage prevention

The present invention relates to a bit line sense amplifier, and more particularly, to a bit line sense amplifier capable of efficiently screening cell defects when driven in a USD test mode.

In general, when a semiconductor device is manufactured and shipped, a test is performed to reveal potential defects of the semiconductor device or to remove defective memory cells in order to ensure reliability thereof. As such a test method, the semiconductor device operates at a voltage higher than the actual use voltage, thereby causing stress in a short time beyond the initial failure period in the actual use condition. After that, the memory cells that may cause initial operation failure among the tested semiconductor devices are selected before shipment. By such an electrical test, the semiconductor device, which may cause initial defective operation, is efficiently removed, thereby increasing the reliability of the product.

The burn-in test is divided into a wafer burn-in test and a package burn-in test according to the test method.

The wafer burn-in test is to remove defective parts by applying a high voltage to a chip in a wafer state, and the package burn-in test is to remove defective parts by applying a high voltage to a chip in a packaged state. The part removed by this test is replaced by using a redundancy device that is inherent in the current memory device. Currently, most semiconductor memories are undergoing burn-in tests for several hours or more in the package state as described above. Such a test guarantees a user the lifespan of a completed memory device, and is essential to show the reliability of the semiconductor memory device.

1 is a partial circuit diagram of a bit line sense amplifier according to the prior art.

As shown, the bit line sense amplifier according to the related art is enabled by the sense amplifier enable signals RTO and SB and a sense amplifier for amplifying a signal difference applied to the bit line pair BL // BL. 110); A precharge unit 120 for precharging the bit line pairs BL and / BL with the bit line precharge voltage VBLP when the sense amplifier 110 is disabled; Equalizers 130A and 130B enabled by the equalization signal BLEQ to equalize the voltage levels of the pair of bit lines BL and / BL; Connection units 140A and 140B for selectively connecting the sense amplifier 110 to a neighboring cell block (not shown) in response to a bit line separation signal BISH; And a data output unit 150 for amplifying the data signal selected by the column address signal CY through the sense amplifier 110 and then outputting the amplified data signal to a pair of segment input / output lines SIO and SIOB. It includes;

Here, the equalizer 130A is located between the connection block 140A and the cell block connected to one side of the bit line sense amplifier, and the equalizer 130B is between the connection block 140B and the cell block connected to the other side of the bit line sense amplifier. Located in

The bit line sense amplifier configured as described above operates as follows when driven in the USD (Unlimited Sensing Delay) test mode.

In the bit line sense amplifier according to the related art, after a word line is enabled at a high level, a minute voltage difference is loaded on a pair of bit lines BL and BL by charge sharing.

At the same time, the bit line sense amplifier according to the related art enables the bit line separation signals BISH and BISL to cut off the connection between the neighboring cell block and the sense amplifier 110.

Then, the bit line sense amplifier according to the prior art tests that the charge stored in the memory cell is transferred to the bit line to generate charge sharing, and that the minute voltage difference between the bit lines generated by the charge sharing is kept constant.

In other words, the bit line sense amplifier according to the related art delays the sensing operation of the sense amplifier 110 for a long time, and a micro bridge between the word line and the bit line due to a defect of the memory cell during this delay time. To see if it happens.

However, the bit line sense amplifier according to the related art has a leakage current in the NMOS transistors 141A, 142A, 141B, and 142B of the equalizers 130A and 130B due to the sensing delay of the sense amplifier 110 during the USD test operation. current) may occur. Here, the leakage current means a phenomenon in which current flows even when the MOS transistor is turned off due to the parasitic bipolar transistor generated in the MOSFET structure.

That is, the bit line sense amplifier according to the related art disables all of the connection parts 140A and 140B by the bit line separation signals BISH and BISL for the USD test operation. At this time, the voltage difference is generated in the bit line pair BL, / BL by charge sharing, and is maintained for a long time, and the equalizer 130A, Leakage current may occur in the NMOS transistors 131A and 131B of 130B.

Accordingly, the bit line sense amplifier according to the related art causes charge transfer between the bit line BL and the bit line bar / BL due to the leakage current. As a result, the bit line sense amplifier according to the related art reduces the voltage difference between the bit line BL and the bit line bar / BL, and accordingly, the sensing margin is reduced to reduce the bit line pair BL. A column fail is caused in the memory cell connected to / BL).

Accordingly, the bit line sense amplifier according to the related art cannot efficiently screen a defect of a memory cell, thereby causing a package yield loss.

Accordingly, the present invention was created to solve the problems inherent in the prior art as described above, and an object of the present invention is to provide a bit line sense amplifier capable of efficiently screening a defect of a memory cell during a USD test operation. Is in.

In accordance with an aspect of the present invention for achieving the object as described above, a bitline sense amplifier is provided: the circuit is enabled by a sense amplifier enable signal and amplifies a signal difference applied to the bitline pair. Sense amplifiers; A precharge unit configured to precharge the pair of bit lines with a bit line precharge voltage when the sense amplifier is disabled; An equalizer which is enabled by an equalization signal when the sense amplifier is disabled to equalize the voltage level of the bit line pair; A connection unit for selectively connecting the sense amplifier with a neighboring cell block in response to the bit line separation signal; And a leakage preventing NMOS transistor connected between the bit line pairs and having a gate terminal connected to the dummy word line.

In the above configuration, the leakage preventing NMOS transistor is located between the equalizing unit and the cell block.

In the above configuration, a ground voltage is input to the dummy word line.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a partial circuit diagram of a bit line sense amplifier according to an exemplary embodiment of the present invention.

As shown, the bit line sense amplifier according to the embodiment of the present invention is enabled by the sense amplifier enable signals RTO and SB, and applied to the bit line pair BL and / BL. A sense amplifier 210 for amplifying a signal difference; A precharge unit 220 for precharging the bit line pairs BL and / BL with the bit line precharge voltage VBLP when the sense amplifier 210 is disabled; Equalizers 230A and 230B enabled by the equalization signal BLEQ to equalize the voltage levels of the pair of bit lines BL and / BL; Connection units 240A and 240B for selectively connecting the sense amplifier 210 to a neighboring cell block (not shown) in response to a bit line separation signal BISH; A data output unit 250 for amplifying the data signal selected by the column address signal CY through the sense amplifier 210 and then outputting the amplified data signal to a pair of segment input / output lines SIO and SIOB; And a leakage preventing NMOS transistor 260 connected between the bit line pairs BL and / BL and having a gate terminal connected to the dummy word line D_WL.

Here, the equalizing unit 230A is located between the connecting unit 240A and the leakage preventing NMOS transistor 260, and the equalizing unit 230B is a cell block connected to the connecting unit 240B and one side of the bit line sense amplifier according to the present invention. Located in between.

The NMOS transistor 231A of the equalizer 230A is connected between the bit line BL and the bit line bar / BL and receives the equalization signal BLEQ through the gate terminal.

In addition, the leakage preventing NMOS transistor 260 is located between the equalizer 230A and a cell block connected to the other side of the bit line sense amplifier according to the present invention, and the gate terminal of the leakage preventing NMOS transistor 260 is a dummy word line ( D_WL). In this case, as shown in FIG. 3, the leakage preventing NMOS transistor 260 may be implemented using a dummy cell (not shown). That is, the bit line sense amplifier according to the embodiment of the present invention may manufacture a dummy cell as an NMOS transistor and use it as the leakage preventing NMOS transistor 260.

In the bit line sense amplifier according to the embodiment of the present invention having the above configuration, the amount of leakage current flowing between the bit line pairs BL and / BL by the leakage preventing NMOS transistor 260 when driving in the USD test mode is increased. This is reduced, referring to Figure 2 in detail as follows.

In the bit line sense amplifier according to an embodiment of the present invention, when the word line is enabled in the USD test mode, a minute voltage difference is loaded on the pair of bit lines BL and BL by charge sharing. In this case, the bit line sense amplifier according to the embodiment of the present invention disables the precharge unit 220, the equalizers 230A and 230B, and the leakage preventing NMOS transistor 260.

Here, the gate terminal of the leakage preventing NMOS transistor 260 is connected to the dummy word line D_WL, and a ground voltage is input to the dummy word line D_WL. Accordingly, the bit line sense amplifier according to the embodiment of the present invention disables the leakage preventing NMOS transistor 260 by the dummy word line D_WL to which the ground voltage is input when the bit line sense amplifier is driven in the USD test mode.

At the same time, the bit line sense amplifier according to an embodiment of the present invention applies the bit line separation signals BISH and BISL at a low level for the USD test operation to block the connection between the neighboring cell block and the sense amplifier 210. Let's do it. This is to prevent the influence of the sense amplifier 210 during the USD test operation. In other words, the bit line sense amplifier according to an embodiment of the present invention disables all of the connection units 240A and 240B and then tests the defect of the memory cell.

At this time, even if the bit line sense amplifier according to the embodiment of the present invention maintains the charge sharing state for a long time, the leakage current flowing between the bit lines BL and / BL through the leakage preventing NMOS transistor 260 is larger than that of the conventional art. Decreases.

In detail, the bit line sense amplifier according to the embodiment of the present invention generates a leakage current in the NMOS transistor 231A of the equalizer 230A due to the sensing delay of the sense amplifier 210 during the USD test operation. At this time, since the leakage preventing NMOS transistor 260 is connected in parallel with the NMOS transistor 231A of the equalizer 230A, the bit line bar (/ BL) or the bit line bar (/ BL) in the bit line BL. To reduce the amount of leakage current flowing into the bit line BL.

In other words, when a leakage current occurs in the NMOS transistor 231A of the equalizer 230A, the leakage current passes through the NMOS transistor 231A of the equalizer 230A and the NMOS transistor 260 for preventing leakage. Since it flows from the BL to the bit line bar / BL, or from the bit line bar / BL to the bit line BL, the amount is reduced in half.

As described above, when the bit line sense amplifier according to the embodiment of the present invention is driven in the USD test mode, a bit line pair is generated by the equalizer 230A and the leakage current also flows to the leakage preventing NMOS transistor 260. The leakage current flowing between (BL, / BL) is reduced.

Accordingly, the bit line sense amplifier according to the embodiment of the present invention reduces the amount of charge transfer that occurs between the bit line BL and the bit line bar / BL due to the leakage current. As a result, the bit line sense amplifier according to the embodiment of the present invention has an effect of reducing the sensing margin to prevent column fail in memory cells connected to the bit line pairs BL and / BL.

Therefore, the bit line sense amplifier according to the embodiment of the present invention can efficiently screen defects of the memory cell, and thus, there is an advantage in terms of package yield.

According to the above-described configuration of the present invention, when the bit line sense amplifier is driven in the USD test mode, the amount of leakage current flowing between the bit line BL and the bit line bar / BL through the leakage preventing NMOS transistor is measured. By reducing, there is an effect that the defects of the cells can be screened efficiently.

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (3)

A sense amplifier enabled by the sense amplifier enable signal and amplifying a signal difference applied to the bit line pair; A precharge unit configured to precharge the pair of bit lines with a bit line precharge voltage when the sense amplifier is disabled; An equalizer which is enabled by an equalization signal when the sense amplifier is disabled to equalize the voltage level of the bit line pair; A connection unit for selectively connecting the sense amplifier with a neighboring cell block in response to the bit line separation signal; And And a leakage preventing NMOS transistor connected between the pair of bit lines and having a gate terminal connected to the dummy word line. The method of claim 1, And the leakage preventing NMOS transistor is positioned between the equalizer and the cell block. The method of claim 1, And a ground voltage is input to the dummy word line.

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