KR20070040035A - Display substrate and method for manufacturing the same - Google Patents

Abstract

Disclosed are a display substrate and a method of manufacturing the same for improving an afterimage. The display substrate includes a semiconductor layer made of amorphous silicon (a-Si: H (F)) doped with fluorine (F), and includes a source wiring and a drain electrode having a Mo / Al / Mo three-layer structure. The application of the a-Si: H (F) semiconductor layer to the four-process display substrate on which Mo / Al / Mo is applied as the metal wiring reduces the occurrence of light leakage current. Accordingly, an afterimage may be improved and a display substrate having an improved display quality of an image may be provided.

Light leakage current, silicon fluoride, SiF4 gas, aluminum wiring, semiconductor layer

Description

DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME}

1 is a plan view of a display substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3A to 3H are process diagrams illustrating a method of manufacturing the display substrate illustrated in FIG. 2.

4A to 4B are conceptual views illustrating expected molecular structures of the semiconductor layer.

5 is data obtained by analyzing a semiconductor layer by secondary ion mass spectrometry.

6 is data obtained by analyzing an a-Si: H (F) semiconductor layer by Fourier transform infrared spectroscopy.

7A to 7B are graphs showing characteristic curves of the switching element TFT.

8A to 8B are graphs showing characteristic curves of switching elements before and after applying driving stress in a state where light is provided.

<Description of the symbols for the main parts of the drawings>

120 gate electrode 130 gate insulating film

140: channel layer 142: semiconductor layer

144: ohmic contact layer L: protrusion

154 source electrode 156 drain electrode

The present invention relates to a display substrate and a method for manufacturing the same, and more particularly, to a display substrate for improving the afterimage and a method for manufacturing the same.

A liquid crystal display (LCD) includes a liquid crystal layer injected between a thin film transistor substrate and a counter substrate. The liquid crystal layer is an anisotropic dielectric constant, and the image is displayed by adjusting the amount of light transmitted by changing the arrangement according to the intensity of the electric field.

A plurality of gate lines parallel to each other and a plurality of data lines insulated from and intersecting with the gate lines are formed on the display substrate, and a pixel is formed in each area surrounded by the gate lines and the data lines. Each pixel is provided with a pixel electrode and a switching element for applying a pixel voltage to the pixel electrode.

The switching element is insulated from the gate electrode, the gate electrode extending from the gate lines, the channel layer overlapped with the gate electrode, the source electrode formed from the data line and electrically connected to the channel layer and spaced apart from the source electrode and electrically connected to the channel layer. And a drain electrode.

As the liquid crystal display (LCD) becomes larger and higher in quality, the need for low-resistance wiring of a display substrate is increasing. Therefore, aluminum (Al) to an aluminum alloy having a low specific resistance value is to be used as the metal wiring of the display substrate. The demand is growing. However, in the case of aluminum (Al), there is a problem in that direct contact with the pixel electrode is difficult and diffuses into the silicon (Si) film. Therefore, when aluminum wiring is used for the source wiring and the drain electrode, a Mo / Al / Mo three-layer film structure in which a molybdenum (Mo) film is laminated on the upper and lower sides is used.

Meanwhile, in the manufacturing process of the display substrate, the metal wiring is subjected to a photolithography process using a mask and isotropically etched by an etchant. However, in the four processes for reducing the number of manufacturing processes, the channel layer is etched using the source wiring and the drain electrode as a mask, and the channel layer is anisotropically etched by a reactive ion etching process.

Since the anisotropic etching is an etching that proceeds only in the vertical direction of the substrate surface, the lower part of the mask is not etched, but is etched with a wider width than the mask. In addition, not only the channel layer 140 to be etched, but also a small amount of both cross-sectional views of the left and right cross-sectional views of the source wiring and the drain electrode used as the mask.

As a result, the line width of the channel layer is wider than that of the source wiring and the drain electrode. When light is irradiated to a channel layer of a portion protruding from the line widths of the source wiring and the drain electrode, electron hole pairs (e-h pairs) are formed while the bond of amorphous silicon molecules in the channel layer is broken by the light energy.

The holes of the electron-electron pair thus formed move toward the gate electrode by the gate voltage Vg, and the electrons move toward the drain electrode so that photo leakage current flows. Therefore, there is a problem that an afterimage occurs on the display screen due to the current flowing even when the switching element is turned off. In particular, in the four-step display substrate in which the Mo / Al / Mo three-layer film structure is applied as the metal wiring, the afterimage problem due to the light leakage current is even more serious.

Therefore, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display substrate for improving the afterimage of the display screen.

Another object of the present invention is to provide a method of manufacturing the display substrate.

The display substrate according to the embodiment for realizing the object of the present invention includes an insulating substrate, a first metal pattern, a gate insulating film, a semiconductor layer, a second metal pattern, a passivation film and a pixel electrode.

The first metal pattern is formed on the insulating substrate, and includes a gate wiring and a gate electrode of a switching device. The gate insulating layer is formed on the first metal pattern. The semiconductor layer is formed on the gate insulating layer and is formed of an amorphous silicon layer containing fluorine (F). The second metal pattern is formed on the semiconductor layer, and includes a source wiring and a drain electrode of a switching element. The passivation layer is formed on the second metal pattern and includes a contact hole exposing a portion of the drain electrode. The pixel electrode is formed on the passivation layer and electrically connected to the drain electrode through the contact hole to apply a pixel voltage.

According to an aspect of the present invention, a method of manufacturing a display substrate includes forming a first metal layer on an insulating substrate, etching the first metal layer, and a switching element connected to the gate wiring and the gate wiring. Forming a first metal pattern including a gate electrode, depositing a gate insulating film on an insulating substrate on which the first metal pattern is formed, and forming a silylene gas (SiH4) and a silicon fluoride gas (SiF4) on the gate insulating film. Forming a semiconductor layer by using a source gas including a source gas, doping n + ions on the semiconductor layer, forming a second metal layer on the ohmic contact layer, and forming a second metal layer on the ohmic contact layer. Etching the metal layer to form a second metal pattern including a source wiring and a source electrode and a drain electrode of the switching element, and the second metal Etching a portion of the ohmic contact layer and the semiconductor layer using a pattern as a mask, forming a passivation film having a contact hole formed on the second metal pattern, and a pixel electrode electrically connected to the drain electrode through the contact hole Forming a step.

According to the display substrate and the manufacturing method thereof, the afterimage of the display screen is improved, and the display quality of the image is improved.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view of a display substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

1 and 2, a display substrate according to an exemplary embodiment of the present invention may include an insulating substrate 110, a gate wiring GL, a switching element TFT, a source wiring DL, a passivation layer 160, and a pixel. The electrode PE is included.

The insulating substrate 110 is made of a transparent material through which light can be transmitted. For example, the insulating substrate 110 is made of glass.

A plurality of gate lines GL extending in a first direction and a plurality of source lines DL extending in a second direction crossing the first direction are formed on the insulating substrate 110. The pixel portion P is defined in the insulating substrate 110 by the gate lines GL and the source lines DL.

The switching element TFT includes a gate electrode 120, a gate insulating layer 130, a channel layer 140, a source electrode 154, and a drain electrode 156.

The gate electrode 120 extends from the gate line GL and is formed of the same first metal pattern as the gate line GL. The first metal pattern has a structure in which the lower metal layer 122 made of any one selected from aluminum (Al) and aluminum neodymium (AlNd) and the upper metal layer 124 made of molybdenum (Mo) are sequentially stacked.

The lower metal layer 122 serves as a path for the electrical signal, which is a function of the wiring, and is formed of aluminum (Al) or aluminum neodymium (AlNd) having a low specific resistance.

The upper metal layer 124 is a layer formed to protect the lower metal layer 122, and prevents hillock of aluminum (Al) that appears in a subsequent process at a high temperature, and between the pixel electrode and the lower metal layer 122. It serves to lower the contact resistance.

The gate insulating layer 130 is formed on the insulating substrate 110 to cover the first metal pattern. The gate insulating layer 130 is made of a silicon nitride film SiNx.

The channel layer 140 is formed on the gate insulating layer 130 to correspond to the gate electrode 120 and is formed to have a wider line width than the source wiring and the drain electrode. The channel layer 140 includes a semiconductor layer 142 and an ohmic contact layer 144.

The semiconductor layer 142 is formed of an amorphous silicon (F-doped a-Si: H, hereinafter a-Si: H (F)) layer doped with fluorine (F).

In this case, when the content of fluorine (F) contained in the semiconductor layer 142 is less than 0.5%, the effect of the present invention does not appear. When the content of the fluorine (F) exceeds 5%, the amorphous silicon structure is destroyed, so that the characteristics of the semiconductor layer 142 may be reduced. It is deteriorated.

Therefore, the semiconductor layer 142 preferably includes fluorine (F) in a content of 0.5% to 5%.

The ohmic contact layer 144 is made of amorphous silicon (hereinafter, n + a-Si) doped with a high concentration of n-type impurities. The ohmic contact layer 144 is formed in a region overlapping the source electrode 154 and the drain electrode 156.

The source electrode 154 extends from the source wiring DL and is formed of the same second metal pattern as the source wiring DL.

The drain electrode 156 is also formed of a second metal pattern and is electrically connected to the pixel electrode PE. The drain electrode 156 is spaced apart from the source electrode 154 and is formed on the gate insulating layer 130 on the opposite side of the source electrode 154 with respect to the gate electrode 120. The source electrode 154 corresponds to the source electrode 154 of the switching element TFT, and the drain electrode 156 corresponds to the drain electrode 156 of the switching element TFT.

The source wiring DL is formed of the second metal pattern on the gate insulating layer 130 so as to cross the gate wiring GL.

The second metal pattern including the source wiring DL, the source electrode 154, and the drain electrode 156 is selected from a first layer 150a made of molybdenum (Mo), aluminum (Al), or aluminum neodymium (AlNd). The second layer 150b made of any one and the third layer 150c made of molybdenum (Mo) are sequentially stacked.

The first layer 150a is a layer formed to prevent diffusion of silicon (Si) in the channel layer into the second layer 150b.

The second layer 150b is a layer that serves as a path for the electric signal, which is an original function of the wiring.

The third layer 150c is a layer formed to protect the second layer 150b. The third layer 150c prevents the heellock of the second layer 150b, which may appear in a subsequent high temperature process, and prevents the pixel electrode PE. It is a layer formed to lower the contact resistance with.

The passivation layer 160 is formed on the gate insulating layer 130 to cover the second metal pattern. In the passivation layer 160, a contact hole 172 is formed to expose the drain electrode 156.

The pixel electrode PE is formed on the passivation layer 160 of the pixel portion P, and receives the pixel voltage from the drain electrode 156 through the contact hole 170. The pixel electrode PE is made of a transparent conductive material through which light can pass. For example, the transparent conductive material includes indium tin oxide (ITO) and indium zinc oxide (IZO).

Although not shown, the display substrate may further include a storage common wiring.

The storage common line is formed at the same time when the gate line GL is formed of the same first metal pattern as the gate line GL. The storage common line generates an electric field between the pixel electrode PE and maintains the pixel voltage applied to the pixel electrode PE.

3A to 3H are process diagrams illustrating a method of manufacturing the display substrate illustrated in FIG. 2.

Referring to FIG. 3A, the lower metal layer 122 and the upper metal layer 124 are sequentially stacked on the insulating substrate 110 and include a gate line GL and a gate electrode 120 through a photolithography process MASK 1. A first metal pattern is formed.

In this case, the lower metal layer 122 is made of any one selected from aluminum (Al) or aluminum neodymium (AlNd), and the upper metal layer 124 is made of molybdenum (Mo).

Referring to FIG. 3B, a silicon nitride layer (SiNx) 130 is formed on the insulating substrate 110 on which the first metal pattern is formed by a plasma enhanced chemical vapor deposition (PECVD) method. In this case, for example, xylene gas (SiH 4), hydrogen gas (H 2), and nitrogen gas (NH 3) are supplied into the PECVD chamber forming the silicon nitride film 130.

Referring to FIG. 3C, after the silicon nitride layer 130 is formed, a semiconductor layer 142 formed of a-Si: H (F) is formed by supplying a source gas including SiF 4 gas and SiH 4 gas into the PECVD chamber. .

When the mixed gas of the SiF4 gas and the SiH4 gas is 100%, when the ratio of the SiF4 gas is less than 25% or more than 80%, the formation of the semiconductor layer 142 made of a-Si: H (F) impossible. Therefore, the SiF 4 gas and the SiH 4 gas included in the source gas have a ratio of 1: 3 to 4: 1.

In addition, when the content of fluorine (F) contained in the semiconductor layer 142 is less than 0.5%, the effect of the present invention does not appear. When the content of the fluorine (F) is greater than 5%, the amorphous silicon structure is destroyed, so that the characteristics of the semiconductor layer 142 may be reduced. Since it is deteriorated, the semiconductor layer 142 is formed to contain 0.5% to 5% of fluorine (F).

After the semiconductor layer 142 is formed, for example, n + a-Si is supplied into the PECVD chamber by supplying, for example, xylene gas (SiH 4), hydrogen gas (H 2), nitrogen gas (NH 3), and hydrogen phosphide gas (PH 3). An ohmic contact layer 144 is formed.

Referring to FIG. 3D, a first layer 150a made of molybdenum (Mo), a second layer 150b made of aluminum (Al) or aluminum neodymium (AlNd), and molybdenum (Mo) are formed on the ohmic contact layer 144. The third layer (150c) consisting of sequentially stacked.

Referring to FIG. 3E, a second metal pattern including the source wiring DL, the source electrode 154, and the drain electrode 156 is formed through the photolithography process MASK 2. The drain electrode 156 is spaced apart from the source electrode 154 and is formed on the opposite side of the source electrode 154 with respect to the gate electrode 120.

Referring to FIG. 3F, the channel layer 140 including the semiconductor layer 142 and the ohmic contact layer 144 is etched using the second metal pattern as a mask.

The ohmic contact layer 144 formed between the source electrode 154 and the drain electrode 156 is etched to expose the semiconductor layer 142, and the channel layer 140 not covered by the second metal pattern is etched to form a gate. The insulating film 130 is exposed.

In this case, the channel layer 140 is anisotropically etched by the ions generated by plasma discharge of the reaction gas in the chamber at a predetermined pressure. Since the anisotropic etching is performed only in the vertical direction of the substrate surface, the lower portion of the second metal pattern used as the mask is not etched and is etched in a wider width than the second metal pattern. In addition, not only the channel layer 140 to be etched, but also a small amount of both cross-sectional views of the second metal pattern used as a mask are etched.

 Therefore, the channel layer 140 has a protruding portion L protruding from the second metal pattern. Since the protrusion L is not covered by the second metal pattern, an electron-electron pair is easily generated by being exposed to light energy.

Referring to FIG. 3G, after forming the passivation layer 160 to cover the channel layer 140, the contact hole 170 exposing a part of the drain electrode 156 through a photolithography process (MASK 3). ).

Subsequently, referring to FIG. 3H, a transparent conductive layer (not shown) is deposited on the passivation layer 160, and the pixel electrode PE is formed through the photolithography process MASK 4.

The pixel electrode PE is electrically connected to the drain electrode 156 through the contact hole 170. The pixel electrode PE is made of a transparent conductive material through which light can pass. For example, the pixel electrode 180 is made of ITO or IZO.

4A to 4B are conceptual views illustrating expected molecular structures of the semiconductor layer.

4A is a comparative example and is an expected molecular structure diagram of an a-Si: H semiconductor layer formed under general process conditions.

Figure 4b is an example, the expected molecular structure of the a-Si: H (F) semiconductor layer according to the present invention.

4A to 4B, in the examples, some of the Si—H bonds present in the comparative example are changed to Si—F bonds. Si-F bonds have a bond strength of 810 kJ / mol, which is about 2.4 times greater than that of Si-H, 340 kJ / mol. Therefore, in the embodiment, the coupling that is broken when light energy is applied from the outside is reduced.

5 is data obtained by analyzing a semiconductor layer by Secondary Ion Mass Spectroeter (SIMS).

5 represents the relative values of fluorine (F) contained in samples 1,2,3. Sample 1 is an a-Si: H semiconductor layer formed of a source gas not containing SiF4, and samples 2 and 3 are a-Si: H (F) semiconductor layers formed of a source gas containing SiF4 gas.

 At this time, samples 2 and 3 were formed by varying the amount of SiF4 gas added to the source gas.

Referring to FIG. 5, Sample 1 does not show a value of fluorine (F). In other words, it is understood that fluorine (F) does not naturally exist in the semiconductor layer unless the SiF 4 gas is supplied.

Samples 2 and 3 show that fluorine (F) is contained in the semiconductor layer by adding SiF 4 gas to the source gas. In addition, it can be seen that the amount of fluorine (F) contained in the semiconductor layer can be adjusted by adjusting the amount of SiF 4 gas to be added.

FIG. 6 is data obtained by analyzing an a-Si: H (F) semiconductor layer by Fourier Transform Infrared Spectrometry (FTIR).

Referring to FIG. 6, Si-F bonds are formed in an amorphous silicon (a-Si: H) semiconductor layer through a peak of a region corresponding to a Si-H bond and a peak of a region corresponding to a Si-F bond. You can check.

7A to 7B are graphs showing characteristic curves of the switching element TFT.

The horizontal axis of the graph represents the gate voltage Vg applied to the switching element, and the vertical side represents the drain current (Drein current, Id (A)).

7A to 7B, Comparative Examples are graphs showing characteristic curves of a switching device in which an a-Si: H semiconductor layer is deposited with a source gas not containing SiF 4 gas, and an embodiment includes a source including SiF 4 gas and SiH 4 gas. It is a graph which shows the characteristic curve of the switching element which deposited the a-Si: H (F) semiconductor layer by gas. In Example, 50 sccm of SiF4 gas was added as an example at the time of semiconductor layer deposition.

FIG. 7A is a graph illustrating a characteristic curve of the switching element TFT without providing light, and an area A indicated by a dotted line in FIG. 7A indicates an OFF leakage current region of the switching element.

Referring to the region A, it can be seen that the off leakage current of the switching element of the embodiment is lower than the off leakage current of the comparative example. The off leakage current causes fine driving of the switching element even when the switching element is turned off, and thus causes an afterimage. Therefore, it can be seen that the switching element of the embodiment is very advantageous for improvement of afterimage over the switching element of the comparative example.

7B is a graph showing characteristic curves of the switching element TFT in a state where light is provided. Region B indicated by a dotted line in FIG. 7B means an off leakage current region of the switching element.

Referring to the region B, it can be seen that the off leakage current of the example is lower than the off leakage current of the comparative example.

The Si-F bonds present in the a-Si: H (F) semiconductor layer of the Example are larger than the Si-H bonds present in the a-Si: H semiconductor layer of the Comparative Example, and thus are broken when light energy is applied. Loss of bonding is relatively small. Thus, since the occurrence of electron-hole pairs is reduced, the photo leakage current is also reduced.

In addition, since the SiFx (x = 1,2,3) included in the a-Si: H semiconductor layer of the embodiment exhibits a + polarity (+ 3, + 2, + 1), an electron pair is generated due to light energy. By effectively trapping electrons, the light leakage current is reduced.

That is, in the embodiment, the light leakage current is reduced by the a-Si: H (F) semiconductor layer, thereby reducing the off leakage current of the switching element. Therefore, the embodiment has a lower off-leakage current value than the comparative example, and is advantageous for improving afterimages.

[Table 1] is a numerical value of the minimum value of the off-leakage current shown in Figure 7b.

unit Comparative example Example OFF leakage current minimum A 1.3178E-12 4.679E-13

Referring to [Table 1], it can be seen that the off leakage current of the example decreased by about one third of the off leakage current of the comparative example.

8A to 8B are graphs showing characteristic curves of switching elements before and after applying driving stress in a state where light is provided.

8A is a graph showing a characteristic curve of a switching device including a a-Si: H semiconductor layer as a comparative example.

FIG. 8B is a graph showing a characteristic curve of a switching device including an a-Si: H (F) semiconductor layer as an embodiment.

8A to 8B, in the comparative example, since a difference occurs in the electrical characteristic curve before and after the driving stress, it can be seen that the driving characteristics of the switching element are unstable.

In the embodiment it can be seen that the driving characteristics of the switching element shows a constant characteristic regardless of the driving stress.

That is, the embodiment can ensure a stable driving characteristics by implementing a switching element stable to the driving stress, thereby improving the afterimage phenomenon due to the light leakage current.

As described above, the display substrate according to the present invention includes an a-Si: H (F) semiconductor layer formed of a source gas containing a SiF 4 gas. Since the a-Si: H (F) semiconductor layer contains Si-F bonds having a strong bond strength in the film, the bonds are hardly broken even when exposed to light energy. That is, even if the channel layer formed to protrude from the source / drain electrodes by the four-sheet process is exposed to light, generation of the electron-electron pair is reduced by the a-Si: H (F) semiconductor layer, thereby reducing the light leakage current do. In addition, since SiFx (x = 1,2,3) included in the a-Si: H (F) semiconductor layer has a + polarity (+ 3, + 2, + 1), electron electron pairs are generated due to light energy. By effectively trapping the caster, the light leakage current can be reduced.

 Reduction of the light leakage current lowers the off leakage current of the switching element and reduces the occurrence of afterimages by implementing a switching element that is stable to driving stress. As a result, the display quality of the display device can be improved.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (10)

Insulating substrate; A first metal pattern formed on the insulating substrate and including a gate wiring and a gate electrode of a switching device; A gate insulating film formed on the first metal pattern; A semiconductor layer formed on the gate insulating film and formed of an amorphous silicon layer containing fluorine (F); A second metal pattern formed on the semiconductor layer and including a source wiring and a source electrode and a drain electrode of the switching element; A passivation film formed on the second metal pattern and including a contact hole exposing a part of the drain electrode; And And a pixel electrode formed on the passivation layer and electrically connected to the drain electrode through the contact hole to apply a pixel voltage. The display substrate of claim 1, wherein the semiconductor layer comprises 0.5% to 5.0% of fluorine (F). The display substrate of claim 1, further comprising an ohmic contact layer formed by doping n + ions on the semiconductor layer and corresponding to a source electrode and a drain electrode of the switching element. The display substrate of claim 1, wherein the first metal pattern comprises a lower metal layer formed of any one selected from aluminum (Al) and aluminum neodymium (AlNd), and an upper metal layer formed of molybdenum (Mo). The method of claim 1, wherein the second metal pattern is a first layer made of molybdenum (Mo), a second layer made of any one selected from aluminum (Al) or aluminum neodymium (AlNd), a third layer made of molybdenum (Mo) The display substrate which was laminated | stacked sequentially. Forming a first metal layer over the insulating substrate; Etching the first metal layer to form a first metal pattern including a gate wiring and a gate electrode of a switching element connected to the gate wiring; Depositing a gate insulating film on the insulating substrate on which the first metal pattern is formed; Forming a semiconductor layer on the gate insulating layer using a source gas including a SiH 4 gas and a SiF 4 gas; Doping n + ions on the semiconductor layer to form an ohmic contact layer; Forming a second metal layer on the ohmic contact layer; Etching the second metal layer to form a second metal pattern including a source wiring and a source electrode and a drain electrode of the switching element; Etching a portion of the ohmic contact layer and the semiconductor layer using the second metal pattern as a mask; Forming a passivation film having a contact hole formed on the second metal pattern; And Forming a pixel electrode electrically connected to the drain electrode through the contact hole. The method of claim 6, wherein the ratio of the SiF 4 gas and the SiH 4 gas is 1: 3 to 4: 1. The method of claim 6, wherein the semiconductor layer comprises 0.5 to 5.0% of fluorine (F). The display substrate of claim 6, wherein the first metal layer is formed by sequentially stacking a lower metal layer made of any one selected from aluminum (Al) or aluminum neodymium (AlNd) and an upper metal layer made of molybdenum (Mo). Method of preparation. The method of claim 6, wherein the second metal layer comprises a first layer made of molybdenum (Mo), a second layer made of any one selected from aluminum (Al) or aluminum neodymium (AlNd), a third layer made of molybdenum (Mo) A method of manufacturing a display substrate, characterized in that laminated sequentially.

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