KR20070039312A - Semiconductor device having trench device isolation layer and method of forming the same - Google Patents

Abstract

A semiconductor device having a trench isolation film and a method of forming the same are provided. This device includes a liner, a lower device isolation film, and an upper device isolation film. The liner is formed on the substrate to cover the bottom surface of the trench defining the active region and the lower portions of both sides of the trench. The lower device isolation layer is located on the liner and fills the bottom of the trench. The upper device isolation film covers the liner and the lower device isolation film and fills the upper portion of the trench. At this time, the upper edge of the active region is rounded.

Description

A semiconductor device having a trench isolation layer and a method of forming the same {SEMICONDUCTOR DEVICE HAVING TRENCH DEVICE ISOLATION LAYER AND METHOD OF FORMING THE SAME}

1 and 2 are cross-sectional views illustrating a method of forming a semiconductor device having a conventional trench isolation layer.

3 is a cross-sectional view illustrating a semiconductor device having a trench isolation layer according to an embodiment of the present invention.

4 is a cross-sectional view taken along the line II ′ of FIG. 3.

5 to 10 are cross-sectional views illustrating a method of forming a semiconductor device having a trench isolation film according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device having a trench device isolation film and a method for forming the same.

Among the single components of the semiconductor device, the device isolation layer serves to electrically isolate neighboring semiconductor devices. According to the trend of high integration of semiconductor devices, trench isolation layers having a small planar area and excellent insulating properties have been widely used.

Typically, the trench isolation film may be formed by filling the trench formed in the semiconductor substrate with an oxide film. An oxide film filling the trench may stress the trench. A liner may be formed in the trench to buffer the stress of the oxide film. A method of forming a semiconductor device having a trench isolation film is described with reference to the drawings.

1 and 2 are cross-sectional views illustrating a method of forming a semiconductor device having a conventional trench isolation layer.

Referring to FIG. 1, a buffer oxide film pattern 2 and a hard mask pattern 3 that are sequentially stacked on a predetermined region of a semiconductor substrate 1 are formed. The hard mask pattern 3 is formed of a silicon nitride film. The semiconductor substrate 1 is etched using the hard mask pattern 3 as a mask to form a trench 4 defining an active region.

A thermal oxidation process is performed on the semiconductor substrate 1 to form sidewall oxide films 5 on the bottom and side surfaces of the trench 4. The liner film 6 is conformally formed on the entire surface of the semiconductor substrate 1. The liner film 6 is formed of a silicon nitride film.

An oxide film filling the trench 4 is formed on the entire surface of the semiconductor substrate 1, and the oxide film is planarized until the liner layer 6 on the hard mask pattern 3 is exposed to form an isolation layer 7. .

Referring to FIG. 2, the exposed liner layer 6 and the hard mask pattern 3 are removed by wet etching to form a liner 6a in the trench 4. In this case, upper ends of the liner 6a may be etched lower than the upper surface of the active region by the wet etching. As a result, a dent 8 may be generated at the boundary between the device isolation layer 7 and the active region. After the liner 6a is formed, the buffer oxide layer pattern 2 is removed by wet etching to expose the active region.

A gate oxide layer 9 is formed in the exposed active region, and a gate electrode 10 is formed on the gate oxide layer 9 to cross the active region. The gate oxide film 9 is formed of a thermal oxide film.

In the above-described method for forming a semiconductor device, when the liner 6a is formed, the upper ends of the liner 6a may be further etched by wet etching to generate the dent 8. As a result, the gate electrode 8 may fill the dent 8 to be in contact with the liner 6a. As a result, a hump phenomenon or an inverse narrow width effect may occur in the transistor including the gate electrode 8, thereby deteriorating characteristics of the semiconductor device. In addition, when the gate electrode 8 is a gate electrode of a high voltage transistor of a flash memory device, holes may be trapped in the liner 6a by a high voltage applied to the gate electrode 8. The liner 6a is formed of a silicon nitride film. The silicon nitride film has deep level traps. Accordingly, when a high voltage is applied to the gate electrode 8, holes may be trapped in the liner 6a. As a result, even if an off voltage is applied to the gate electrode 8, a part of the channel region adjacent to the dent 8 can be turned on by the liner 6a in which holes are trapped. As a result, a leakage current is generated between the source region and the drain region on both sides of the gate electrode 8, thereby deteriorating the characteristics of the semiconductor device.

On the other hand, according to the conventional method described above, the upper edge of the active region is formed in an angular shape. Accordingly, the electric field is concentrated at the upper edge of the active region, so that the channel region located at the upper edge of the active region may be turned on even at a voltage lower than the threshold voltage. As a result, the leakage current between the source region and the drain region can be further increased.

SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned general problems, and a technical object of the present invention is to provide a semiconductor device having a trench isolation film capable of preventing dents and a method of forming the same.

Another object of the present invention is to provide a semiconductor device having a trench isolation film capable of preventing electric field concentration due to an upper edge of an active region, and a method of forming the same.

Provided is a semiconductor device for solving the above technical problems. This device includes a liner, a lower device isolation film, and an upper device isolation film. The liner is formed in the substrate to cover the bottom surface of the trench defining the active region and the lower portions of both sides of the trench. The lower device isolation layer is positioned on the liner and fills a lower portion of the trench. The upper device isolation layer covers the liner and the lower device isolation layer and fills an upper portion of the trench. At this time, the upper edge of the active region is rounded.

Specifically, the device may further include a thermal oxide film formed on the upper side of the trench. In this case, the upper device isolation film further covers the thermal oxide film. The upper device isolation layer may be formed of an insulating material having an etch selectivity with respect to the liner. The device may further include a sidewall oxide layer formed on a bottom surface of the trench and a lower portion of both sides of the trench. In this case, the liner covers the sidewall oxide layer.

Provided are a method of forming a semiconductor device for solving the above technical problems. This method includes the following steps. A buffer pattern and a hard mask pattern sequentially stacked on the substrate are formed, and the substrate is etched using the hard mask pattern as a mask to form a trench defining an active region. A liner is formed to cover the bottom surface of the trench and lower portions of both sides of the trench, and a lower device isolation layer positioned on the liner to fill the lower portion of the trench. The upper edge of the active region is formed in a round shape. An upper device isolation layer filling the upper portion of the trench is formed to cover the lower device isolation layer and the liner, and the hard mask pattern and the buffer insulation pattern are removed to expose the active region.

In detail, the forming of the lower device isolation layer and the liner and the forming of the upper corner of the active region in a round shape may include the following steps. A liner film is conformally formed on the substrate having the trench. The lower device isolation layer is formed on the liner layer, but the liner layer positioned higher than the lower device isolation layer is exposed. Isotropic etching is performed on the liner layer to form the liner. The hard mask pattern is isotropically etched to expose the buffer insulating pattern on the edge of the active region, and the exposed buffer insulating pattern is removed to expose the upper edge of the active region. The upper edge of the exposed active region is thermally oxidized to form a rounded upper edge of the active region.

The method may further include forming a sidewall oxide film on the bottom and both sides of the trench. In this case, when forming the liner, the sidewall oxide film formed on the upper side of the trench is exposed, and the upper edge of the active region is exposed by removing the exposed buffer insulating pattern and the exposed sidewall oxide film.

Isotropically etching the exposed liner layer and isotropically etching the hard mask pattern may be performed in-situ. When removing the buffer insulating pattern on the edge of the active region, the upper surface of the lower device isolation layer may be recessed. The method may further include removing the thermal oxide film on the rounded upper corner of the active region before forming the upper device isolation layer. The upper device isolation layer may be formed of an insulating material having an etch selectivity with respect to the liner.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art. In the drawings, the thicknesses of layers (or films) and regions are exaggerated for clarity. In addition, where it is said that a layer (or film) is "on" another layer (or film) or substrate, it may be formed directly on another layer (or film) or substrate or a third layer between them. (Or membrane) may be interposed. Portions denoted by like reference numerals denote like elements throughout the specification.

3 is a cross-sectional view illustrating a semiconductor device having a trench isolation layer in accordance with an embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line II ′ of FIG. 3.

3 and 4, a trench 106 defining an active region is disposed in a predetermined region of the semiconductor substrate 100 (hereinafter, referred to as a substrate). The liner 110a covers the bottom surface of the trench 106 and the lower portions of both sides of the trench 106. That is, the upper ends of the liner 110a are positioned lower than the upper surface of the active area.

A lower device isolation layer 112a ′ may be disposed on the liner 110a to fill the lower portion of the trench 106. The lower device isolation layer 112a ′ may have a height close to the upper ends of the liner 110a. An upper device isolation layer 116 covers the lower device isolation layer 112a ′ and the liner 110a. The upper device isolation layer 116 fills an upper portion of the trench 106. The upper device isolation layer 116 may be formed of an insulating material having an etch selectivity with the liner 110a.

The sidewall oxide layer 108 may be disposed on the bottom surface of the trench 106 and the lower portions of both sides of the trench 106. In this case, the liner 110a covers the sidewall oxide layer 108. A thermal oxide layer 114 may be disposed on the upper sidewall of the trench 106 on the sidewall oxide layer 108. In this case, the upper device isolation layer 116 further covers the thermal oxide layer 114. Alternatively, the thermal oxide film 114 may be omitted. In this case, the upper device isolation layer 116 may directly contact the upper sidewall of the trench 106.

The upper edge of the active region is preferably rounded. The rounded upper corner of the active region may be located higher than the liner 110a.

A gate electrode 120 crosses the active region, and a gate insulating layer 118 is formed between the gate electrode 120 and the active region. The gate insulating layer 118 may be formed of a thermal oxide layer. Source / drain regions 122 are formed in the active region on both sides of the gate electrode 120. The gate electrode 120 is spaced apart from the liner 110a by the upper device isolation layer 116.

The gate electrode 120 is a conductive material doped polysilicon, metal (ex, tungsten or molybdenum, etc.), metal silicide (ex, tungsten silicide, cobalt silicide, nickel silicide or titanium silicide, etc.) and conductive metal nitride (ex, Titanium nitride or tantalum nitride). The gate electrode 120 may be a gate electrode of a MOS transistor. In particular, the gate electrode 120 may be a gate electrode of a high voltage MOS transistor used in an EEPROM device. Alternatively, the gate electrode 120 may correspond to a floating gate electrode included in a memory cell of an e-prohm element. When the gate electrode 120 is a floating gate electrode, the gate electrode 120 may be formed of doped polysilicon.

In the above-described semiconductor device, the liner 110a is positioned lower than the top surface of the active region, and the upper device isolation layer 116 covers the liner 110a. Thereby, the dent by the overetching of the conventional liner can be prevented. In addition, the upper device isolation layer 116 is interposed between the gate electrode 120 and the liner 110a. As a result, the gate electrode 120 and the liner 110a are spaced apart from each other, and as a result, the conventional problems caused by the dent and the problem caused by the contact between the liner and the gate electrode can be solved. The upper edge of the active region has a rounded shape, thereby solving the problem caused by concentrating an electric field on the angled upper edge of the conventional active region.

Next, a method of forming a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

5 to 10 are cross-sectional views illustrating a method of forming a semiconductor device having a trench isolation film according to an embodiment of the present invention.

Referring to FIG. 5, a buffer insulating pattern 102 and a hard mask pattern 104 that are sequentially stacked on a predetermined region of the substrate 100 are formed. The hard mask pattern 104 includes an opening that exposes a predetermined region of the substrate 100. The buffer insulating pattern 102 may be formed of a silicon oxide layer, and the hard mask pattern 104 may be formed of a silicon nitride layer.

Using the hard mask pattern 104 as an etching mask, the substrate 100 is etched to form a trench 106 defining an active region. A first thermal oxidation process is performed on the substrate 100 having the trench 106 to form sidewall oxide films 108 on the bottom and both sides of the trench 106. The first thermal oxidation process may be performed to heal etch damage on the bottom and both sides of the trench 106.

A liner layer 110 is conformally formed on the entire surface of the substrate 100, and a first insulating layer 112 is formed on the liner layer 110 to fill the trench 106. The liner layer 110 may be formed of a silicon nitride layer. The first insulating layer 112 may be formed of a silicon oxide film, particularly, a high density plasma silicon oxide film having excellent gap-fill characteristics.

Referring to FIG. 6, the first insulating layer 112 is planarized until the liner layer 110 disposed on the top surface of the hard mask pattern 104 is exposed. Subsequently, the planarized first insulating layer 112 is recessed to form a lower device isolation layer 112a filling the lower portion of the trench 106. The upper surface of the lower device isolation layer 112a has a lower height than the upper surface of the active region. Accordingly, the liner layer 110 formed on the upper portions of both side surfaces of the trench 106 are exposed.

Referring to FIG. 7, the liner layer 110 is etched by wet etching, which is isotropic etching, to form a liner 110a. In this case, all of the liner layer 110 positioned higher than the lower device isolation layer 112a is removed. The liner 110a covers a bottom surface of the trench 106 and a lower portion of both sides of the trench 106. That is, the upper ends of the liner 110a are formed lower than the upper surface of the active area. As a result, the sidewall oxide layer 108 formed on upper portions of both sides of the trench 106 is exposed.

The exposed hard mask pattern 104 isotropically etched to expose the buffer insulating pattern 102 located on the edge of the active region. Both the hard mask pattern 104 and the liner 110a may be formed of a silicon nitride film. In this case, during the isotropic etching of the hard mask pattern 104, the liner 110a may be further etched so that upper ends of the liner 110a may be lower than an upper surface of the lower device isolation layer 112a. When the liner layer 110 and the hard mask pattern 104 are formed of the same material, isotropically etching the liner layer 110 and isotropically etching the hard mask pattern 104 may be performed in situ. It is preferable to carry out in-situ. The isotropically etched hard mask pattern 104 ′ may have a smaller width than the active region.

Referring to FIG. 8, the exposed buffer insulating pattern 104 and the exposed sidewall oxide layer 108 are removed by wet etching, which is an isotropic etching, to expose the upper edge of the active region. The buffer insulating pattern 104 and the sidewall oxide layer 108 may be formed of a silicon oxide layer. In this case, the lower device isolation layer 112a may also be formed of a silicon oxide layer. Accordingly, during isotropic etching that exposes the upper edge of the active region, an upper surface of the lower device isolation layer 112a may also be recessed. An upper surface of the recessed lower device isolation layer 112a ′ may have a height close to that of the upper end of the liner 110a.

Subsequently, a second thermal oxidation process is performed on the substrate 100 to form an upper edge of the exposed active region in a round shape. In this case, a thermal oxide film 114 is formed on the upper edge of the active region by the second thermal oxidation process.

Referring to FIG. 9, a second insulating film is formed on the substrate 100 to fill the upper portion of the trench 106, and the second insulating film is planarized until the hard mask pattern 104 ′ is exposed. The separator 116 is formed. The upper device isolation layer 116 fills an upper portion of the trench 106 and covers the lower device isolation layer 112a 'and the liner 110a. In addition, the upper device isolation layer 116 may cover the thermal oxide layer 114. The upper device isolation layer 116 may be formed of an insulating material having an etch selectivity with respect to the liner 110a. For example, the upper device isolation layer 116 may be formed of a silicon oxide layer.

Meanwhile, before the upper device isolation layer 116 is formed, the thermal oxide layer 114 may be removed to expose the rounded upper corner of the active region. In this case, the upper device isolation layer 116 may directly contact the rounded upper corner of the active region.

Referring to FIG. 10, the exposed hard mask pattern 104 ′ and the buffer insulation pattern 102 are continuously removed to expose the top surface of the active region. When removing the buffer insulating pattern 102 under the hard mask pattern 104 ′, the upper device isolation layer 116 and the thermal oxide layer 114 may be recessed.

Subsequently, the gate insulating layer 118 and the gate electrode 120 of FIGS. 3 and 4 are formed on the active region, and the source / drain of FIG. 4 is implanted by implanting impurity ions using the gate electrode 120 as a mask. Form regions 122. As described above, the gate electrode 120 is spaced apart from the liner 110a by the upper device isolation layer 116. As a result, the semiconductor device of FIGS. 3 and 4 may be implemented.

According to the above-described method of forming a semiconductor device, a liner 110a lower than an upper surface of the active region is formed, and an upper device isolation layer 116 covering the liner 110a is formed. Subsequently, the hard mask pattern 104 ′ is removed. As a result, the liner 110a is protected when the hard mask pattern 104 'is removed. As a result, the dents caused by the overetching of the conventional liner can be prevented. In addition, the gate electrode is spaced apart from the liner 110a and the gate electrode 120 by the upper device isolation layer 116. In addition, the upper edge of the active region is formed in a round shape. As a result, it is possible to solve the problems caused by the conventional dent, the problem caused by the contact between the liner and the gate electrode, and the problem that the electric field is concentrated at angled edges of the active region.

As described above, according to the present invention, the liner is formed lower than the active region, and the upper device isolation layer covering the liner is formed. As a result, it is possible to prevent the dent due to over-etching of the conventional liner, and to separate the liner and the gate electrode from each other. In addition, by forming the upper edge of the active region in a round shape, it is possible to prevent the phenomenon that the electric field is concentrated on the angular corner of the conventional active region.

Claims (13)

A liner formed on the substrate to cover the bottom surface of the trench defining an active region and a lower portion of both sides of the trench; A lower device isolation layer on the liner and filling the lower portion of the trench; And And an upper device isolation layer covering the liner and the lower device isolation layer and filling an upper portion of the trench, wherein the upper edge of the active region is rounded. The method of claim 1, And a thermal oxide film formed on the upper side of the trench, wherein the upper device isolation layer further covers the thermal oxide film. The method according to claim 1 or 2, The upper device isolation layer is formed of an insulating material having an etch selectivity with respect to the liner. The method according to claim 1 or 2, And a sidewall oxide film formed on a bottom surface of the trench and lower portions of both sides of the trench, wherein the liner covers the sidewall oxide film. The method according to claim 1 or 2, A gate electrode crossing the active region; A gate insulating layer interposed between the gate electrode and the active region; And And source / drain regions formed in the active regions on both sides of the gate electrode. Forming a buffer pattern and a hard mask pattern sequentially stacked on the substrate; Forming a trench defining an active region by etching the substrate using the hard mask pattern as a mask; Forming a bottom liner of the trench, a liner covering lower portions of both sides of the trench, and a lower device isolation layer on the liner and filling the bottom portion of the trench; Forming an upper edge of the active region in a round shape; Forming an upper device isolation layer filling an upper portion of the trench to cover the lower device isolation layer and the liner; And And removing the hard mask pattern and the buffer insulating pattern to expose the active region. The method of claim 6, Forming the lower device isolation layer and the liner and forming the upper edge of the active region in a round shape, Conformally forming a liner film on the substrate having the trench; Forming the lower device isolation layer on the liner layer, exposing the liner layer positioned higher than the lower device isolation layer; Forming the liner by isotropic etching the liner layer; Isotropically etching the hard mask pattern to expose the buffer insulating pattern on an edge of the active region; Exposing an upper edge of the active region by removing the exposed buffer insulation pattern; And And forming a rounded upper edge of the active region by performing a thermal oxidation process on the exposed upper edge of the active region. The method of claim 7, wherein Before forming the liner film, Forming a sidewall oxide film on the bottom and both sides of the trench further, When the liner is formed, a sidewall oxide layer formed on an upper side of the trench is exposed, and an upper edge of the active region is exposed by removing the exposed buffer insulation pattern and the exposed sidewall oxide layer. Method of formation. The method of claim 7, wherein Isotropically etching the exposed liner layer, and isotropically etching the hard mask pattern, wherein the semiconductor device is formed in-situ. The method of claim 7, wherein And removing the buffer insulating pattern on the edge of the active region, the upper surface of the lower device isolation layer is recessed. The method of claim 7, wherein Before forming the upper device isolation layer, And removing the thermal oxide film on the rounded upper edge of the active region. The method according to any one of claims 6 to 11, The upper device isolation layer is formed of an insulating material having an etch selectivity with respect to the liner. The method according to any one of claims 6 to 11, Forming a gate insulating film on the exposed active region; Forming a gate electrode crossing the active region on the gate insulating layer; And And forming source / drain regions in the active region on both sides of the gate electrode.

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