KR20070036559A - Device for driving global signal - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a global signal driving apparatus. In particular, a technique for reducing skew for each bank of global signals by differently controlling the driving capability of the global signal driver for each bank by using bank addresses when driving the global signals. Initiate. The present invention is a drive control unit for decoding a bank address and outputs a plurality of drive control signals set differently according to the distance that the global signal is transmitted to the plurality of banks, and the global signal according to the selective activation state of the plurality of drive control signals And a driver configured to control the driving size of the global signal to different values corresponding to the distances transmitted to the plurality of banks and output the same to the plurality of banks.

Global, signal, drive, bank, address

Description

Global signal driving device {Device for driving global signal}

1 is a block diagram of a conventional global signal driving device.

2 is a view for explaining the problem of the conventional global signal driving device.

3 is a signal waveform diagram of a conventional global signal driver.

4 is a block diagram of a global signal driving device according to the present invention;

FIG. 5 is a detailed circuit diagram of the driving controller of FIG. 4. FIG.

6 is a detailed circuit diagram of a driving unit of FIG. 4.

7 is a signal waveform diagram according to the global signal drive device of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a global signal driver, and more particularly, discloses a technique for reducing skew for each bank of global signals by differently controlling the driving capability of the global signal driver for each bank using a bank address.

Semiconductor chips, especially Synchronous Dynamic Random Access Memory (SDRAM), have increased operating frequencies and memory capacities, resulting in larger chip sizes. Therefore, it is difficult to secure margins between signals due to skew of banks of global signals, thereby limiting the performance of the entire chip.

1 is a block diagram of a conventional global signal driving device.

The conventional global signal driving apparatus includes an input buffer 10, a data controller 20, an address / command controller 30, a driver 40, and a bank 50.

Here, the input buffer 10 buffers and outputs the input data DATA, the command signal CMD, and the address ADD. The data controller 20 controls and outputs the data buffered through the input buffer 10. The address / command controller 30 controls and outputs the buffered address and command signals through the input buffer 10.

The driver 40 drives the data applied from the data control unit 20 and the address and command signals applied from the address / command control unit 30 to output the data D, the command signal C, and the bank control signal BC. . Here, all the data D, the command signal C, and the bank control signal BC output from the driver 40 are referred to as global signals. The bank 50 is controlled in accordance with the data D applied from the driver 40, the command signal C, and the bank control signal BC.

By the way, the conventional global signal drive device having such a configuration determines the size of the drive unit 40 based on the farthest side from the interval between the respective banks 50. Accordingly, in all cases, the driving unit 40 having the same size is used.

For example, as shown in the configuration diagram of FIG. 2, the driving unit 41 drives the global signal GS1 adjacent to banks 0 and 1 in the 8 bank product. The driver 42 drives the global signal GS2 adjacent to the banks 6 and 7. At this time, in the case of the global signal GS1, the time for reaching bank 0.1 is shorter than the time for reaching banks 6 and 7. On the other hand, for the global signal GS2, the time to reach banks 6 and 7 is shorter than the time to reach banks 0 and 1.

If the global signal GS2 is to be high while the global signal GS1 is high, the skew of the two global signals GS1 and GS2 in each bank acts in the opposite direction. As a result, it is difficult to secure a margin between the global signals GS1 and GS2. Therefore, as shown in FIG. 3, when the actual skew becomes larger than the prediction of the simulation, a fail A occurs in the bank 0 from the global signal GS2 outside the high period of the global signal GS1.

In addition, even when driving the global signals GS1 and GS2 to be used in the nearest banks, the driver having the same size as the driving size of the farthest bank is used as it is, which causes a large current consumption.

The present invention has been made to solve the above problems, and in particular, the driving capability of the global signal driver for each bank according to the distance at which the global signal is transmitted using the bank address for a global signal used in only one bank at a time. The goal is to reduce skew per bank and reduce the current consumed to drive the global signal.

Accumulation capacitor control apparatus of the present invention for achieving the above object comprises a drive control unit for decoding a bank address and outputs a plurality of drive control signals set differently according to the distance the global signal is transmitted to the plurality of banks; And a driving unit configured to control the driving size of the global signal to a different value and output the same to a plurality of banks according to a distance in which the global signal is transmitted to the plurality of banks according to a selective activation state of the plurality of driving control signals. It is done.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a block diagram of a global signal driving apparatus according to the present invention.

The present invention includes an input buffer 100, a data controller 200, an address / command controller 300, a drive controller 400, a driver 500, and a bank 600.

Here, the input buffer 100 buffers and outputs the input data DATA, the command signal CMD, and the address ADD. The data controller 200 controls and outputs the data buffered through the input buffer 100. The address / command controller 300 controls and outputs the buffered address and the command signal through the input buffer 100.

In addition, the driving controller 400 uses a plurality of driving control signals DCON having different values for respective positions of the banks 600 using the bank addresses BA <0: 2> among the buffered addresses applied from the input buffer 100. Outputs The driver 500 drives data applied from the data control unit 200, command signals applied from the address / command control unit 300, and addresses with different driving capability sizes determined according to the plurality of driving control signals DCON. The command signal C and the bank control signal BC are output to the bank 600.

Here, the data D output from the driver 500, the command signal C, and the bank control signal BC are referred to as global signals GS1 and GS2. In addition, the operation of the bank 600 is controlled according to the data D applied from the driver 500, the command signal C, and the bank control signal BC.

FIG. 5 is a detailed circuit diagram of the driving controller 400 of FIG. 4.

The driving controller 400 includes a plurality of NAND gates ND1 to ND12, and a plurality of inverters IV1 to IV3.

Here, the NAND gate ND1 performs a NAND operation on the bank addresses BA <0>, BA <1>, BA <2>, and outputs a bank selection signal B <7>. The NAND gate ND2 performs a NAND operation on the bank address BA <0>, the bank address BA <1>, and the bank address BA <2> inverted by the inverter IV1, and outputs a bank selection signal B <6>. The NAND gate ND3 performs a NAND operation on the bank address BA <0>, the bank address BA <1> and the bank address BA <2> inverted by the inverter IV2, and outputs a bank selection signal B <5>. The NAND gate ND4 performs a NAND operation on the bank address BA <0> inverted by the inverter IV1, the bank address BA <1> and the bank address BA <2> inverted by the inverter IV2, and outputs a bank selection signal B <4>. .

The NAND gate ND5 performs a NAND operation on the bank address BA <0>, the bank address BA <1>, and the bank address BA <2> inverted by the inverter IV3, and outputs a bank selection signal B <3>. The NAND gate ND6 NAND-operates the bank address BA <0> inverted by the inverter IV1, the bank address BA <0>, and the bank address BA <2> inverted by the inverter IV3, and outputs a bank selection signal B <1>. do. The NAND gate ND7 performs a NAND operation on the bank address BA <0>, the bank address BA <1> inverted by the inverter IV2, and the bank address BA <2> inverted by the inverter IV3, and outputs a bank selection signal B <0>. .

The NAND gate ND9 performs NAND operation on the bank selection signals B <7> and B <6> to output the drive control signal DCON <67>. The NAND gate ND10 performs a NAND operation on the bank selection signals B <5> and B <4> to output the drive control signal DCON <45>. The NAND gate ND11 performs a NAND operation on the bank selection signals B <3> and B <2> to output the drive control signal DCON <23>. The NAND gate ND12 performs a NAND operation on the bank selection signals B <1> and B <0> to output the drive control signal DCON <01>.

FIG. 6 is a detailed circuit diagram of the driver 500 of FIG. 4.

The driver 500 includes a plurality of inverters IV4 to IV8, a plurality of transfer gates T1 to T4, and voltage supply means. Here, the voltage supply means includes a plurality of PMOS transistors P1 to P4 and a plurality of NMOS transistors N1 to N4.

Here, the transfer gate T1 selectively outputs the drive control signal DCON <67> inverted by the inverter IV5 and the input signal IN inverted by the inverter IV4 in accordance with the state of the drive control signal DCON <67>. The transfer gate T2 selectively outputs the drive control signal DCON <45> inverted by the inverter IV6 and the input signal IN inverted by the inverter IV4 in accordance with the state of the drive control signal DCON <45>.

Then, the transfer gate T3 selectively outputs the drive control signal DCON <23> inverted by the inverter IV7 and the input signal IN inverted by the inverter IV4 in accordance with the state of the drive control signal DCON <23>. The transfer gate T4 selectively outputs the drive control signal DCON <01> inverted by the inverter IV8 and the input signal IN inverted by the inverter IV4 according to the state of the drive control signal DCON <01>.

In addition, the PMOS transistors P1 to P4 are connected in series between the power supply voltage VDD applying stages, and outputs of the transfer gates T1 to T4 are applied through respective gate terminals. Here, the output terminal of the transfer gate T1 is connected to the gate terminals of the PMOS transistors P1 to P4, and the output terminal of the transfer gate T2 is connected to the gate terminals of the PMOS transistors P1 to P3. The output terminal of the transfer gate T3 is connected to the PMOS transistors P1 and P2, and the output terminal of the transfer gate T4 is connected to the PMOS transistor P1.

In addition, the NMOS transistors N1 to N4 are connected in series between the ground voltage VSS applying terminals, and outputs of the transfer gates T1 to T4 are applied through respective gate terminals. Here, the output terminal of the transfer gate T1 is connected to the gate terminals of the NMOS transistors N1 to N4, and the output terminal of the transfer gate T2 is connected to the gate terminals of the NMOS transistors N1 to N3. The output terminal of the transfer gate T3 is connected to the NMOS transistors N1 and N2, and the output terminal of the transfer gate T4 is connected to the NMOS transistor N1.

Here, the input signal IN represents data applied from the data control unit 200, an address and a command signal applied from the address / command control unit 300. The output signal OUT output through the node B represents the bank control signal BC output to the bank 600.

Referring to the operation of the present invention having such a configuration as follows.

In the embodiment of the present invention, it is assumed that eight banks 0 to 7 are arranged as shown in FIG. 2, and banks 0.1, 2, 3, 4, 5, 6 and 7 have the same skew.

Accordingly, the driving controller 400 decodes the bank addresses BA <0: 2> from the buffered addresses applied from the input buffer 100, thereby driving the plurality of driving control signals DCON <01>, DCON <23>, and DCON <45. Output>, DCON <67> with different values.

That is, the driving controller 400 outputs the driving control signal DCON <01> high when the input bank address BA <0: 2> is 000 (bank 0) or 001 (bank 1). The driving controller 400 outputs the driving control signal DCON <23> high when the input bank address BA <0: 2> is 010 (bank 2) or 011 (bank 3).

When the input bank address BA <0: 2> is 100 (bank 4) or 101 (bank 5), the driving controller 400 outputs the driving control signal DCON <45> high. The driving controller 400 outputs the driving control signal DCON <67> high when the input bank address BA <0: 2> is 110 (bank 6) or 111 (bank 7).

The driving unit 500 of FIG. 6 is a driving unit 41 adjacent to the banks 0 and 1 shown in FIG. 2. That is, the driver 500 is disposed closest to the banks 0 and 1 and is disposed farthest from the banks 6 and 7.

When the driver 500 drives the data D transmitted to the banks 6 and 7, and the command signal C and the bank control signal BC, the driving control signal DCON <67> becomes high. Accordingly, among the transfer gates T1 to T4, the transfer gate T1 is turned on so that the input signals IN applied from the data control unit 200 and the address / command control unit 300 are four PMOS transistors P1 to P4 and four NMOS transistors N1 to N4. Are all applied to.

Therefore, the PMOS transistors P1 to P4 or the NMOS transistors N1 to N4 are turned on to drive the data D, the command signal C, and the bank control signal BC, which are transferred to the banks 6 and 7, with the greatest driving capability.

On the other hand, when the driver 500 wants to drive the data D transmitted to the banks 4 and 5, the command signal C and the bank control signal BC, the driving control signal DCON <45> becomes high. Accordingly, among the transfer gates T1 to T4, the transfer gate T2 is turned on so that the input signals IN applied from the data control unit 200 and the address / command control unit 300 are three PMOS transistors P1 to P3 and three NMOS transistors N1 to N3. Is applied to.

Therefore, the PMOS transistors P1 to P3 or the NMOS transistors N1 to N3 are turned on to drive the data D and the command signal C and the bank control signal BC which are transmitted to the banks 4 and 5 with a smaller driving capability than the banks 6 and 7.

Similarly, the driving unit 500 becomes high when the data D transmitted to the banks 2 and 3 and the command signal C and the bank control signal BC are to be driven. Accordingly, among the transfer gates T1 to T4, the transfer gate T3 is turned on so that the input signals IN applied from the data control unit 200 and the address / command control unit 300 are two PMOS transistors P1 and P2 and two NMOS transistors N1 and N2. Is applied to.

Accordingly, the PMOS transistors P1, P2 or the NMOS transistors N1, N2 are turned on to drive the data D, the command signal C, and the bank control signal BC, which are transferred to the banks 2 and 3, with a larger driving capacity than the banks 0 and 2.

On the other hand, when the driver 500 tries to drive the data D transmitted to the banks 0 and 1, and the command signal C and the bank control signal BC, the driving control signal DCON <01> becomes high. Accordingly, among the transfer gates T1 to T4, the transfer gate T4 is turned on and the input signal IN applied from the data controller 200 and the address / command controller 300 is applied to one PMOS transistor P1 and one NMOS transistor N1.

Therefore, the PMOS transistor P1 or the NMOS transistor N1 is turned on to drive the data D and the command signal C and the bank control signal BC which are transmitted to the banks 0 and 1 with the smallest driving capability.

Here, the plurality of PMOS transistors P1 to P4 and the plurality of NMOS transistors N1 to N4 need not be the same in size, and PMOS transistors and NMOS transistors having different sizes may be used according to the skew characteristic of each global signal.

For example, in the 8-bank product, the data D driven by the driver 500 adjacent to the banks 0 and 1, the command signal C and the bank control signal BC are called the global signals GS1, and are farthest from the banks 0 and 1, respectively. The data D driven by the driver 500 adjacent to the banks 6 and 7, and the command signal C and the bank control signal BC are referred to as the global signal GS2.

At this time, in the case of the global signal GS1, the time for reaching bank 0.1 is shorter than the time for reaching banks 6 and 7. On the other hand, for the global signal GS2, the time to reach banks 6 and 7 is shorter than the time to reach banks 0 and 1.

Accordingly, the present invention uses the bank addresses BA <0: 2> with respect to the global signals GS1 and GS2 used in only one bank 600 at a time to transmit the global signals GS1 and GS2 to each bank 600. Accordingly, the driving ability of the driving unit 500 is controlled differently.

Therefore, assuming that global signal GS2 should be high while the global signal GS1 is high, as shown in FIG. 7, even if the actual skew becomes larger than the prediction of the simulation, the global signal GS2 is the global signal GS1 in the bank 600. It does not go out of the high section of.

Meanwhile, in another embodiment of the present invention, four banks of eight banks are described as having the same skew. However, the present invention is not limited thereto, and the eight banks may be extended so that the skew is controlled separately, but not more than four. It is also possible to reduce to control skew by dividing into banks of. That is, according to the present invention, the skew can be divided and controlled as necessary regardless of the number of banks.

As described above, the present invention has the following effects.

First, the bank skew may be reduced by controlling the driving capability of the driver for each bank differently according to the distance at which the global signal is transmitted using the bank address.

Secondly, a small size driver is used to drive a near bank, and a large size driver is used to drive a distant bank, thereby providing an effect of reducing current consumed to drive a global signal.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (13)

A driving controller which decodes a bank address and outputs a plurality of driving control signals differently set according to a distance at which a global signal is transmitted to the plurality of banks; And A driving unit configured to control the driving size of the global signal to a different value and output the same to the plurality of banks according to a distance in which the global signal is transmitted to the plurality of banks according to a selective activation state of the plurality of driving control signals; Global signal driving apparatus comprising a. The apparatus of claim 1, wherein the global signal includes any one of data, an address, and a command signal. The method of claim 1, wherein the driving unit drives the global signal at a first driving size as the distance between the global signals is transmitted to the plurality of banks increases, and the distance from which the global signals are transmitted to the plurality of banks is farther away. And driving the global signal at a second driving size larger than the first driving size. The method of claim 1, wherein the drive control unit Inverting means for inverting the bank address; A plurality of first NAND gates NAND-operating the output of the inverting means and the bank address to output a plurality of bank selection signals; And And a plurality of second NAND gates for NAND-operating the plurality of bank selection signals to output the plurality of driving control signals. The method of claim 1, wherein the driving unit An inverter for inverting the global signal; A plurality of transfer gates selectively turned on according to an activation state of the plurality of drive control signals to selectively output the outputs of the inverter; And And a voltage supply means for outputting the global signal with different voltage values according to outputs of the plurality of transmission gates. The method of claim 5, wherein the voltage supply means A plurality of PMOS transistors connected in series with a power supply voltage terminal, each gate terminal of which is selectively connected to an output terminal of the plurality of transmission gates; And And a plurality of NMOS transistors connected in series to a ground voltage terminal, each gate terminal of which is selectively connected to output terminals of the plurality of transmission gates. 7. The global signal driving device of claim 6, wherein the plurality of transmission gates have the same number as the plurality of PMOS transistors. 7. The global signal driving device of claim 6, wherein the plurality of transmission gates have the same number as the plurality of NMOS transistors. 7. The global signal driving apparatus of claim 6, wherein gate terminals of the plurality of PMOS transistors and the plurality of NMOS transistors are respectively connected correspondingly. The method of claim 6, wherein the plurality of transmission gates A first transfer gate having a gate terminal and an output terminal of the plurality of PMOS transistors respectively connected; A second transfer gate connected to the plurality of PMOS transistor gate terminals and an output terminal thereof, the second transfer gate connected to a smaller number of PMOS transistors than the first transfer gate; A third transfer gate connected to the plurality of PMOS transistor gate terminals and an output terminal thereof, the third transfer gate connected to a smaller number of PMOS transistors than the second transfer gate; And And a fourth transmission gate connected to one of the gate terminals of the plurality of PMOS transistors and an output terminal thereof. The method of claim 6, wherein the plurality of transmission gates A fourth transfer gate having a gate terminal and an output terminal of the plurality of NMOS transistors respectively connected; A fifth transfer gate connected to the plurality of NMOS transistor gate terminals and an output terminal thereof, and connected to the NMOS transistor having a smaller number than the fourth transfer gate; A sixth transfer gate connected to the plurality of NMOS transistor gate terminals and an output terminal thereof, the sixth transfer gate connected to a smaller number of NMOS transistors than the fifth transfer gate; And And a seventh transmission gate connected to one of the gate terminals of the plurality of NMOS transistors and an output terminal thereof. The method of claim 6, wherein the voltage supply means When the first drive control signal is activated, both the plurality of PMOS transistors and the plurality of NMOS transistors are activated, and when the second drive control signal is activated, one of the plurality of PMOS transistors and the plurality of NMOS transistors. And one NMOS transistor enabled. The global signal driving device of claim 6, wherein the plurality of PMOS transistors and the plurality of NMOS transistors have different sizes.

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