KR20070036549A - Delay locked loop circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay locked loop circuit, and more particularly, discloses a technique for outputting a clock having a multi-phase to link a delay locked loop (DLL) to a PVT condition. The present invention performs a shifting operation according to the output of the phase comparator for comparing the phase of the rising / falling clock and the feedback clock to output a register signal for controlling the amount of phase delay. The multi-phase delay line outputs a multi-phase signal by controlling the delay of the rising / falling clock according to the register signal, and generates a plurality of multi-clocks having a phase different from that of the multi-phase signal according to the state of the delay control signal. The phase controller outputs a plurality of phase control signals for controlling the shifting operation by comparing the phases of the plurality of multi-clocks and the multi-phase signal, and the multi-phase delay control unit performs the shifting operation according to the states of the plurality of phase control signals. To output the delay control signal.

Multi, phase, delay, fixed, loop, line, clock

Description

Delay Locked Loop Circuit

1 is a block diagram of a conventional delay locked loop circuit.

FIG. 2 is a detailed circuit diagram of the delay line of FIG. 1. FIG.

3 is a block diagram of a delay locked loop circuit according to the present invention;

4 is a detailed circuit diagram of the clock buffer of FIG. 3.

FIG. 5 is a detailed circuit diagram of the phase comparator of FIG. 3. FIG.

FIG. 6 is a detailed circuit diagram of the delay controller of FIG. 3. FIG.

FIG. 7 is a detailed circuit diagram illustrating the multi phase delay line of FIG. 3. FIG.

FIG. 8 is a detailed circuit diagram of the multi-phase delay controller of FIG. 3. FIG.

FIG. 9 is a detailed circuit diagram of the phase controller of FIG. 3. FIG.

FIG. 10 is a detailed circuit diagram of the delay cell of FIG. 9. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay locked loop circuit, and more particularly, to output a clock having multiple phases from a double data rate (DDR) synchronous dynamic random access memory (SDRAM) so that a DLL (Delay Locked Loop) can be linked to PVT conditions. It is a technique to do.

In general, a delay locked loop (DLL) is a circuit for controlling the timing of data output from the inside of the DRAM by using an external clock signal input from the outside of the DRAM. In order to transfer data to the chipset without error, the DRAM and chipset must be synchronized to the clock signal.

That is, when a clock signal input from the outside is input into the DRAM, the phase is delayed by logic circuits such as an input clock buffer, a line loading, and a data output buffer. Since the phase of the external clock signal and that of the internal clock signal are different, a DLL is used to compensate for this.

As such, the DLL compensates for the phase skew delayed by the DRAM internal circuit, that is, the core of the DRAM core (Core) based on the external clock signal so that the phase of the data output from the inside to the outside does not differ from the phase of the clock signal. The time point at which the sensed data is output through the data output buffer is equal to the timing of the clock signal input from the outside.

These DLLs are largely divided into analog DLLs and digital DLLs, and digital DLLs come in various forms such as register control DLLs, hybrid DLLs, synchronous mirror DLLs, and measurement control DLLs.

1 is a block diagram of a conventional register control delay locked loop circuit.

Conventional delay locked loop circuits include a clock buffer (10, 11, 20), a phase comparator (30), a delay line (40), a dummy delay line (50), A delay controller 60, a replica model circuit 70, a clock signal line 80, and an output buffer 90 are provided.

Here, the clock buffers 10, 11, and 20 buffer the clocks clk, clkb input from the outside with the internal rising / falling clocks rclk and fclk. In the case of a DLL used for DDR SDRAM, clock buffers 10, 11, and 20 are rising edge clock buffers 10 that generate a rising clock rclk that occurs in synchronization with the rising edge of clock clk inputted from the outside. And a falling edge clock buffer 11 for generating a falling clock fclk generated in synchronization with the falling edge of the clock signal input from the outside using the inverted clock clkb input from the outside.

The phase comparator 30 detects a phase difference between the two clocks by comparing the rising clock rclk and the phase of the feedback clock fbclk fed back from the replica model unit 70. The phase comparator 30 compares the input clock of which frequency is lowered with the output clock while passing through a clock divider (not shown). The phase comparator 30 controls the delay control unit 60 based on the comparison result, and the output signal of the phase comparator 30 is three types of ground, lead, and in-phase locking.

The delay line 40 also delays the phase of the internal rising / polling clocks rclk, fclk. The dummy delay line 50 delays the output clock of the clock buffer 20 to generate the feedback clock fbclk, and outputs the delayed output clock to the replica model unit 70. Here, the configuration of the dummy delay line 50 is the same as the delay line 40, except that a divided clock is input to consume less power. The delay controller 60 is configured of a shift register, and controls the delay rate of the delay line 40 by using the signal output from the phase comparator 30.

Also, the replica model unit 70 according to the output of the dummy delay line 50 until the clock signal input from the outside until the delay line 40 and the signal output from the delay line 40 is output to the outside of the chip. Modeling delay elements of the outputs a feedback clock fbclk. Accordingly, the correct delay factors determine the skew value of the performance of the DLL. The replica modeling is performed using a method of shrinking, simplifying, or using a basic circuit of a dummy clock buffer, a divider, and an output buffer.

The clock signal line 80 functions as a clock driver device that generates a data output device driving signal using the output signal POUT of the delay line 40. The output buffer 90 outputs data received from the core through the data bus to the output terminal in synchronization with the clock of the clock signal line 80.

2 is a detailed circuit diagram of the delay line 40 described above.

The delay line 40 includes a plurality of unit delay cells UDC1 to UDC5 connected in series and a plurality of NAND gates ND11 to ND15. Here, the signals for controlling the plurality of unit delay cells UDC1 to UDC5 correspond one-to-one with the register signals Reg_n to Reg_0 output from the shift register of the delay control unit 60. Each unit delay cell UDC1 to UDC5 includes a plurality of NAND gates ND1 to ND10.

Each of the plurality of NAND gates ND11 to ND15 performs a NAND operation on the rising signals rclk (or polling clock fclk) and the register signals Reg_n to Reg_0 which are outputs of the delay control unit 60, respectively. Accordingly, the reference clock signal is applied to the unit delay cell UDC at which the register signals Reg_n to Reg_0 are at the high level, thereby forming a delay path.

The unit delay cell UDC1 includes the NAND gates ND1 and ND2. Here, the NAND gate ND1 performs a NAND operation on the power supply voltage VDD and the NAND gate ND11. The NAND gate ND2 performs a NAND operation on the power supply voltage VDD and the output of the NAND gate ND1 to output the unit delay cell UDC2. Since the configurations of the remaining unit delay cells UDC2 to UDC5 are the same as those of the unit delay cells UDC1, a detailed description of the detailed configuration will be omitted.

The delay line 40 includes two delay lines for the rising clock rclk and two delay lines for the falling clock fclk. Accordingly, the rising edge and the falling edge of the clock are processed in the same manner, so that the duty ratio distortion can be suppressed as much as possible.

However, this conventional delay locked loop circuit generates an output clock having one phase. Based on the output clock, the output of the DRAM and a control block for controlling the output are operated. Accordingly, when the control block operates according to one output clock during high frequency operation, various operational problems may be caused.

The present invention was created to solve the above problems, in particular, by changing the delay line to generate a clock having a phase faster than the output clock of the DLL to allow the DLL (Delay Locked Loop) to be linked to PVT conditions The purpose is.

In accordance with another aspect of the present invention, a delay locked loop circuit includes: a phase comparator configured to compare and output a phase of a buffered rising / falling clock and a feedback internal clock; A delay controller configured to output a register signal for controlling a phase delay amount by performing a shifting operation according to a comparison result of the phase comparator; A multi-phase delay line for controlling a delay of a rising / falling clock according to a register signal to output a multi-phase signal, and generating a plurality of multi-clocks having a phase different from that of the multi-phase signal according to a state of the delay control signal; A phase controller configured to output a plurality of phase control signals for controlling a shifting operation by comparing phases of a plurality of multi-clocks and the multi-phase signal; And a multi phase delay control unit configured to output a delay control signal by performing a shifting operation according to the states of the plurality of phase control signals.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a block diagram of a delay locked loop circuit of the present invention.

The present invention includes a clock buffer (100, 101, 110), a phase comparator (120), a multi phase delay controller (130), a multi phase delay line (140), and a dummy. Dummy Delay Line 150, Delay Controller 160, Replica Model Circuit 170, Phase Estimator 180, Clock Signal Line 190, And an output buffer 200.

Here, the clock buffers 100, 101, and 110 buffer the clocks clk and clkb inputted from the outside with the internal rising / falling clocks rclk and fclk. In the case of the DLL used for the DDR SDRAM, the clock buffers 100, 101, and 110 may include a rising edge clock buffer 100 that generates a rising clock rclk that occurs in synchronization with the rising edge of the clock clk input from the outside, and from the outside. And a falling edge clock buffer 101 for generating a falling clock fclk generated in synchronization with a falling edge of a clock signal input from the outside using the input inverted clock clkb.

The phase comparator 120 compares the phases of the rising clock rclk and the feedback clock fbclk fed back from the replica model unit 170 and detects a phase difference between the two clocks. The phase comparator 120 compares the input clock of which frequency is lowered with the output clock while passing through a clock divider (not shown). The phase comparator 120 controls the delay control unit 160 based on the comparison result. The output signal of the phase comparator 120 is three types: lead, lag, and locking. .

In addition, the multi-phase delay control unit 130 is composed of a bidirectional shift register and outputs a delay control signal OC <1: n> for delaying the multi-phase according to the phase control signals sre, sro, slo, and sle. . Here, the phase control signals sre, sro, slo, and sle represent even shift write signals, odd shift write signals, even shift left signals, and odd shift left signals, respectively.

The multi phase delay line 140 outputs the multi phase signal MPOUT and the multi clock MPCLK by delaying the phases of the internal rising / falling clocks rclk and fclk according to the delay control signals OC <1: n> and the register signals Reg_n to Reg_0. The dummy delay line 150 delays the output clock of the clock buffer 110 to output the replica model unit 170 to generate the feedback clock fbclk.

The delay controller 160 is configured of a shift register, and controls the delay rate of the multi phase delay line 140 by using a signal output from the phase comparator 120. Here, the shift register is configured to be able to set an initial maximum / minimum delay time. The replica model unit 170 may output a clock signal input from the outside to the multi phase delay line 140 and a signal output from the multi phase delay line 140 according to the output of the dummy delay line 150 to the outside of the chip. The delay elements until are modeled to output the feedback clock fbclk. Accordingly, the correct delay factors determine the skew value of the performance of the DLL. The replica modeling is performed using a method of shrinking, simplifying, or using a basic circuit of a dummy clock buffer, a divider, and an output buffer.

In addition, the phase controller 180 outputs the phase control signals sre, sro, slo, and sl to the multi phase delay controller 130 to adjust the phase according to the multi phase signal MPOUT applied from the multi phase delay line 140. . That is, the phase controller 180 changes the phase of the multi-clock MPCLK, which is the output of the multi-phase delay line 140, according to the PVT (Process, Voltage, Temperature) condition of the DRAM.

The clock signal line 190 performs a function of a clock driver device that generates a data output device driving signal using the multi-phase signal MPOUT of the multi-phase delay line 140. The output buffer 200 outputs data received from the core through the data bus to the output terminal in synchronization with the clock of the clock signal line 190.

4 is a detailed circuit diagram illustrating the clock buffer 100 of FIG. 3.

The clock buffer 100 includes PMOS transistors P1 and P2, NMOS transistors N1 to N3, and inverter IV1 to configure a differential amplifier.

Here, external clocks clkb and clk are applied to the gate terminals of the NMOS transistors N1 and N2 constituting the input terminal of the differential amplifier, respectively. The NMOS transistor N3 whose gate is controlled by the enable signal EN is connected between the source terminal of the NMOS transistors N1 and N2 and the ground voltage terminal.

The PMOS transistors P1 and P2 having the gate terminals commonly connected between the drain terminals of the NMOS transistors N1 and N2 and the power supply voltage terminal are respectively disposed, and the signal output from the drain terminal of the NMOS transistor N2 is inverted by the inverter IV1. Accordingly, the inverter IV1 outputs a rising clock rclk (or falling clock fclk) generated in synchronization with the rising edge of the external clock clk.

FIG. 5 is a detailed circuit diagram of the phase comparator 120 of FIG. 3.

The phase comparator 120 includes a phase comparator 121 and a shift register controller 125. Here, the phase comparison unit 121 includes a plurality of delay cells DC1 to DC3, a plurality of NAND gates ND16 to ND44, a plurality of inverters IV2 to IV7, an oragate OR1, a noagate NOR1, and an AND gate AND1. . The shift register control unit 125 includes a plurality of NAND gates ND45 to ND56 and inverters IV8 to IV10.

The phase comparison unit 121 having such a configuration compares the rising clock rclk, the feedback clock fbclk applied from the replica model unit 170, and the phase of the multi-phase signal MPOUT. The phase comparator 121 outputs three pieces of information to the delay controller 160 based on the comparison result: lead, lag, and locking. That is, it is shift written by the comparison signals PC1, PC3 or shift left by the comparison signals PC2, PC4.

In addition, the phase comparator 121 determines whether to perform a shift operation by using the multi-phase signal MPOUT or perform a shift operation on the rising clock rclk by comparing the rising clock rclk and the feedback clock fbclk. For example, in the case of using a divider having an eight division ratio, eight phase delay cells are used to compare phases between two clocks. When the comparison value satisfies a desired condition, eight shifting operations are performed using a clock before being divided. Will be performed.

Accordingly, the shift register controller 125 sets and outputs different combinations of states of the shift write signals SR1 and SR2 and the shift left signals SL1 and SL2 according to three states that are the results output from the phase comparator 121. At this time, the shift signal is not generated in the locked state.

FIG. 6 is a detailed circuit diagram of the delay controller 160 of FIG. 3.

The delay controller 160 includes a plurality of stages including a plurality of NOR gates NOR2 to NOR7, a plurality of NAND gates ND57 to ND62, a plurality of NMOS transistors N4 to N27, and a plurality of inverters IV11 to IV16.

Here, a stage will be described as an example. Each stage includes an inverted latch composed of a NAND gate ND57 and an inverter IV11, and a switching unit N4 to N7 for changing the latched value according to the phase control signals sre, sro, slo, and sle. And a logic combining unit (Noar gates NOR2 to NOR7) for outputting the register signals Reg_n to Reg_0 by logically combining the positive output of the latch of the previous stage and the negative output of the latch of the next stage.

The NAND gates ND57 to ND62 of each stage receive a reset signal reset for initialization, and receive a negative output of the corresponding latch as a type force. The NOA gates NOR2 to NOR7 input the positive output of the latch of the previous stage and the negative output of the latch of the next stage.

Accordingly, the delay control unit 160 performs the shifting operation according to the four phase control signals sre, sro, slo, and sle. The initial input conditions hold both ends to have a maximum / minimum delay. In addition, the delay controller 160 prevents the two phase control signals sre, sro, slo, and sle in the high state from overlapping each other in order to perform the shift operation.

FIG. 7 is a detailed circuit diagram of the multi phase delay line 140 of FIG. 3.

The multi phase delay line 140 includes a logic combination unit 141, a plurality of unit delay cells UDC6 to UDC10 connected in series, and an output control unit 142.

Here, the logic combination unit 141 NANDs each of the plurality of NAND gates ND73 to ND77 to each of the rising signals rclk (or polling clock fclk) and the register signals Reg_n to Reg_0 which are outputs of the delay control unit 160. Accordingly, the reference clock signal is applied to the unit delay cell UDC at which the register signals Reg_n to Reg_0 become high levels, thereby forming a delay path.

The signals controlling the plurality of unit delay cells UDC6 to UDC10 correspond one-to-one with register signals Reg_n to Reg_0 output from the shift register of the delay control unit 160. Each unit delay cell UDC6 to UDC10 includes a plurality of NAND gates ND63 to ND72.

In addition, the unit delay cell UDC6 includes NAND gates ND63 and ND64. Here, the NAND gate ND63 NAND-operates the power supply voltage VDD and the NAND gate ND73. The NAND gate ND64 NAND-operates the output of the power supply voltage VDD and the NAND gate ND63, and outputs the result to the unit delay cell UDC7. The unit delay cell UDC10 of the last stage outputs the multi-phase signal MPOUT to the clock signal line 190. Detailed configurations of the remaining unit delay cells UDC7 to UDC10 are the same as those of the unit delay cells UDC6, and thus descriptions of the detailed configurations will be omitted.

In addition, the output control unit 142 includes a plurality of transfer gates T1 to T4 and a plurality of inverters IV17 to IV20. Each transmission gate T1 to T4 is selectively switched according to the state of the delay control signal OC <1: n> to output the outputs of the plurality of unit delay cells UDC6 to UDC9 to the multi-clock MPCLK.

FIG. 8 is a detailed circuit diagram of the multi phase delay controller 130 of FIG. 3.

The multi-phase delay control unit 130 includes a plurality of stages of NOR gates NOR8 to NOR12, a plurality of NAND gates ND78 to ND83, a plurality of NMOS transistors N28 to N51, and a plurality of inverters IV21 to IV26.

Here, a stage will be described as an example. Each stage includes an inverting latch L composed of a NAND gate ND79 and an inverter IV22, and a switching unit for changing the latched value according to the phase control signals sre, sro, slo, and sle. (S) and a logic combining unit C for logically combining the positive output of the latch of the previous stage and the sub-output of the latch of the next stage to output the delay control signal OC <1: n>. The latch L of each stage receives the reset signal reset as one input of the NAND gate ND79 for initialization, and receives the sub output of the latch L as a type force.

The NMOS transistor N32 of the switching unit S is connected to the constant output terminal of the latch L and switched in accordance with the phase control signal sre. The NMOS transistor N33 selectively generates a path between the positive output terminal of the latch L and the ground voltage terminal together with the NMOS transistor N32 according to the negative output of the latch L of the previous stage. The NMOS transistor N34 is connected to the negative output terminal of the latch L and switched in accordance with the phase control signal slo. The NMOS transistor N35 selectively generates a path between the negative output terminal of the latch L and the ground voltage terminal together with the NMOS transistor N34 according to the constant output of the latch L of the next stage.

In the previous stage and the next stage, the phase control signals sro and sle are controlled. The logic combination section C includes the NOA gates NOR8 to NOR12 which input the positive output of the latch of the previous stage and the negative output of the latch of the next stage.

Accordingly, the multi-phase delay control unit 130 performs the shifting operation according to the four phase control signals sre, sro, slo, and sle. The initial input condition is held at both ends to have a maximum / minimum delay. In addition, the multi-phase delay control unit 130 does not overlap two signals of the high state of the phase control signals sre, sro, slo, and sl in order to perform the shift operation.

FIG. 9 is a detailed circuit diagram of the phase controller 180 of FIG. 3.

The phase controller 180 includes a phase comparator 181, a flip-flop unit 183, and a logic combiner 184.

Here, the phase comparison unit 181 includes a delay cell 182, a plurality of NAND gates ND84 to ND90, and inverters IV27 and IV28. The phase comparison unit 181 compares the phases of the multi-clock MPCLK and the multi-phase signal MPOUT and outputs them to the logic combination unit 184.

The flip-flop unit 183 includes a plurality of NAND gates ND91 to ND98 and inverters IV29 to IV31 to form a T-flip flop. The flip-flop unit 183 flips the multi-clock MPCLK and outputs the multi-clock MPCLK to the logic combination unit 184.

In addition, the logic combination section 184 includes a plurality of NAND gates ND99 to ND102. Here, the plurality of NAND gates ND99 to ND102 perform NAND operations on the output of the phase comparator 181 and the output of the flip-flop unit 183, respectively, to output phase control signals sre, sro, slo, and sl.

FIG. 10 is a detailed circuit diagram illustrating the delay cell 182 of FIG. 9. Here, the delay cell 182 is an RC delay cell including inverters IV32, IV33, resistor R, and capacitor C. The delay cell 182 delays and outputs the multi phase signal MPOUT.

Referring to the operation of the present invention having such a configuration as follows.

First, the phase controller 180 compares the phases of the multi-clock MPCLK and the multi-phase signal MPOUT to set and output different state combinations of the phase control signals sre, sro, slo, and sle. The phase control unit 180 has a constant delay amount, and the delay amount of the phase control unit 180 may be set by the mode register set or by a fuse.

Here, the phase control signals sre and sro are control signals for right shifting and are alternately outputted in a pulse form. The phase control signals sll and sle are control signals for left shifting, and are alternately outputted in a pulse form.

Accordingly, the phase controller 180 feeds back the multi-phase delay control unit 130 by adjusting the delay amounts of the multi-clock MPCLK and the multi-phase signal MPOUT, and determines the phase difference between the multi-clock MPCLK and the multi-phase signal MPOUT. .

Thereafter, the multi phase delay control unit 130 controls the shifting operation according to the phase control signals sre, sro, slo, and sle, and outputs a delay control signal OC <1: n> to the multi phase delay line 140.

Subsequently, one of the transmission gates T1 to T4 is turned on in the multi phase delay line 140 according to the state of the delay control signal OC <1: n>. Accordingly, the multi-clock MPCLK having a phase which is faster than the multi-phase signal MPOUT output through the unit delay cell UDC10 is output. At this time, when the reset signal reset is input during the initial operation, the delay control signal OC <1> becomes high, and the multi-clock MPCLK phase becomes multi-phase signal MPOUT faster according to the phase control signals sle and slo.

Meanwhile, in the exemplary embodiment of the present invention, a method of changing the phase of the multi-clock MPCLK by changing the multi-phase delay line 140 according to the PVT condition is used. After removing the feedback loop in another embodiment, the multi-phase delay line is removed. One of the delay control signal OC <1: n> which is the control signal of 140 may be selected and output. One of the delay control signals OC <1: n> may be selected through a mode register set or a fuse. In addition, after the feedback loop is formed, a method of changing the delay amount of the delay cell through a mode register set or a fuse may be used.

In addition, in the present invention, only one phase information is additionally output, but one or more outputs may be generated using a plurality of outputs of the transmission gates T1 to T5 of the multi-phase delay line 140.

As described above, the present invention provides an effect of improving the DLL control margin by interlocking a delay locked loop (DLL) to PVT conditions by outputting a clock having a multi-phase.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (20)

A phase comparator comparing and outputting the phase of the buffered rising / falling clock and the feedback internal clock; A delay controller configured to output a register signal for controlling a phase delay amount by performing a shifting operation according to a comparison result of the phase comparator; A multi-phase signal for controlling a delay of the rising / falling clock according to the register signal to output a multi-phase signal, and generating a plurality of multi-clocks having a phase different from that of the multi-phase signal according to the state of the delay control signal. Delay line; A phase controller for comparing a phase of the plurality of multi-clocks and the multi-phase signal to output a plurality of phase control signals for controlling a shifting operation; And And a multi phase delay control unit configured to output the delay control signal by performing a shifting operation according to the states of the plurality of phase control signals. The method of claim 1, A clock buffer configured to generate an external clock by buffering an external clock; A dummy delay line delaying an output clock of the clock buffer and outputting the delayed output clock; A replica model unit for modeling delay elements according to an output of the dummy delay line to generate the feedback internal clock; And And an output buffer for outputting data applied through a data bus in synchronization with a clock of the multi-phase signal. The method of claim 1, wherein the multi-phase delay line A first logical combination unit configured to logically output the rising / falling clock and the register signal; A plurality of unit delay cells connected in series to adjust the delay amount of the multi-phase signal by adjusting the number of selections according to the output of the first logical combination unit; And And an output control unit which is selectively turned on according to an activation state of the delay control signal and outputs signals of each connection node of the plurality of unit delay cells to the plurality of multiclocks, respectively. 4. The PLL circuit of claim 3, wherein the logic combiner comprises a plurality of NAND gates for NAND-operating the rising / falling clock and the register signal. The method of claim 3, wherein the plurality of unit delay cells And a reference clock signal is applied to a unit delay cell according to the output of the first logic combination unit when the register signal is at a high level, thereby forming a delay path. The method of claim 3, wherein the output control unit And a plurality of transmission gates connected between each connection node of the plurality of unit delay cells and output terminals of the plurality of multi-clocks, respectively, and selectively turned on according to an activation state of the delay control signal. Circuit. 7. The PLL circuit of claim 6, wherein only one of the plurality of transmission gates is turned off and the other of the transmission gates is turned on. 8. A phase locked loop circuit as claimed in claim 6 or 7, wherein a turn-on number of said plurality of transfer gates is controlled by a mode register set. 8. The phase-lock loop of claim 6 or 7, wherein the number of turn-on numbers of the plurality of transfer gates is controlled according to a cutting state of the fuse. The method of claim 3, wherein the output control unit A phase comprising a plurality of transmission gates connected between one unit delay cell of the plurality of unit delay cells and output terminals of the plurality of multi-clocks and selectively turned on according to an activation state of the delay control signal; Synchronous loop circuit. 2. The phase locked loop circuit of claim 1, wherein the multi-phase delay control unit includes a bidirectional shift register. The method of claim 1 or 11, wherein the multi-phase delay control unit A switching unit configured to selectively switch according to states of the plurality of phase control signals to control shift left and shift write operations; A latch unit for latching an output of the switching unit; And And a second logical combination section for performing a logic operation on the output of the latch section to output the delay control signal. The method of claim 1, wherein the phase control unit A phase comparison unit comparing phases of the plurality of multi-clocks and the multi-phase signal; A first flip-flop unit which flips and outputs the multi-clock; And And a third logical combination unit configured to logically perform an output of the phase comparator and an output of the first flip-flop unit to output the plurality of phase control signals. The method of claim 13, wherein the phase comparison unit A delay cell for delaying the multi-phase signal for a predetermined time; A second flip-flop unit configured to flip-flop the outputs of the plurality of multi-clocks and the delay cell; And And an inverter unit for delaying the output of the second flip-flop unit. 15. The PLL circuit of claim 14, wherein the delay time of the delay cell is controlled by a mode register set. 15. The PLL circuit of claim 14, wherein the delay time of the delay cell is controlled by cutting a fuse. 15. The PLL circuit of claim 14, wherein the delay cell comprises an RC delay cell. 15. The PLL circuit of claim 13, wherein the first flip-flop portion includes a T-flip flop. The method of claim 13, wherein the third logical combination portion And a plurality of NAND gates configured to NAND-operate the output of the phase comparator and the output of the first flip-flop unit to output the plurality of phase control signals, respectively. The phase locked loop circuit according to claim 1 or 13, wherein the plurality of phase control signals include an even shift write signal, an odd shift write signal, an even shift left signal, and an odd shift left signal.

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