KR20070035673A - Display device - Google Patents

Abstract

The present invention relates to a display device, and more particularly, to a display device capable of reducing EMI.

A display device including a plurality of pixels arranged in a matrix form includes a data line connected to the pixel, a signal controller for processing image data from outside, and generating a plurality of control signals and clock signals, and a plurality of gray voltages. A gray voltage generator to generate a gray voltage corresponding to the image data from the signal controller, and to apply the gray voltage to the data line as a data voltage, wherein the plurality of clock signals are in phase with each other. This is off.

As such, by providing the phase difference between the front clock signal and the rear clock signal, the harmonic component is reduced as compared with the prior art without the phase difference, thereby reducing EMI in the voltage driving method.

Display, EMI, Point-to-Point, Voltage Drive, Signal Control, Data Drive

Description

Display device {DISPLAY DEVICE}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a timing diagram illustrating a general operation of a liquid crystal display according to an exemplary embodiment of the present invention.

5A and 5B are diagrams illustrating a clock signal of a liquid crystal display according to an exemplary embodiment and a clock signal according to the related art, respectively.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

191: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: data driver 511-516: data driver integrated circuit

600: signal controller 800: gray voltage generator

DIO: Digital I / O Signals R, G, B: Input Video Data

MCLK: Main Clock Hsync: Horizontal Sync Signal

FCLK: Forward Clock Signal BCLK: Backward Clock Signal

Vsync: Vertical Sync Signal CONT1: Gate Control Signal

CONT2: data control signal DAT: digital video signal

Clc: Liquid Crystal Capacitor Cst: Keeping Capacitor

Q: switching device

The present invention relates to a display device.

Recently, organic electroluminescence display (OLED), plasma display panel (PDP), liquid crystal display (LCD), instead of heavy and large cathode ray tube (CRT) Flat panel display devices such as are being actively developed.

The PDP is a device for displaying characters or images using plasma generated by gas discharge, and the organic light emitting diode display displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display applies an electric field to the liquid crystal layer interposed between the two display panels, and adjusts the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such flat panel displays, for example, a liquid crystal display and an organic light emitting display may turn on / off a switching element of a pixel by emitting a gate signal to a pixel including a switching element, a display panel having a display signal line, and a gate line among the display signal lines. A gate driver to turn off, a gray voltage generator to generate a plurality of gray voltages, a data driver to select a voltage corresponding to image data among the gray voltages and apply a data voltage to the data lines of the display signal lines, and to control them. It includes a signal controller.

Recently, voltage driving and current driving are used as a method of transferring data from a signal controller to a data driver.

The voltage driving method transfers data by determining a logic value with a voltage having a width of about 2.5V, for example. In the current driving method, a current corresponding to 3I flows in order to transfer data corresponding to a low value, and a current corresponding to I 1/3 of a low value flows in order to deliver data corresponding to a high value. The desired information is displayed on the screen by passing the logic values corresponding to "1" and "1".

In addition, a point-to-point cascading interface, also known as a wise bus, has been introduced to help reduce power consumption.

In this case, the voltage driving method has a high level of electromagnetic interference (EMI) because the voltage driving method transmits a TTL (transistor transistor logic) signal at a high speed.

Accordingly, an aspect of the present invention is to provide a display device capable of reducing an EMI level in a voltage driving method.

According to an exemplary embodiment of the present invention, a display device including a plurality of pixels arranged in a matrix form may process data lines connected to the pixels and image data from outside, and a plurality of controls. A signal controller for generating a signal and a clock signal, a gray voltage generator for generating a plurality of gray voltages, and a gray voltage corresponding to the image data from the signal controller among the gray voltages, and applying the data voltage to the data line as a data voltage; And a data driver, wherein the plurality of clock signals are out of phase with each other.

In this case, the plurality of clock signals may have a phase difference of 90 ° to 270 °, and further, the plurality of clock signals may have a phase difference of 180 °.

The data driver may include a plurality of data driver integrated circuits, and the signal controller and the data driver integrated circuit may be connected in a point-to-point manner.

In this case, the data driving integrated circuit may be positioned in a symmetrical structure at left and right with respect to the signal controller.

The plurality of clock signals may include a first signal input to a first data driving integrated circuit group located at the left side of the signal controller and a second data driving integrated circuit group located at a right side of the signal controller. It can include two signals.

In this case, the first and second signals may be input to the first and second data driving integrated circuit groups connected in series with each other.

The first signal and the second signal may have a phase difference of 90 ° to 270 °, or the first signal and the second signal may have a phase difference of 180 °.

The first data driving integrated circuit group and the second data driving integrated circuit group may apply the data voltage to the data line at the same time.

The signal controller and the data driver may communicate using a voltage driving method.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, the display device according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5B, and the liquid crystal display device will be described as an example.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. It is a schematic diagram of a liquid crystal display device which concerns on an example. 4 is a schematic layout view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 5A and 5B illustrate a clock signal and a conventional clock signal of the liquid crystal display according to an exemplary embodiment of the present invention, respectively. Drawing.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, the pixel PX connected to the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line Dj. ) Includes a switching element Q connected to the signal line G _i D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring again to FIGS. 1 and 3, the gray voltage generator 800 is mounted on a printed circuit board 550 and includes two sets of gray voltages related to transmittance of the pixel PX (or Reference gray voltage set) is generated. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300. The data driver 500 receives the gray voltage from the gray voltage generator 800 through the wiring 810 and receives the gray voltage. Is applied to the data lines D ₁ -D _m as data signals. However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

In addition, the data driver 500 includes a plurality of data driver integrated circuits 511-516, and each data driver integrated circuit 511-516 is mounted on a flexible printed circuit film 540. And is connected to the signal controller 600 in a point-to-point manner to receive the corresponding image data DAT1-DAT6. In the data driving integrated circuits 511-516, three integrated circuits 511-513 are disposed on the left side with respect to the signal controller 600, and three integrated circuits 514-516 are disposed on the right side. It has a symmetrical structure. Each of the data driving integrated circuits 511-516 receives the image data DAT1-DAT6 from the signal controller 600 through the signal lines 561-566, and all of the data driving integrated circuits 511-513 located on the left side. The output signals FCLK and DIO are applied through the signal lines 531-533, and all the data driver integrated circuits 514-516 located on the right side receive the output signals BCLK and DIO through the signal lines 534-536. Licensed.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a digital input / output signal DIO.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver ( 500).

In this case, the processed image signal DAT is divided into the image signals DAT1-DAT6 as shown in FIG. 3, and the data driver integrated circuits 511-513 and the data on the right side of the left side of the signal controller 600 are referred to. Input to the drive integrated circuits 514-516, respectively. In this case, each of the image signals DAT1-DAT6 is transmitted to each of the data driving integrated circuits 511-516 in the point-to-point manner described above, and thus requires a carry signal for shifting the data DAT1-DAT6. I never do that. In other words, instead of filling data in the data driving integrated circuit 513 first and then applying data to the next data driving integrated circuit 512, the data DAT1 input to each of the data driving integrated circuits 511-516 from the beginning. Create and export DAT6).

In addition, the signal controller 600 may have a clock signal FCLK (hereinafter, referred to as a shear clock signal) input to the data driving integrated circuits 511-513 located on the left side with respect to the signal controller 600. The phases of the clock signal BCLK (hereinafter, referred to as a "after clock signal") input to the data driving integrated circuits 514-516 located at s are different from each other, and thus, for example, a difference of 90 ° to 270 ° may be provided. Further, as shown in Fig. 5A, the phase difference can be exported at 180 degrees. When the phases of the front clock signal FCLK and the rear clock signal BCLK are different from each other, the harmonic components present in the front clock signal FCLK and the rear clock signal BCLK are reduced, and the prior art shown in FIG. EMI can be reduced compared to the clock signal. In particular, as shown, when the phase difference of 180 ° is provided, the rising edge and the falling edge of the two clock signals FCLK and BCLK coincide with each other to further increase the canceling effect of the signal and minimize EMI.

4 illustrates a clock signal CLK, a digital input / output signal DIO, and transmission lines D10-Dx2. Here, 'x' represents the number of the data driver integrated circuits 511-516 described above, and 'x = 6' in the structure shown in FIG. 3. The clock signal CLK is the front clock signal FCLK or the rear clock signal BCLK.

The transmission lines D10-Dx2 transmit a red, green, and blue digital image data DAT in a bundle of three. For example, the first transmission line D10 of the transmission lines D10-D12 is red image data. The second transmission line D11 may transmit green image data, and the third transmission line D12 may transmit blue image data.

The remaining time excluding the time at which the image data DAT is transmitted is called a blank interval tb, and various control signals for processing the image data DAT may be inserted in the blank interval tb. .

For example, a charge sharing control signal CSP for controlling a charge sharing time may be inserted into the blank period tb. The charge sharing is a connection between two adjacent data lines and a switching element is turned on as it is known to share the charge between two adjacent data lines. The charge sharing control signal CSP is controlled by controlling the turn-on time of the switching element. Control the time. In addition, a polarity signal POL for determining the polarity of the pixel voltage with respect to the common voltage may be inserted.

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signals FCLK and BCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage &quot;) RVS) may be further included. At this time, the digital input / output signal DIO includes a horizontal synchronization start signal STH and a load signal LOAD, so that the signal controller 600 may provide a separate horizontal synchronization start signal STH and a load signal LOAD. Do not export.

According to the data control signal CONT2 from the signal controller 600, the data driver integrated circuits 511-516 respectively receive the digital image signals DAT1-DAT6 for one row of pixels PX, and each digital signal. By selecting the gray scale voltage corresponding to the image signals DAT1-DAT6, the digital image signals DAT1-DAT6 are converted into analog data signals, and then applied to the corresponding data lines D ₁ -D _m . In addition, the data driving integrated circuits 511-513 receiving the front clock signal FCLK wait for a phase difference from the rear clock signal BCLK and output analog data signals so that all the data driving integrated circuits 511-516 simultaneously analog. Output the data signal.

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the turned-on switching element Q.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync), so that the gate-on voltages (for all gate lines G ₁ -G _n ) are sequentially converted. Von is applied to apply a data signal to all the pixels PX to display an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

As such, when the phases of the front clock signal FCLK and the rear clock signal BCLK are shifted, EMI can be reduced in the voltage driving method.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (11)

A display device including a plurality of pixels arranged in a matrix form, A data line connected to the pixel, A signal controller which processes image data from outside and generates a plurality of control signals and clock signals; A gray voltage generator for generating a plurality of gray voltages, and A data driver which selects a gray voltage corresponding to the image data from the signal controller and applies it to the data line as a data voltage among the gray voltages; Including, The plurality of clock signals are out of phase with each other. Display device. In claim 1, The plurality of clock signals have a phase difference of 90 ° to 270 °. In claim 2, And a plurality of clock signals have a phase difference of 180 degrees. In claim 1, The data driver includes a plurality of data driver integrated circuits, The signal controller and the data driver integrated circuit are connected in a point to point manner. Display device. In claim 4, The data driving integrated circuit is positioned symmetrically to the left and right of the signal controller. In claim 5, The plurality of clock signals may include a first signal input to a first data driving integrated circuit group located at a left side of the signal controller and a second signal input to a second data driving integrated circuit group located at a right side of the signal controller. Display device including. In claim 6, And the first and second signals are input to the first and second data driving integrated circuit groups connected in series with each other. In claim 7, The first signal and the second signal has a phase difference of 90 ° to 270 °. In claim 8, And the first signal and the second signal have a phase difference of 180 degrees. In claim 9, And the first data driving integrated circuit group and the second data driving integrated circuit group apply the data voltage to the data line at the same time. In claim 1, And the signal controller and the data driver communicate using a voltage driving method.

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