KR20070032468A - Semiconductor package by pad redistribution and manufacture method thereof - Google Patents

Semiconductor package by pad redistribution and manufacture method thereof Download PDF

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Publication number
KR20070032468A
KR20070032468A KR1020050086734A KR20050086734A KR20070032468A KR 20070032468 A KR20070032468 A KR 20070032468A KR 1020050086734 A KR1020050086734 A KR 1020050086734A KR 20050086734 A KR20050086734 A KR 20050086734A KR 20070032468 A KR20070032468 A KR 20070032468A
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South Korea
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bonding pad
chip
semiconductor package
substrate
fuse
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KR1020050086734A
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Korean (ko)
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김지묵
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주식회사 하이닉스반도체
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Priority to KR1020050086734A priority Critical patent/KR20070032468A/en
Publication of KR20070032468A publication Critical patent/KR20070032468A/en

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor package by pad redistribution and a manufacturing method thereof are provided to simplify a structure of the semiconductor package by employing a second bonding pad made of paste and connected to a first bonding pad on a chip. A chip(120) is mounted on a substrate(110). The chip has a fuse(121) and a first bonding pad(122). A dielectric(123) is prepared on the chip to expose parts of the fuse and the first bonding pad. A second bonding pad(124) is prepared on the dielectric. The second bonding pad is connected to the first bonding pad. The second bonding pad is connected to the exposed parts of the fuse and the first bonding pad. A wire(130) electrically connects the second bonding pad to the substrate. The second bonding pad is a conductive paste.

Description

패드 재배열에 의한 반도체 패키지 및 그 제조방법{Semiconductor package by pad redistribution and manufacture method thereof}Semiconductor package by pad redistribution and method for manufacturing same

도 1a는 종래의 반도체 패키지를 개략적으로 나타낸 단면도,1A is a cross-sectional view schematically showing a conventional semiconductor package;

도 1b는 도 1a의 반도체 패키지를 패드 재배열에 의하여 구조를 변화시킨 단면도,FIG. 1B is a cross-sectional view of the structure of the semiconductor package of FIG.

도 2는 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도,2 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention;

도 3은 도 2의 반도체 패키지 중 제2 본딩 패드를 나타낸 평면도,3 is a plan view illustrating a second bonding pad in the semiconductor package of FIG. 2;

도 4는 본 발명의 또 다른 실시예에 따른 반도체 패키지를 나타낸 단면도,4 is a cross-sectional view showing a semiconductor package according to another embodiment of the present invention;

도 5는 도 2의 반도체 패키지 제조 방법을 순차적으로 나타낸 순서도.5 is a flowchart sequentially illustrating a method of manufacturing a semiconductor package of FIG. 2.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100... 반도체 패키지 110... 기판100 ... Semiconductor Package 110 ... Substrate

120... 칩 122... 제1 본딩 패드120 ... chip 122 ... first bonding pad

123... 절연층 124,125... 제2 본딩 패드123 ... Insulation layer 124,125 ... Second bonding pad

130... 와이어 130 ... wire

본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로서, 특히 패드의 재배열을 통하여 제조 공정을 단순화한 반도체 패키징 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor packaging and a method for manufacturing the same, which are simplified by a rearrangement of pads.

일반적으로 반도체 패키지는 웨이퍼 공정에 의해 만들어진 개개의 칩을 실제 전자 제품으로써 사용할 수 있도록 전기적 연결을 해주고, 외부의 충격에 보호되도록 밀봉 포장된 것을 말한다.In general, a semiconductor package is a package that is electrically sealed so that individual chips made by a wafer process can be used as actual electronic products and are protected from external impact.

최근 전자 제품이 점차 소형화 되면서, 반도체가 실장될 공간은 점차 줄어 드는 반면, 전자 제품은 더욱 다기능화되고, 고성능화되기 때문에 이를 뒷받침해 줄 반도체의 종류 및 개수는 늘어가는 추세이며, 따라서 단위 체적당 실장 효율을 높이기 위해서 패키지는 경박단소화되고 있다.In recent years, as electronic products become smaller in size, the space in which semiconductors are to be mounted is gradually reduced, while electronic products are becoming more versatile and higher in performance, and thus the type and number of semiconductors to support them are increasing. In order to increase efficiency, the package is light and small.

이러한 반도체 패키지는 고객의 요구에 따라 도 1a와 같은 형태에서 패드의 재배열을 통하여 도 1b와 같이 그 구조를 변형할 수 있다.The semiconductor package may be modified as shown in FIG. 1B through rearrangement of pads in the form as shown in FIG. 1A according to a customer's request.

패드의 재배열에 의하여 변형된 반도체 패키지의 구조에 대하여 도 1b를 참조하여 간략히 설명하면 다음과 같다.The structure of a semiconductor package deformed by rearrangement of pads will be briefly described with reference to FIG. 1B.

즉, 반도체 패키지(20)는 기판(21) 상에 칩(22)이 실장되고, 이 칩(22)과 기판(21) 사이를 와이어(31)에 의하여 전기적으로 연결한 후, 칩(22) 및 와이어(31)를 보호하기 위하여 EMC(epoxy moding compound;32)에 의하여 밀봉한다.That is, in the semiconductor package 20, the chip 22 is mounted on the substrate 21, and the chip 22 is electrically connected between the chip 22 and the substrate 21 by the wire 31. And an epoxy modulating compound (EMC) 32 to protect the wire 31.

칩(22) 상에는 퓨즈(23)와 본딩 패드(24)가 마련되고, 이 퓨즈(23) 및 본딩 패드(24)의 일부분이 노출되도록 절연층(25)이 적층된다. A fuse 23 and a bonding pad 24 are provided on the chip 22, and an insulating layer 25 is stacked to expose a portion of the fuse 23 and the bonding pad 24.

그리고 절연층(25) 상에는 유전층(26)이 적층되어 퓨즈(23)의 노출된 부분을 덮고, 유전층(25) 및 본딩 패드(24) 상에는 시드 메탈(seed metal;27)과 전해 도금층(28) 및 무전해 도금층(29)이 순차적으로 적층되며, 무전해 도금층(29)의 일측에 와이어(31)가 접합되어 기판(21)과 칩(22) 사이의 전기적 연결을 가능하게 한다.The dielectric layer 26 is stacked on the insulating layer 25 to cover the exposed portion of the fuse 23, and the seed metal 27 and the electroplating layer 28 are disposed on the dielectric layer 25 and the bonding pad 24. And the electroless plating layer 29 are sequentially stacked, and a wire 31 is bonded to one side of the electroless plating layer 29 to enable electrical connection between the substrate 21 and the chip 22.

그런데, 이와 같은 구조의 반도체 패키지는 그 제조 공정이 복잡하고, 그 제조 비용도 상당하여 비경제적인 문제점이 있다.By the way, the semiconductor package of such a structure has the complicated manufacturing process, the manufacturing cost is considerable, and there is a problem that it is uneconomical.

미설명 부호 10은 반도체 패키지, 11은 기판, 12는 칩, 13은 와이어, 14와 32는 EMC, 15와 33은 솔더 볼이다.Reference numeral 10 is a semiconductor package, 11 is a substrate, 12 is a chip, 13 is a wire, 14 and 32 are EMC, and 15 and 33 are solder balls.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 제조 공정 및 구성요소를 단순화하여 경제적인 반도체 패키지 및 그 제조방법을 제공하는 것을 그 목적으로 한다.The present invention has been made to solve the above problems, and aims to provide an economical semiconductor package and its manufacturing method by simplifying the manufacturing process and components.

상기의 목적을 달성하기 위한 본 발명의 반도체 패키지는, 기판; 상기 기판 상에 실장되며, 퓨즈와 제1 본딩패드가 마련된 칩; 상기 퓨즈와 상기 제1 본딩 패드의 일부분이 노출되도록 상기 칩 상에 마련된 절연층; 상기 절연층 상에 마련되며, 상기 퓨즈와 상기 제1 본딩 패드의 노출된 부분과 접합되는 제2 본딩 패드; 및 상기 제2 본딩 패드와 상기 기판을 전기적으로 연결하는 와이어를 포함한다.The semiconductor package of the present invention for achieving the above object, the substrate; A chip mounted on the substrate and provided with a fuse and a first bonding pad; An insulating layer provided on the chip to expose a portion of the fuse and the first bonding pad; A second bonding pad provided on the insulating layer and bonded to an exposed portion of the fuse and the first bonding pad; And a wire electrically connecting the second bonding pad and the substrate.

여기서, 상기 제2 본딩 패드는 전도성을 가진 페이스트인 것이 바람직하다.Here, the second bonding pad is preferably a paste having conductivity.

그리고 본 발명의 또 다른 반도체 패키지는, 기판; 상기 기판 상에 실장되며, 퓨즈와 제1 본딩패드가 마련된 칩; 상기 퓨즈와 상기 제1 본딩 패드의 일부분 이 노출되도록 상기 칩 상에 마련된 절연층; 상기 절연층 상에 마련된 제2 본딩 패드; 및 상기 제2 본딩 패드의 일측과 상기 기판 사이 및 상기 제2 본딩 패드 타측과 상기 제1본딩 패드 사이를 전기적으로 연결하는 와이어를 포함한 것이 바람직하다. And another semiconductor package of the present invention, a substrate; A chip mounted on the substrate and provided with a fuse and a first bonding pad; An insulating layer provided on the chip to expose a portion of the fuse and the first bonding pad; A second bonding pad provided on the insulating layer; And a wire electrically connecting between one side of the second bonding pad and the substrate, and the other side of the second bonding pad and the first bonding pad.

그리고 본 발명의 반도체 패키지 제조방법은, 기판 상에 칩을 실장하는 단계; 상기 칩 상에 소정 패턴이 형성된 스텐실 마스크를 씌우는 단계; 상기 스텐실 마스크 상에 전도성을 가진 페이스트를 도포하는 단계; 상기 도포된 페이스트를 밀어 상기 패턴대로 상기 칩 상에 상기 페이스트를 부착하는 단계; 및 상기 부착된 페이스트와 상기 기판 사이를 와이어로 전기적 연결을 하는 단계를 포함한다.The semiconductor package manufacturing method of the present invention includes the steps of mounting a chip on a substrate; Covering a stencil mask having a predetermined pattern formed on the chip; Applying a conductive paste on the stencil mask; Pushing the applied paste to attach the paste onto the chip according to the pattern; And electrically connecting a wire between the attached paste and the substrate.

여기서, 상기 소정 패턴은 상기 와이어와 연결되는 부분의 면적이 넓은 "T" 자 형상인 것이 바람직하다.Here, the predetermined pattern is preferably a "T" shape of a large area of the portion connected to the wire.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도이다.2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

도면을 참조하면, 반도체 패키지(100)는 기판(110)과, 기판(110) 상에 실장된 칩(120)과, 기판(110)과 칩(120) 사이를 전기적으로 연결하는 와이어(130) 및 칩(120)과 와이어(130)를 외부로부터 보호하기 위하여 밀봉하는 EMC(140)를 포함한다. 미설명 부호 150은 솔더 볼이다.Referring to the drawings, the semiconductor package 100 includes a substrate 110, a chip 120 mounted on the substrate 110, and a wire 130 electrically connecting the substrate 110 and the chip 120. And an EMC 140 that seals the chip 120 and the wire 130 to protect it from the outside. Reference numeral 150 is a solder ball.

칩(120) 상에는 퓨즈(121)와 제1 본딩 패드(122)가 마련되며, 퓨즈(121)와 제1 본딩 패드(122)의 일부분이 노출되도록 절연층(123)이 적층된다.The fuse 121 and the first bonding pad 122 are provided on the chip 120, and the insulating layer 123 is stacked to expose a portion of the fuse 121 and the first bonding pad 122.

그리고 절연층(123) 상에는 전기 전도성 물질의 페이스트(paste)로 이루어진 제2 본딩 패드(124)가 적층되며, 이 제2 본딩 패드(124)는 제1 본딩 패드(122)와 접합된다. 여기서, 페이스트로는 AG나 SN3AG0.5CU APSTE 등의 제품을 사용할 수 있다.The second bonding pad 124 made of a paste of an electrically conductive material is stacked on the insulating layer 123, and the second bonding pad 124 is bonded to the first bonding pad 122. Here, as paste, products, such as AG and SN3AG0.5CU APSTE, can be used.

이 제2 본딩 패드(124)는 도 3과 같이 일측이 넓은 면적을 갖도록 "T"자 형상을 가지며, 넓게 형성된 부분에 와이어(130)의 일측단부가 접합되어, 기판(110)과 칩(120) 사이의 전기적 연결이 이루어지게 한다.The second bonding pad 124 has a “T” shape such that one side has a large area as shown in FIG. 3, and one side end of the wire 130 is bonded to a widely formed portion to form a substrate 110 and a chip 120. ) Make electrical connections between

도 4는 본 발명의 또 다른 실시예를 나타낸 반도체 패키지 중 칩과, 제2 본딩 패드 및 와이어의 연결 상태를 개략적으로 나타낸 단면도이다.4 is a cross-sectional view schematically illustrating a connection state between a chip, a second bonding pad, and a wire in a semiconductor package according to still another embodiment of the present invention.

도면을 참조하면, 또 다른 실시예로서의 반도체 패키지는 제2 본딩 패드(125)의 형태 및 와이어(130a,130b) 접합 구조를 제외하고는 도 2에 도시된 반도체 패키지(100)와 동일하므로 구별되는 부분만 설명하기로 한다.Referring to the drawings, a semiconductor package as another embodiment is the same as the semiconductor package 100 shown in FIG. 2 except for the shape of the second bonding pad 125 and the bonding structure of the wires 130a and 130b. I will explain only.

절연층(123) 상에 적층되는 제2 본딩 패드(125)는 도 2의 반도체 패키지(100)에서와 달리 제1 본딩 패드(122)를 덮지 않는 구조이다. 즉, 제2본딩 패드(125)와 제1 본딩 패드(122)는 서로 전기적으로 연결되지 않는다.Unlike the semiconductor package 100 of FIG. 2, the second bonding pads 125 stacked on the insulating layer 123 do not cover the first bonding pads 122. That is, the second bonding pads 125 and the first bonding pads 122 are not electrically connected to each other.

따라서, 제2 본딩 패드(125)와 제1 본딩 패드(122)를 상호 전기적으로 연결하기 위하여 제2 본딩 패드(125)의 타측과 제1 본딩 패드(122)의 일측을 와이어(130b)로 연결한다.Therefore, in order to electrically connect the second bonding pads 125 and the first bonding pads 122 to each other, the other side of the second bonding pads 125 and one side of the first bonding pads 122 are connected by a wire 130b. do.

그리고 제2 본딩 패드(125)의 일측에는 기판(110)과 칩(120) 사이의 전기적 연결을 위하여 와이어(130a)가 연결된다.In addition, a wire 130a is connected to one side of the second bonding pad 125 for electrical connection between the substrate 110 and the chip 120.

한편, 도 5는 도 2의 반도체 패키지 제조방법을 순차적으로 나타낸 순서도이다.5 is a flowchart sequentially illustrating a method of manufacturing the semiconductor package of FIG. 2.

도면을 참조하면, 먼저 상면에 퓨즈와 제1 본딩 패드가 마련되고, 퓨즈와 제1 본딩 패드의 일부분이 노출되도록 절연층이 적층된 칩을 기판 상에 실장한다(S1). Referring to the drawings, first, a fuse and a first bonding pad are provided on an upper surface, and a chip having an insulating layer laminated thereon is mounted on a substrate so that a portion of the fuse and the first bonding pad are exposed (S1).

그런 다음, 칩 상에 "T"자 형상의 패턴이 형성된 스텐실 마스크를 씌우고(S2), 전기 전도성을 가진 페이스트를 스텐실 마스크 상에 도포한다(S3).Then, a stencil mask having a “T” shape pattern is formed on the chip (S2), and an electrically conductive paste is applied onto the stencil mask (S3).

다음으로, 스텐실 마스크 상에 도포된 페이스트를 롤러 등으로 밀어 스텐실 마스크에 형성된 패턴을 통해 칩 상에 페이스트가 부착되도록 한다(S4).Next, the paste applied on the stencil mask is pushed with a roller or the like so that the paste is attached onto the chip through a pattern formed on the stencil mask (S4).

다음으로, 칩 상에 부착된 페이스트와 기판 사이를 전기적으로 연결하기 위하여, 와이어의 일측은 기판에 접합시키고, 타측은 페이스트의 넓게 형성된 부분에 접합시킨 후(S5), EMC로 칩 및 와이어를 밀봉(미도시)함으로써 본 발명의 일 실시예에 따른 반도체 패키지가 제조된다. Next, in order to electrically connect between the paste attached to the chip and the substrate, one side of the wire is bonded to the substrate, and the other side is bonded to the widely formed portion of the paste (S5), and then the chip and the wire are sealed with EMC. By not shown, a semiconductor package according to an embodiment of the present invention is manufactured.

여기서, 도 3의 반도체 패키지의 제조방법은, 스텐실 마스크에 형성된 패턴의 형상을 바꾸고, 와이어에 의하여 기판과 제2 본딩 패드 사이 뿐만 아니라, 제2 본딩 패드와 제1 본딩 패드를 연결함에 의하여 제조된다.Here, the method of manufacturing the semiconductor package of FIG. 3 is manufactured by changing the shape of the pattern formed on the stencil mask and connecting not only the substrate and the second bonding pad but also the second bonding pad and the first bonding pad by a wire. .

이와 같은 반도체 패키지 및 그 제조방법에 의하면, 반도체 패키지를 구성하는 구성 요소가 종래보다 줄어들어, 그 제조 공정이 단순화되고, 또한 그 제조 비용도 줄어들게 되어 종래보다 경제적인 반도체 패키지를 얻을 수 있게 된다.According to such a semiconductor package and a manufacturing method thereof, the constituent elements constituting the semiconductor package are reduced compared to the prior art, the manufacturing process is simplified, and the manufacturing cost is reduced, so that a semiconductor package more economical than the conventional one can be obtained.

상술한 바와 같이 본 발명의 반도체 패키지 및 그 제조방법에 의하면, 패드 재배열의 방법으로서, 칩 상에 제1 본딩 패드와 연결되고, 페이스트로 이루어진 제2 본딩 패드를 마련하여 반도체 패키지의 구조를 단순화시키고, 또한 그 제조 방법을 단순화시켜 경제적인 반도체 패키지를 제조 및 제공할 수 있게 하는 효과를 제공한다.As described above, according to the semiconductor package of the present invention and a method of manufacturing the same, as a method of rearranging the pad, a second bonding pad, which is connected to the first bonding pad on the chip and made of paste, is provided to simplify the structure of the semiconductor package. In addition, it provides the effect of simplifying the manufacturing method to manufacture and provide an economical semiconductor package.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (5)

기판; Board; 상기 기판 상에 실장되며, 퓨즈와 제1 본딩패드가 마련된 칩; A chip mounted on the substrate and provided with a fuse and a first bonding pad; 상기 퓨즈와 상기 제1 본딩 패드의 일부분이 노출되도록 상기 칩 상에 마련된 절연층;An insulating layer provided on the chip to expose a portion of the fuse and the first bonding pad; 상기 절연층 상에 마련되며, 상기 퓨즈와 상기 제1 본딩 패드의 노출된 부분과 접합되는 제2 본딩 패드; 및A second bonding pad provided on the insulating layer and bonded to an exposed portion of the fuse and the first bonding pad; And 상기 제2 본딩 패드와 상기 기판을 전기적으로 연결하는 와이어를 포함한 것을 특징으로 하는 반도체 패키지.And a wire for electrically connecting the second bonding pad and the substrate. 제1항에 있어서,The method of claim 1, 상기 제2 본딩 패드는 전도성을 가진 페이스트인 것을 특징으로 하는 반도체 패키지.The second bonding pad is a semiconductor package, characterized in that the conductive paste. 기판; Board; 상기 기판 상에 실장되며, 퓨즈와 제1 본딩패드가 마련된 칩; A chip mounted on the substrate and provided with a fuse and a first bonding pad; 상기 퓨즈와 상기 제1 본딩 패드의 일부분이 노출되도록 상기 칩 상에 마련된 절연층;An insulating layer provided on the chip to expose a portion of the fuse and the first bonding pad; 상기 절연층 상에 마련된 제2 본딩 패드; 및A second bonding pad provided on the insulating layer; And 상기 제2 본딩 패드의 일측과 상기 기판 사이 및 상기 제2 본딩 패드 타측과 상기 제1본딩 패드 사이를 전기적으로 연결하는 와이어를 포함한 것을 특징으로 하는 반도체 패키지.And a wire electrically connecting between one side of the second bonding pad and the substrate and the other side of the second bonding pad and the first bonding pad. 기판 상에 칩을 실장하는 단계;Mounting a chip on a substrate; 상기 칩 상에 소정 패턴이 형성된 스텐실 마스크를 씌우는 단계;Covering a stencil mask having a predetermined pattern formed on the chip; 상기 스텐실 마스크 상에 전도성을 가진 페이스트를 도포하는 단계;Applying a conductive paste on the stencil mask; 상기 도포된 페이스트를 밀어 상기 패턴대로 상기 칩 상에 상기 페이스트를 부착하는 단계; 및Pushing the applied paste to attach the paste onto the chip according to the pattern; And 상기 부착된 페이스트와 상기 기판 사이를 와이어로 전기적 연결을 하는 단계를 포함한 것을 특징으로 하는 반도체 패키지 제조방법.And electrically connecting a wire between the attached paste and the substrate. 제4항에 있어서,The method of claim 4, wherein 상기 소정 패턴은 상기 와이어와 연결되는 부분의 면적이 넓은 "T" 자 형상인 것을 특징으로 하는 반도체 패키지 제조방법.The predetermined pattern is a semiconductor package manufacturing method, characterized in that the "T" shape of a large area of the portion connected to the wire.
KR1020050086734A 2005-09-16 2005-09-16 Semiconductor package by pad redistribution and manufacture method thereof KR20070032468A (en)

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Publication number Priority date Publication date Assignee Title
EP3067923A1 (en) * 2015-02-18 2016-09-14 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3067923A1 (en) * 2015-02-18 2016-09-14 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US10586777B2 (en) 2015-02-18 2020-03-10 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

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