KR20070031463A - Power delivery system - Google Patents

Abstract

The system is disclosed. Such a system includes a load, a voltage regulation circuit connected to the load, a power source, a load connected to the power source to receive one or more voltages from the power source, and a digital bus connected between the power source and the load. This digital bus sends power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.

Power delivery system, digital bus, power, load

Description

Power delivery system {POWER DELIVERY SYSTEM}

<Copyright Notice>

Included here is the copyrighted material. The copyright owner has no objection to the facsimile copy of the patent disclosure by any person, as is the patent and trademark office files or records, but otherwise reserves all rights in any copyright.

<Technology field>

The present invention relates to a computer system; More specifically, the present invention relates to delivering power to a power sensing system such as a computer system.

Background

 Integrated circuit elements such as central processing units (CPUs) are typically powered by remotely located power supplies. Power consumption of CPUs is excessively high, and cost-effective cooling solutions are currently reaching physical limits. It is important to transform the energy converted into heat by CPU operation into performance. In addition, power supply technologies are approaching their limits, and the adjustment of supply voltages within tight tolerances entails higher costs for decoupling and packaging.

<Brief Description of Drawings>

The invention is shown by way of example and is not limited to the figures of the accompanying drawings, wherein like reference numerals represent like elements.

1 is a block diagram of one embodiment of a computer system.

2 is a block diagram of an exemplary power source connected to a voltage load.

3 is a block diagram of another example of a power supply connected to a voltage load.

4 is a block diagram of another example of a power source connected to a voltage load.

5 is a block diagram of another example of a power source connected to a voltage load.

6 is a block diagram of one embodiment of a voltage regulator module coupled to a CPU.

7 is a block diagram of another embodiment of a voltage regulation module coupled to a CPU.

8 is a block diagram of another embodiment of a voltage regulation module coupled to a CPU.

9 is a block diagram of one embodiment of a device.

10 is a block diagram of one embodiment of a voltage regulation module.

11 is a block diagram of another embodiment of a voltage regulation module.

12 is a block diagram of one embodiment of a CPU.

<Detailed Description of the Invention>

According to one embodiment, a power delivery system for a computer system is described. Power delivery systems characterize the performance of a power supply, load, or both to measure voltage, current, power, and temperature, and share measurements over a unidirectional or bidirectional digital bus. In one embodiment, this measurement is performed by sensing and sampling the analog signal, converting the signal into digital form, and encoding the signal into a suitable form for transmission over the bus.

Such measurement may be implemented by monitoring digital control signals already present at the power supply, for example, the output of the regulator (PWM, PFM, etc.). These control signals contain information about the duty cycle and switching frequency of the power supply and allow for indirect measurement of output current, voltage and power. In addition, existing control signals already present in the load (eg, the processor's clock frequency or I / O frequency) may be used to indirectly measure power consumption at the load. This shared information about the output power of the power supply or the input power of the load is used by the power supply, load, or both to manage and optimize DC and transient load regulation, power conversion efficiency, battery life or other aspects of system performance. can do.

In the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

Reference in the specification to “one embodiment” or “an embodiment” means that a given feature, structure, or characteristic described in connection with this embodiment is included in at least one embodiment of the present invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

1 is a block diagram of one embodiment of a computer system 100. Computer system 100 includes a central processing unit (CPU) 102 coupled to a bus 105. In one embodiment, the CPU 102 is a Pentium ^® family processor of the processes including the Pentium ^® II processor family, Pentium ^® III processors, and Pentium ^® IV processors available from Intel Corporation of Santa Clara, California. Also, other CPUs may be used.

Also, a chipset 107 is connected to the bus 105. Chipset 107 includes a memory control hub (MCH) 110. MCH 110 may include a memory controller 112 that is coupled to main system memory 115. Main system memory 115 stores data and sequences of instructions executed by CPU 102 or any other device included in system 100. In one embodiment, main system memory 115 includes dynamic random access memory (DRAM), but main system memory 115 may be implemented using other memory types. Further devices, such as multiple CPUs and / or multiple system memories, may be connected to the bus 105.

The chipset 107 also includes an input / output control hub (ICH) 140 connected to the MCH 110 via a hub interface. ICH 140 provides an interface to input / output (I / O) devices in computer system 100. ICH 140 may be connected to a Peripheral Component Interconnect (PCI) bus attached to a Specification Revision 2.1 bus developed by the PCI Special Interest Group of Portland, Oregon.

The computer system 100 also includes a voltage regulation module (VRM) and a power supply 165 coupled to the CPU 102. VRM 160 provides the regulated voltage supply to CPU 102. In one embodiment, the power supply 165, VRM 160, and CPU 102 are separate discrete devices, for example integrated circuits or printed circuit boards. However, in other embodiments, these devices may be integrated by packaging, bonding, or manufacturing on the same IC. In other embodiments, the power supply 165 may be connected directly to the CPU 102 without the implementation of the VRM 160.

As mentioned above, the power consumption of CPUs is excessively high. Currently, various mechanisms exist to increase the efficiency of power consumption. For example, FIG. 2 is a block diagram of a conventional power supply, or VRM, that delivers voltage to a load. In this example, the power supply performs the regulation of the output voltage. If the voltage is within certain limits, the power supply will signal a "power good" to inform the load that the load is safe to operate. Thus, the power good signal indicates that the output voltage from the power supply is stable.

3 is a block diagram of another conventional power supply for transferring voltage to a load. In this system, the load informs the power supply about the desired output voltage by transmitting a K-bit binary code through the parallel digital bus. Such a bus is commonly referred to as a VID bus. The power supply then outputs a voltage corresponding to the digital code.

4 is a block diagram of another conventional power delivery system. In such a system, the power supply uses additional lines to sense the output voltage at the load point. The power supply outputs a voltage on power lines connected to the load. If the load current changes, the actual voltage at the load point may be different from the voltage at the output terminal of the power supply since the load current causes a voltage drop on the power lines. Since sense lines are not significantly loaded by current, the power supply can accurately determine and adjust the actual voltage at the load point rather than its output terminals. These sense lines are the wires that directly connect the output terminals at the load point and the sense terminals of the power supply.

5 is a block diagram of another conventional power delivery system. In such a system, the power supply provides an analog signal (voltage or current) that is proportional to the output current flowing from one of the output voltage terminals to the load. In some cases, this power supply may use the signal internally for adjustment purposes. However, it may be difficult to route the analog signal from the power supply to the load in a noisy environment.

Since no devices (eg, power supply, VRM or load) can determine how other devices operate, all of the power delivery systems described above that are currently available cannot efficiently manage power consumption. Thus, actual power management is not possible. According to one embodiment, power consumption measurements are exchanged between the VRM 160 and the CPU 102 load. By exchanging these measurements, load power consumption may be managed efficiently.

6 is a block diagram of one embodiment of a VRM 160 coupled to the CPU 102 via a digital bus 610. In this embodiment, the CPU 102 broadcasts power consumption measurements over the bus 610. For example, the CPU 102 measures the voltages at the load point, converts the measured voltages into digital signals, and sends this signal to the VRM 160. In one embodiment, bus 610 is a parallel telemetry bus. However, in other embodiments, bus 610 may be implemented as a serial bus.

7 is a block diagram of another embodiment of a VRM 160 coupled to the CPU 102 via a digital bus 610. In this embodiment, power consumption measurements are broadcast over bus 610 by VRM 160 and received at CPU 102. For example, the VRM 610 measures output voltage and output current, or power, and sends this information to the CPU 102.

8 is a block diagram of another embodiment of a VRM 160 coupled to the CPU 102 via a digital bus 610. In this embodiment, bi-directional exchange of power consumption measurements occurs between the VRM 160 and the CPU 102. Power consumption measurements may include digitally encoded input and output voltages, currents, power, and temperature of VRM 160. Such measurements may also include input voltages, currents, power, and temperature of the CPU 102. According to one embodiment, the information may be binary encoded and having a discrete value. Thus, the amplitude of the signal may have a discrete value. For example, two different voltages can be used to represent logic zero and one.

9 is a block diagram of one embodiment of a device 900. The device 900 may be implemented as the VRM 160 or the CPU 102. In embodiments in which the power source 165 is directly connected to the CPU 102, the device 900 may also be implemented in the power source 165. Device 900 includes an analog-to-digital (A / D) converter 910, encoder 920, and interface 930.

In this embodiment, the power consumption measurements are derived from the analog signal digitized by the A / D converter 910, encoded by the encoder 920, so that the signal can be transmitted over the digital data bus 610. Is formatted by the interface 930. In another embodiment, A / D converter 910 outputs a digital word (eg, a binary word) in either parallel or serial format.

In other embodiments, other devices may be implemented instead of the A / D converter 910. For example, a voltage-to-frequency, current-to-frequency, voltage-to-time, or current-to-time converter may be used instead of the A / D converter 910.

10 is a block diagram of one embodiment of a device 1000 with analog control. Device 100 may be implemented as VRM 160 or power source 165, in which embodiments power source 165 is directly connected to CPU 102. The device 1000 includes a compensator 1010, a modulator 1020, an interface 1030, and a power stage 1040.

In the embodiment shown in FIG. 10, the device 1000 is a switching power supply. In a switching power supply, the control signal applied to the switching devices is essentially digital (eg, the switch can be either on or off). The modulator 1020 generates a control signal. In one embodiment, modulator 1020 is a pulse-width modulator (PWM). However, in other embodiments, the modulator 1020 may be a pulse-frequency modulator (PFM), constant on time or constant off time modulator, or the like.

Modulator 1020 determines a control signal based on an error signal received from compensator 1010 that senses voltages and currents at various points. According to one embodiment, the digital signal output by the modulator 1020 is transmitted over the digital bus 610. In switching power supplies based on various phases (eg, flyback, buck, boost, etc.), the digital signal from modulator 1020 includes information about the output power. Compared to the device 900 described above, the device 1000 does not implement an explicit A / D converter.

11 is a block diagram of one embodiment of a device 1100 with digital control. The device 1100 may be implemented as a VRM 160 or a power supply 165, in which embodiments the power supply 165 is directly connected to the CPU 102. The device 1100 includes an A / D converter 1105, a compensator 1110, a modulator 1120, an interface 1130, and a power stage 1140. In the present embodiment, compensator 1110 and modulator 1120 are digital. Thus, any signal after the A / D converter 1105 is transmitted over the digital bus for the purpose of power measurement.

12 is a block diagram of one embodiment of the CPU 102. CPU 102 includes a clock generator 1210, an I / O interface 1220, an ALU 1225, and an interface 1230. These digital blocks draw current from the voltage provided from the VRM 160 or the power supply 165. In CMOS processes and other techniques, power consumption is strongly correlated to the switching operation or immediate state of the CPU 102 load. Thus, for example, digital signals derived from clock frequency, I / O transmission activity, ALU 1225 activity, the number of I / O bits in a given state, or the like, may provide an approximate or accurate estimate of the power consumed by the load. Provide the information to allow. Such signals may be broadcast over digital data bus 610 for current or power estimation purposes.

As many variations and modifications of the present invention will undoubtedly be apparent to those skilled in the art upon reading the foregoing description, any particular embodiment described and illustrated by way of example is not intended to be limiting. Thus, the detailed description of various embodiments is not intended to limit the claims, which themselves themselves cite only those features that are considered essential to the present invention.

Claims (25)

power; A load coupled to the power source for receiving one or more voltages from the power source; And A digital bus coupled between the power source and the load to transmit power consumption measurements from the load to the power source and to transmit power consumption measurements from the power source to the load System comprising a. The method of claim 1, The load converts the measured load voltage into a digital signal and transmits the signal to the power supply via the digital bus. The method of claim 1, The power consumption measurements sent from the load are selected from the group comprising input voltage, output voltage, input current, output current, input power, output power and temperature. The method of claim 1, The power supply measures values corresponding to the power consumed by the load and transmits the values to the load via the digital bus. The method of claim 1, The power consumption measurements sent from the power source are selected from the group comprising output voltage, current, power and temperature. The method of claim 1, The digital bus is a serial bus. The method of claim 1, The digital bus is a parallel bus. The method of claim 1, The power supply is a voltage regulation circuit. The method of claim 1, The power source, Analog-to-digital (A / D) converters to digitize analog signals; An encoder coupled to the A / D converter to encode the digitized signal; And An interface coupled to the encoder and the digital bus to interface with the digital bus System comprising a. The method of claim 1, The power source, Compensators; A modulator coupled to the compensator for generating a control signal; And An interface coupled to the modulator and the digital bus to interface with the digital bus System comprising a. The method of claim 10, The power supply further comprises a power stage coupled to the modulator. The method of claim 10, The power supply further comprises an analog-to-digital (A / D) converter coupled to the compensator and the interface. The method of claim 1, The load, Analog-to-digital (A / D) converters to digitize analog signals; An encoder coupled to the A / D converter to encode the digitized signal; And An interface coupled to the encoder and the digital bus to interface with the digital bus System comprising a. The method of claim 1, The load, A clock generator; Input / output (I / O) interfaces; Arithmetic logic unit (ALU); And An interface connected to the digital bus System comprising a. Transferring one or more voltages from a power source to a load; Receiving power consumption measurements from a load via a digital bus at the power supply; And Transmitting power consumption measurements over the digital bus from the power supply to the load How to include. The method of claim 15, And measuring the values corresponding to the magnitude of power consumed by the load before the power source transmits the power consumption measurements from the power source to the load. The method of claim 15, Converting the value from an analog signal to a digital signal; And Encoding the digital signal. The method of claim 15, And modulating the value to generate a control signal. power; A voltage regulator module (VRM) connected to the power supply; A central processing unit (CPU) coupled to the VRM for receiving one or more voltages from the VRM; And A digital bus coupled between the VRM and the CPU to transmit power consumption measurements from the CPU to the VRM and to transmit power consumption measurements from the VRM to the CPU. Computer system comprising a. The method of claim 19, The VRM measures values corresponding to power consumed by a CPU and transmits the values to the CPU via the digital bus. The method of claim 19, And the digital bus is a serial bus. The method of claim 19, And the digital bus is a parallel bus. The method of claim 19, The VRM is, Analog-to-digital (A / D) converters to digitize analog signals; An encoder coupled to the A / D converter to encode the digitized signal; And An interface coupled to the encoder and the digital bus to interface with the digital bus Computer system comprising a. The method of claim 20, The CPU is Analog-to-digital (A / D) converters to digitize analog signals; An encoder coupled to the A / D converter to encode the digitized signal; And An interface coupled to the encoder and the digital bus to interface with the digital bus Computer system comprising a. The method of claim 19, The CPU is A clock generator; Input / output (I / O) interfaces; Arithmetic logic unit (ALU); And An interface connected to the digital bus Computer system comprising a.

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