KR20070030788A - Improved strained-silicon cmos device and method - Google Patents

Abstract

The present invention provides a semiconductor device in which a single axis strain is generated in a device channel of the semiconductor device, and a method of manufacturing the same. The uniaxial strain is in tension or compression and in a direction parallel to the device channel. Uniaxial strain may be produced on the biaxial strained substrate surface by strain induced liners, strain induced wells or a combination thereof. Uniaxial strain can be produced in a reduced substrate by a combination of strain induced wells and strain induced liners. The present invention also provides a means for increasing biaxial strain in the strain induced isolation region. The present invention further provides a CMOS device in which the device region of the CMOS substrate is processed independently to provide a biaxial strained semiconductor surface in a compressed or tensile state.

Description

IMPROVED STRAINED-SILICON CMOS DEVICE AND METHOD

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices with improved electron and hole mobility, and more particularly to semiconductor devices including silicon (Si) containing layers with improved electron and hole mobility. The present invention also provides a method of manufacturing such a semiconductor device.

Over the past three decades, miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has continued in the semiconductor industry around the world. Although showstoppers have been insisted on decades for continued scaling, the history of technological innovation maintains Moore's Law despite many challenges. Recently, however, signals have emerged that metal oxide semiconductor transistors begin to reach their traditional scaling limits. A concise summary of the short-term and long-term challenges to continued complementary metal oxide semiconductor (CMOS) scaling can be found in the “Grand Challenges” section of the 2002 Update of the International Technology Roadmap for Semiconductors (ITRS). You can find it. Details on devices, materials, circuits and systems can be found in the Proc. IEEE, Volume 89, Issue 3, March 2001.

As the improvement of MOSFET and hence CMOS performance through continuous scaling becomes increasingly difficult, a method of improving performance without scaling becomes important. One way to do this is to increase carrier (electron and / or hole) mobility. Increased carrier mobility can be obtained, for example, by introducing an appropriate strain into the Si lattice.

Applying strain alters the lattice dimension of the silicon (Si) containing substrate. By changing the lattice dimensions, the electronic band structure of the material is also changed. The change occurs only slightly in the intrinsic semiconductor, resulting in a small resistance change, but when the semiconductor material is doped n-type and partially ionized, a very small change in energy band produces a very large change in energy difference between impurity concentration and the band edge Can cause. This results in a change in carrier carrying properties which in some cases can be very large. The application of physical stresses (tensile or compressive) can be further used to improve the performance of devices fabricated on Si containing substrates.

Compression strain along the device channel increases the drive current of the p-type field effect transistor (pFET) and reduces the drive current of the n-type field effect transistor (nFET). Tensile strain along the device channel increases the drive current of the nFET and decreases the drive current of the pFET.

Strained silicon on a relaxed SiGe buffer layer or on a relaxed insulator SiGe (SiGe-on-insulator (SGOI)) is an nFET [K.Rim, p.98, VLSI 2002, B.Lee, IEDM 2002] and pFET. [K. Rim et al., P. 98, VLSI 2002] all show higher drive currents. Although having strained silicon or strained silicon directly on insulator (SSDO) on an SGOI substrate may reduce some processing related problems such as short channel effects and improved As diffusion in SiGe [S. Takagi et al., P. 03-57, IEDM 2003; K. Rim et al., P. 3-49, IEDM 2003], the increase in drive current begins to decrease as devices are downscaled to very short channel dimensions [Q. Xiang et al., VLSI 2003; J. R. Hwang et al., VLSI 2003]. The term "extreme channel" means a device channel that is about 50 nm or less in length.

In extreme channel devices, the reduction in drive current is caused by the source / drain series resistance and the mobility decay appears to be due to higher channel doping by strong halo doping, velocity saturation, and self-heating. Lose.

In addition, for biaxial tensile strain such as strained silicon epitaxially grown on relaxed SiGe, significant hole mobility increase of the pFET device only occurs when the device channel is under high (> 1%) strain, which is undesirable. It tends not to have crystal defects. The strain produced by the lattice mismatch between epitaxially grown Si on relaxed SiGe is also reduced by the stress induced by the shallow trench isolation regions, where the effect of the shallow trench isolation regions is reduced from the source / gate edge. This is especially important for devices with dimensions of about 500 nm or less to the end of the drain region [T. Sanuki et al., IEDM 2003].

Further scaling of semiconductor devices requires controlling the level of strain produced in the substrate and developing new methods to increase the amount of strain that can be produced. In order to maintain the improvement of strained silicon with scaling, the amount of strain must be maintained or increased in the silicon containing layer. Further technological innovations are needed to increase carrier mobility in pFET devices.

The present invention provides a strained nFET device that provides improved carrier mobility in a device channel susceptible to tensile uniaxial strain in a direction parallel to the device channel. The present invention also provides a strained pFET device provided with improved carrier mobility by compression uniaxial strain introduced into the device in a direction parallel to the device channel. The invention further includes a CMOS structure comprising a pFET and an nFET device on the same substrate, wherein the device channel of the pFET device is under uniaxial compression strain and the device channel of the nFET device is under uniaxial tensile strain, and the compression Both strain and tensile strain are in a direction parallel to the device channel.

The present invention described above is a transistor on a semiconductor surface having a biaxial tensile strain when the semiconductor surface is epitaxially grown on a SiGe layer or a biaxial compressive strain when the semiconductor surface is epitaxially grown on a carbon-doped silicon layer. And then induce a uniaxial tensile strain or compressive strain on the device channel. Uniaxial tensile strain or compression strain is produced by strain induced dielectric liners located on the transistors and / or by strain induced wells adjacent to the device channels. Broadly speaking, the semiconductor structure of the present invention is:

A substrate comprising a strained semiconductor layer on a strain inducing layer, the strain inducing layer producing biaxial strain in the strained semiconductor layer;

At least one gate region comprising a gate conductor over a device channel portion of the strained semiconductor layer, wherein the device channel portion separates a source and drain region near the at least one gate conductor;

And a strain induced liner located in the at least one gate region, wherein the strain induced liner is to create a single axial strain in the device channel portion of the strained semiconductor layer below the at least one gate region.

The strain inducing layer consists of SiGe when the biaxial strain on the strained semiconductor surface is in tension, or the strain inducing layer consists of carbon doped silicon when the biaxial strain on the strained semiconductor surface is in compression Can be.

Tensile strain induction liners positioned over transistors with device channels in biaxial tensile strain produce a single axis tensile strain in the device channel, where the single axis strain is in a direction parallel to the device channel and increases carrier mobility in the nFET device. To provide. Compression strain induction liners positioned over transistors with device channels in a biaxial tensile strain produce a single axis compression strain in the device channel, where the single axis strain is in a direction parallel to the device channel and increases carrier mobility in the pFET device. To provide. Compression strain induction liners positioned over transistors with device channels within a biaxial compression strain produce a single axis strain in the device channel, where the single axis compression strain is in a direction parallel to the device channel and increases carrier mobility in the pFET device. To provide.

Another aspect of the invention is a semiconductor structure in which a strain induced well near a biaxially strained device channel induces a uniaxial compressive strain or a monoaxial tensile strain parallel to the device channel. Broadly speaking, the semiconductor structure of the present invention is:

A substrate comprising a strained semiconductor layer on a strain induced layer, the strain induced layer producing biaxial strain in the strained semiconductor layer;

At least one gate region comprising a gate conductor over a device channel portion of the strained semiconductor layer of the substrate, the device channel separating a source and a drain region;

And strain induced well near the at least one gate region, wherein the strain induced well near the at least one gate region is to generate a uniaxial strain in the device channel portion of the strained semiconductor layer.

Strain induction wells comprising carbon doped silicon, located near the device channel in the biaxial tensile strain semiconductor layer, produce a tensile single axis strain in the device channel, the single axis strain being parallel to the device channel. Is in. Tensile uniaxial strain can provide increased carrier mobility in nFET devices.

Strain induction wells, including SiGe, located near the device channel in the biaxial compressive strain semiconductor layer create a compressive single axis strain in the device channel, the single axis strain being in a direction parallel to the device channel. Compression uniaxial strain can provide increased carrier mobility in pFET devices.

Another aspect of the invention is a complementary metal oxide semiconductor (CMOS) structure including nFET and pFET devices. Broadly speaking, the structure of the present invention is:

A substrate comprising a compressive strained semiconductor surface and a tensile strained semiconductor surface, wherein the compressive strained semiconductor surface and the tensile strained semiconductor surface are biaxially strained;

At least one gate region over said compressive strained semiconductor layer comprising a gate conductor over a device channel portion of said compressive strained semiconductor layer of said substrate;

At least one gate region over said tensile strained semiconductor layer comprising a gate conductor over a device channel portion of said tensile strained semiconductor layer of said substrate;

Compressive strain induced liner over the at least one gate region on the compressive strain semiconductor surface—the compressive strain induced liner creates a compressive monoaxial strain in the device channel portion of the compressive strain semiconductor layer, the compressive monoaxial strain Is in a direction parallel to the device channel portion of the compressive strained semiconductor surface;

Tensile strain induction liner over the at least one gate region on the tensile strain semiconductor layer—The tensile strain induction liner creates a uniaxial strain in the device channel portion of the tensile strain semiconductor layer, and the tensile uniaxial strain Is in a direction parallel to the device channel portion of the tensile strained semiconductor layer.

Another aspect of the invention is a complementary metal oxide semiconductor (CMOS) structure including nFETs and pFET devices. Broadly speaking, the structure of the present invention is:

a substrate comprising a tensile strained semiconductor layer having a pFET device region and an nFET device region;

At least one gate region in the pFET device region comprising a gate conductor over a pFET device channel portion of the tensile strained semiconductor layer;

At least one gate region in the nFET device region comprising a gate conductor over an nFET device channel portion of the tensile strained semiconductor surface of the substrate;

A compressive strain induced liner over the at least one gate region in the pFET device region, the compressive strain induced liner to produce a compressive uniaxial strain in the pFET device channel;

Tensile strain inducing liner over the at least one gate region in the nFET device region, wherein the tensile strain inducing liner is to create a monoaxial tensile strain in the nFET device channel.

The aforementioned structure may further include strain induced wells in the nFET device region and at least one gate region in the pFET device region, where the strain induced wells in the pFET device region increase the compressive single axis strain and reduce Strain induction wells increase tensile monoaxial strain.

Another aspect of the invention is a method of forming a semiconductor structure as described above comprising a stress induced liner and / or strain induced wells that provide uniaxial strain in the device channel portion of the substrate. In broad terms, the method of the present invention is:

At least one strained semiconductor surface—the at least one strained semiconductor surface has internal strains of equal magnitude in the first and second directions, the first direction being in the same crystal plane and perpendicular to the second direction Providing a substrate having one;

At least one semiconductor device on said at least one strained semiconductor surface, said at least one semiconductor device comprising a gate conductor over a device channel portion of said semiconductor surface, said device channel separating source and drain regions; Generating a;

A strain induced liner over the at least one gate region—the strain induced liner creates a uniaxial strain in the device channel, and the magnitude of the strain in the first direction is within the device channel portion of the at least one strained semiconductor surface. Forming different from the second direction.

Another aspect of the invention is a method of increasing biaxial strain in a semiconductor layer. Biaxial strain in a semiconductor layer can be increased in compression or tension by forming isolation regions around active device regions with intrinsic compression or tensile dielectric filler. According to the method of the present invention, uniaxial strain can be induced by forming a series of strain guide wells in the vicinity of at least one gate region instead of or in conjunction with the strain guide liner.

The present invention also provides for improved carrier mobility of semiconductor devices formed on a relaxed substrate, wherein a single-axis strain parallel to the device channel of the transistor is provided with a strain induction liner located above the transistor and a strain induction well located near the device channel. Provided by a combination. Broadly speaking, the semiconductor structure of the present invention is:

A relaxation substrate;

At least one gate region comprising a gate conductor over a device channel portion of the relaxed substrate, the device channel portion separating a source and drain region in the vicinity of the at least one conductor;

A strain induction well near said at least one gate region;

A strain induced liner positioned above the at least one gate region—the strain induced liner and the strain induced well create a uniaxial strain in the device channel portion of the relief portion of the substrate that is below the at least one gate region. To be included.

Another aspect of the invention is a complementary metal oxide semiconductor (CMOS) structure including nFETs and pFET devices that can be formed on a substrate having a biaxial strained semiconductor surface and / or a relaxed semiconductor surface. Broadly seen, one method of providing a CMOS structure formed on a substrate having both a relaxed and biaxially strained semiconductor surface comprises providing a substrate having a first device region and a second device region; Creating at least one semiconductor device over a device channel portion of the substrate in the first device region and the second device region; Generating a single axis strain in the first device region and the second device region, wherein the single axis strain is in a direction parallel to the device channels of the first device region and the second device region. do. The first device region may comprise a biaxial strained semiconductor surface and the second device region may comprise a relaxed semiconductor surface.

According to the present invention, the step of generating uniaxial strain in the first device region and the second device region further comprises processing the first device region and the second device region to provide a combination of strain guide structures. The first device region may include a biaxial strained semiconductor surface and strain induced liner over at least one semiconductor device, a biaxial strained semiconductor surface and strain induced wells near the at least one semiconductor device, or a combination thereof. . The second device region may include a relaxation substrate, a strain guide liner over the at least one semiconductor device, and a strain guide well near the at least one semiconductor device.

1 is a cross-sectional view of one embodiment of a semiconductor device of the present invention including an nFET device channel having a uniaxial tensile strain in a direction parallel to the device channel.

FIG. 2 is a cross-sectional view of another embodiment of a semiconductor device of the present invention including a pFET device channel having a single axial compression strain over a SiGe layer in a direction parallel to the device channel.

3 is a cross-sectional view of another embodiment of a semiconductor device of the present invention including a pFET device channel having a single axial compression strain over a Si: C layer in a direction parallel to the device channel.

4 is a cross-sectional view of one embodiment of a CMOS structure of the present invention including the nFET device of FIG. 1 and the pFET device of FIG.

5 is a cross-sectional view of one embodiment of a CMOS structure of the present invention including the nFET device of FIG. 1 and the pFET device of FIG.

6 is a cross-sectional view of another embodiment of a semiconductor device of the present invention including an nFET device channel having a single-axis compression strain formed over a relaxed semiconductor substrate.

FIG. 7 is a cross-sectional view of another embodiment of a semiconductor device of the present invention including a pFET device channel having a uniaxial tensile strain formed over a relaxed semiconductor substrate. FIG.

8 is a cross-sectional view of one embodiment of a CMOS structure of the present invention including a relaxed substrate region and a biaxial strained semiconductor region.

9A-9C show the relationship between lattice dimensions and uniaxial strain parallel to the device channels in compression and tension.

FIG. 10 shows the relationship of I _off to I _on of an nFET device having tensile strain induced and compressive strain induced dielectric layers (tensile strain induced and compressive strain induced liners).

FIG. 11 shows the relationship of I _off to I _on of a pFET device with tensile strain induced and compressive strain induced dielectric layers (tensile strain induced and compressive strain induced liners).

The present invention provides a CMOS structure comprising pFET and nFET devices in which the symmetry of the unit grating in the device channel of each device type can be separated in three directions, where the grating dimension (constant) in each direction is at least 0.05%. different. The lattice direction of the device channel includes a direction parallel to the channel plane (x direction), a direction perpendicular to the channel plane (y direction), and a direction outside the channel plane (z direction).

The present invention also provides a strained silicon nFET in which the lattice constant parallel to the nFET device channel is greater than the lattice constant perpendicular to the nFET device channel and the lattice constant difference is induced by tensile single-axis strain parallel to the device channel. The present invention also provides a strained silicon pFET in which the lattice constant perpendicular to the pFET device channel is greater than the lattice constant parallel to the pFET device channel and the lattice constant difference is induced by compressive uniaxial strain parallel to the device channel. The present invention also provides a pFET and / or nFET device on a relaxed substrate surface where the combination of strain induced liner and strain induced well produces a uniaxial strain parallel to the device channel portion of the pFET and / or nFET device. .

The invention will now be described in detail with reference to the accompanying drawings, which accompany this specification. In the accompanying drawings, the same or corresponding elements are denoted by the same reference numerals. A single gate region is shown in the figure and will be described. Notwithstanding this description, the present invention is not limited to the structure having a single gate region. Rather, a structure having a plurality of such gate regions is expected.

Referring to FIG. 1, in one embodiment of the present invention, there is a uniaxial tensile strain in the device channel 12 of the laminate structure 10 and the uniaxial tensile strain is in a direction parallel to the length of the device channel 12. An n-type field effect transistor (nFET) 20 is provided. The length of the device channel 12 separates the extension 17 of the source and drain regions 13, 14 of the device. Uniaxial tensile strain in device channel 12 of nFET 20 is created by the combination of biaxial tensile strain semiconductor layer 15 and tensile strain inducing liner 25. Gate region 5 includes gate conductor 3 over gate dielectric 2.

Biaxial tensile strained semiconductor layer 15 is formed by epitaxially growing silicon on SiGe strain inducing layer 17. Biaxial tensile strain is derived from epitaxial silicon grown on a surface formed of a material whose lattice constant is greater than the lattice constant of silicon. The lattice constant of germanium is about 4.2% larger than the lattice constant of silicon, and the lattice constant of the SiGe alloy is linear with respect to its germanium concentration. As a result, the lattice constant of SiGe alloy containing 50 atomic% germanium is about 2.1 times larger than the lattice constant of silicon. Epitaxial growth of Si on this SiGe strain inducing layer 17 creates a Si layer under biaxial tensile strain, and the underlying SiGe strain inducing layer 17 is essentially completely or partially unstrained or relaxed (relax)

The term "biaxial tension" means that the tensile strain is produced in a first direction parallel to the nFET device channel 12 and in a second direction perpendicular to the nFET device channel 12, wherein the strain in the first direction The magnitude is equal to the magnitude of the strain in the second direction.

The tensile strain inducing liner 25 preferably comprises Si ₃ N ₄ and is located above the gate region 5 and above the exposed surface of the biaxial tensile strain semiconductor layer 15 near the gate region 5. Tensile strain induction liner 25, together with biaxial tensile strained semiconductor layer 15, produces a single axial tensile strain on device channel 12 in the range of about 100 MPa to about 3000 MPa, where the device channel ( The direction of the uniaxial strain on 12 is parallel to the length of the device channel 12.

The device channel 12 is in a biaxial tensile strain state before the tensile strain induction liner 25 is formed, and the magnitude of the strain produced in the direction perpendicular to the device channel 12 is in a direction parallel to the device channel 12. It is equal to the size of strain generated by. Application of the tensile strain induction liner 25 produces a uniaxial strain in a direction parallel to the device channel 12 (x direction), wherein the magnitude of the tensile strain parallel to the device channel 12 is determined by the device channel 12. Larger than the tensile strain perpendicular to). Also, the lattice constant in nFET device 20 along device channel 12 is greater than the lattice constant across device channel 12.

Referring again to FIG. 1, in another embodiment of the present invention, tensile strain induction well 30 is positioned adjacent device channel 12 in each source and drain region 13, 14. Tensile strain induction well 30 includes carbon doped silicon (Si: C) or carbon doped silicon germanium (SiGe: C). Tensile strain inducing wells 30 including intrinsic tensile Si: C may be grown epitaxially over the recesses of the biaxial tensile strained semiconductor layer 15. The term "intrinsic tensile Si: C layer" means that the Si: C layer is under an internal tensile strain, where the tensile strain is a small lattice dimension of Si: C and a large layer of epitaxially grown Si: C layer. Caused by lattice mismatch between lattice dimensions. Tensile strain induction well 30 creates a monoaxial tensile strain in a direction parallel to nFET device channel 12 within device channel 12.

In one embodiment, tensile strain induction well 30 may be omitted if tensile strain induction liner 25 is provided. In another embodiment of the present invention, tensile strain induction liner 25 may be omitted if tensile strain induction well 30 is provided. In another embodiment, both tensile strain guide well 30 and tensile strain guide liner 25 can be used. The method of forming the nFET 20 of the present invention will be described in detail below.

In a first processing step, a laminate structure 10 is provided that includes a biaxial tensile strained semiconductor layer 15. The laminate structure 10 may include tensile strained Si on SiGe, strained Si (SSGOI) on SiGe-on-insulator (SiGe) on insulator, or tensile strained Si (SSDOI) directly on insulator. In a preferred embodiment, the laminate structure 10 includes a tensile SSGOI with a silicon containing biaxial tensile strained semiconductor layer 15 over the SiGe strain inducing layer 17.

In a first processing step, a SiGe strain inducing layer 17 is formed over the Si containing substrate 9. The term "Si containing layer" is used herein to refer to a material comprising silicon. Examples of Si-containing materials include, but are not limited to, Si, SiGe, SiGeC, SiC, polysilicon (polySi), epitaxial silicon (epi-Si), amorphous silicon (a: Si), SOI and multilayers thereof Etc. An optional insulating layer may be located between the SiGe strain inducing layer 17 and the Si containing substrate 9.

SiGe strain induced layer 17 is formed over the entire Si-containing substrate 10 using an epitaxial growth process or by a deposition process such as chemical vapor deposition (CVD). The Ge component of the SiGe strain inducing layer 17 is typically in the range of 5% to 50% by weight of atoms, more typically in the range of 10% to 20%. Typically, the SiGe strain inducing layer 17 may be grown to a thickness in the range of about 10 nm to about 100 nm.

A biaxial tensile strained semiconductor layer 15 is then formed over the SiGe layer 17. Biaxial tensile strained semiconductor layer 15 comprises an epitaxially grown Si containing material having a lattice dimension smaller than the lattice dimension of lower SiGe layer 17. The biaxial tensile strained semiconductor layer 15 can be grown to a thickness below its critical thickness. Typically, biaxial tensile strained semiconductor layer 15 may be grown to a thickness in the range of about 10 nm to about 100 nm.

Alternatively, the biaxial tensile strained semiconductor layer 15 can be formed directly on the insulating layer to provide an insulator directly strained silicon (SSDOI) substrate. In this embodiment, biaxial tensile strained semiconductor layer 15 including epitaxial Si is grown on a wafer with a SiGe surface. The biaxial tensile strained semiconductor layer 15 is then bonded to the dielectric layer of the support substrate using a bonding method such as thermal bonding. After bonding, the wafer with the SiGe surface and the SiGe layer over the strained Si layer is removed using a process including smart cut and etching to provide a biaxial tensile strained semiconductor layer 26 bonded directly to the dielectric layer. A more detailed description of the formation of strained Si directly on insulator substrate 105 with at least biaxial tensile strained semiconductor layer 15 is entitled 'Strained Si on Insulator Structures'. US Pat. No. 6,603,156.

After the formation of the stacked structure 10 with the biaxial tensile strained semiconductor layer 15, non-limiting examples include the formation of conventional gate pre-clean oxide and gate dielectrics 2; Gate electrode 3 formation and patterning; Gate reification; Source and drain extensions 7 formed; Formation of sidewall spacers 4 by deposition and etching; And conventional MOSFET processing steps, including source and drain (13, 14) formation.

In the next processing step, a tensile strain induction liner 25 is deposited over at least the gate region 5 and the exposed surface of the biaxial tensile strain semiconductor layer 15 near the gate region 5. Tensile strain induction liner 25 creates a uniaxial tensile strain in device channel 12 of an nFET device having a direction parallel to device channel 12 with biaxial tensile strained semiconductor layer 15. Tensile strain induced liner 25 may be nitride, oxide, doped oxide, such as boron phosphate silicate glass, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , HfSiO, other dielectric materials common in semiconductor processing, or any combination thereof. It may include. Tensile strain induction liner 25 may have a thickness in the range of about 10 nm to about 500 nm, preferably about 50 nm. Tensile strain induced liner 25 may be deposited by plasma enhanced chemical vapor deposition (PECVD) or rapid thermal chemical vapor deposition (RTCVD).

Preferably, the tensile strain induction liner 25 comprises a nitride such as Si ₃ N _4, and the processing conditions of the deposition process are selected to provide intrinsic tensile strain in the deposited layer. For example, plasma enhanced chemical vapor deposition (PECVD) can provide nitride stress inducing liners with intrinsic tensile strain. The stress state of the nitride stress inducing liner deposited by PECVD can be controlled by changing the deposition conditions to change the reaction rate in the deposition chamber. More specifically, the stress state of the deposited nitride strain induction liner can be set by changing deposition conditions such as SiH ₄ / N ₂ / He gas flow rate, pressure, RF power, and electrode gap.

In another example, rapid thermal chemical vapor deposition (RTCVD) can provide a nitride tensile strain inducing liner 25 with an internal tensile strain. The size of the internal tensile strain produced in the nitride tensile strain induced liner 25 deposited by RTCVD can be adjusted by changing the deposition conditions. More specifically, the size of the tensile strain in the nitride strain induction liner 25 may be set by changing deposition conditions such as precursor composition, precursor flow rate and temperature.

In another embodiment of the present invention, the tensile strain induction well 30 may be formed after the nFET device 20 is formed and before the deposition of the tensile strain induction liner 25. In the first processing step, recesses are formed in the portion of the biaxial tensile strained semiconductor layer 15 where the source and drain regions 13, 14 are located. The recess can be formed by photolithography and etching techniques. Specifically, an etching mask, which preferably includes a patterned photoresist, is formed over the surface of the entire structure except for the portion of the biaxial tensile strained semiconductor layer 15 near the gate region. The surface of the biaxial tensile strained semiconductor layer 15 over the source and drain regions 13, 14 is then oriented by an directional (isotropic) etching from about 10 nm to about 300 from the surface where the gate region 15 is located. Make it concave to the depth of nm.

In the preferred embodiment, the tensile strain inducing well 30 erodes below the sidewall spacer 4 adjacent the gate electrode 3 in the gate region 5. By placing the tensile strain induction well 30 closer to the device channel 12, the strain generated along the device channel 12 increases. Tensile strain induced wells 30 may be located closer to the device channel 12 by an etching process that performs a first directional (isotropic) etch followed by a non-directional (isotropic) etch, wherein the non-directional etch is a sidewall spacer 4. ) Undercuts to provide recesses that erode the device channel 12.

In the next processing step, carbon doped silicon (Si: C) is epitaxially grown on the concave surface of the biaxial tensile strained semiconductor layer 15 over the source and drain regions 13, 14 to induce tensile strain. The well 30 is formed. Epitaxially grown Si: C is under internal tensile strain (also called intrinsic tensile strain), where the tensile strain is a small lattice dimension of epitaxially grown Si: C and Si: C is epitaxially It is created by lattice mismatch between the large lattice dimensions of the concave surface of the biaxial tensile strained semiconductor layer 15 that is grown. Tensile strain induction wells 30 create a uniaxial tensile strain in device channel 12 of nFET device 20 with a direction parallel to device channel 12. Although Si: C is good, any other intrinsic tensile material, such as Si, intrinsic tensile nitride, and oxide, may be used as long as it produces uniaxial tensile strain in device channel 12.

In another embodiment of the present invention, a tensile strain induced isolation region 50 including an intrinsic tensile dielectric filler is formed, wherein the intrinsic tensile dielectric filler has a strain size in the biaxial tensile strained semiconductor layer 15 from about 0.05 to Increase by about 1%. Isolation region 50 is formed by first etching the trench by a directional etching process such as reactive ion etching. After forming the trench, the trench is filled with a dielectric having an intrinsic tensile strain such as nitride or oxide deposited by chemical vapor deposition. The deposition conditions for producing the intrinsic tensile dielectric filler are similar to those described above for forming the tensile strained dielectric liner 25. As an option, conventional planarization treatments such as chemical mechanical polishing (CMP) can be used to provide planar structures.

2, in another embodiment of the present invention, a p-type field effect transistor (pFET) having a single-axis compression strain is provided in the device channel 12 of the substrate 10, wherein the single-axis compression strain is a device channel. It has a direction parallel to the length of (12). In this embodiment, the uniaxial compressive strain is produced by the combination of biaxial tensile strained semiconductor layer 15 and compressive strain induced liner 55.

Biaxial tensile strained semiconductor layer 15 is Si epitaxially grown on SiGe strain inducing layer 17 similar to the biaxial tensile strained semiconductor layer 15 described above with reference to FIG. 1. The biaxial tensile strain semiconductor layer 15 may comprise epitaxial silicon grown on the SiGe strain inducing layer 17, wherein the Ge concentration of the SiGe strain inducing layer 17 is at least 5%.

Referring again to FIG. 2, the compressive strain induction liner 55 preferably comprises Si ₃ N ₄ , a biaxial tensile strained semiconductor layer 15 over and adjacent to the gate region 5. Is positioned above the exposed surface of the. Compression strain induction liner 55, together with biaxial tensile strained semiconductor layer 15, produces a single axial compression strain in the range of about 100 MPa to about 2000 MPa on device channel 12, wherein The direction is parallel to the length of the device channel 12.

Before the compression strain induction liner 55 is formed, the device channel 12 is in a biaxial tensile strain, where the magnitude of the tensile strain produced in the direction perpendicular to the device channel 12 is determined by the device channel 12. Is the magnitude of the tensile strain produced in a direction parallel to Application of the compression strain induction liner 55 produces a single axial compression strain in a direction parallel to the device channel 12. Therefore, the lattice constant in pFET device 45 across device channel 12 is greater than the lattice constant along device channel 12.

Referring again to FIG. 2, in another embodiment of the present invention, the compressive strain induction well 60 is located adjacent to the device channel 12 in each source and drain region 13, 14. Compression strain induction well 60 including intrinsic compression SiGe may be grown epitaxially over the recess of biaxial tensile strain semiconductor layer 15. The term “intrinsic compressive SiGe layer” means that the SiGe layer is under intrinsic compressive strain (also called intrinsic compressive strain), where the compressive strain is the large lattice dimension of SiGe and the small lattice dimension of the layer where SiGe is epitaxially grown. It is generated by the lattice mismatch of the liver. Compression strain induction well 60 produces uniaxial compression strain in device channel 12. Uniaxial compression strain in the device channel 12 can be increased by placing the compression strain induction well 60 near the device channel. In one preferred embodiment, the compressive strain induction well 60 erodes below the sidewall space 4 adjacent the gate electrode 3 of the gate region 5.

Now, a method of forming the pFET 45 of the present invention will be described. In a first processing step, a laminate structure 10 having a biaxial tensile strained semiconductor layer 15 is provided. In one embodiment, the laminate structure 10 includes a biaxial tensile strained semiconductor layer 15 over the SiGe strain inducing layer 17, and the SiGe strain inducing layer 17 is formed on the Si containing substrate 9. do. Si-containing substrate 9 and SiGe layer 17 are similar to Si-containing substrate 9 and SiGe layer 17 described above with reference to FIG. 1.

After forming the stacked structure 10, the pFET device 45 is formed using conventional processing methods. The pFET device 45 is formed using a MOSFET process similar to the method for generating the nFET device 20 as described with reference to FIG. 1 except that the source and drain regions 13 and 14 are doped to p type.

Referring again to FIG. 2, in the next processing step, a compressive strain induction liner 55 is at least over the gate region 5 and on the exposed surface of the biaxial tensile strained semiconductor layer 15 adjacent to the gate region 5. Is deposited on. Compression strain induction liner 55 may be formed of nitride, oxide, doped oxide, such as boron phosphate silicate glass, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , HfSiO, other dielectric materials common in semiconductor processing, or any combination thereof. It may include. Compression strain induction liner 55 has a thickness in the range of about 10 nm to about 100 nm, preferably about 50 nm. Compression strain induction liner 55 may be deposited by plasma enhanced chemical vapor deposition (PECVD).

Preferably, the compressive strain induction liner 55 comprises a nitride such as Si ₃ N _4, and the processing conditions of the deposition process are selected to provide true compressive strain in the deposited layer. For example, plasma-enhanced chemical vapor deposition (PECVD) can provide nitride strain inducing liners with compressive internal strain. The stress state of the deposited nitride strain induction liner can be set by changing the deposition conditions to change the reaction rate in the deposition chamber, where the deposition conditions are SiH ₄ / N ₂ / He gas flow rate, pressure, RF power and electrodes. Includes gaps.

In another embodiment of the present invention, the SiGe compression strain induction well 60 may be formed after the pFET device 45 is formed and before the deposition of the compression strain induction liner 55. In the first processing step, recesses are formed in the portion of the biaxial tensile strained semiconductor layer 15 where the source and drain regions 13, 14 are located near the gate region 5. The recess can be formed by photolithography and etching techniques. Specifically speaking, an etch mask, preferably including a patterned photoresist, is formed over the surface of the entire structure except for the portion of the biaxial tensile strained semiconductor layer 15 near the gate region. The surface of the biaxial tensile strained semiconductor layer 15 over the source and drain regions 13, 14 is then subjected to a directional etching process from about 10 nm to about 300 nm from the surface where the gate region 15 is located. Concave to depth. In a preferred embodiment, the compressive strain induction well 60 may be positioned closer to the device channel by an etching process where the first directional (isotropic) etch followed by an omnidirectional (isotropic) etch, wherein the nondirectional etch is a sidewall spacer. Undercut (4) to provide a recess for eroding the device channel (12). By placing the compression strain induction well 60 closer to the device channel 12, the strain produced along the device channel 12 is increased.

In the next processing step, SiGe is grown epitaxially on the concave surface of the biaxial tensile strained semiconductor layer 15 over the source and drain regions 13, 14 to form a compressive strain induction well 60. Epitaxially grown SiGe is under internal compressive strain (also called intrinsic compressive strain), where the compressive strain is a large lattice dimension of epitaxially grown SiGe and a biaxial tensile strained semiconductor in which SiGe is epitaxially grown It is created by lattice mismatch between small lattice dimensions of the concave surface of layer 15. Compression strain induction well 60 produces a single axial compression strain in device channel 12 of pFET device 45 with a direction parallel to device channel 12.

In one embodiment, compression strain induction well 60 may be omitted if compression strain induction liner 55 is provided. In another embodiment of the present invention, compression strain induction liner 55 may be omitted if compression strain induction well 60 is provided.

In another embodiment of the present invention, a compressive strain induced isolation region 65 is formed that includes an intrinsic compressed dielectric filler, wherein the intrinsic compressed dielectric filler has a size of about 0.05 of the strain of the biaxial tensile strained semiconductor layer 15. To about 1% increase. The compressive strain induced isolation region 65 is formed by first etching the trench by a directional etching process such as reactive ion etching. After forming the trench, the trench is filled with a dielectric with intrinsic compressive strain, such as nitride or oxide, deposited by chemical vapor deposition. The deposition conditions for producing the compressive strain induced dielectric filler are similar to those described above for forming the compression strained dielectric liner 55.

Referring to FIG. 3, in another embodiment of the present invention, a pFET 75 having a single-axis compression strain in the device channel 12 of the substrate 10a is provided, where the compressed single-axis strain is a device channel ( 12) have a direction parallel to the length. In this embodiment, the single axial compression strain is produced by the combination of the biaxial compression strain semiconductor layer 26 and the compression strain induction liner 55.

Biaxial compressive strained semiconductor layer 26 is epitaxial silicon grown over carbon doped silicon (Si: C) strain inducing layer 18. Biaxial compression strain is derived from epitaxial silicon grown on a surface composed of a material whose lattice constant is smaller than the lattice constant of silicon. The lattice constant of carbon is smaller than the lattice constant of silicon. The epitaxial growth of Si on this Si: C strain inducing layer 18 creates a Si layer under biaxial compression strain, and the underlying Si: C strain inducing layer 18 is essentially unstrained, i.e. relaxed. The term "biaxial compression" means that compression strain is produced in a first direction parallel to the device channel 12 and in a second direction perpendicular to the device channel 12, wherein the magnitude of the strain in the first direction Is equal to the magnitude of the strain in the second direction.

The compression strain induction liner 55 is similar to the compression strain induction liner described above with reference to FIG. 2 and preferably comprises Si ₃ N ₄ . Referring again to FIG. 3, a compressive strain induction liner 55 is located over the gate region 5 and over the exposed surface of the biaxial compressive strain semiconductor layer 26 near the gate region 5.

Compression strain induction liner 55 creates a single axial compression strain on the device channel 12 in the range of about 100 MPa to about 2000 MPa, wherein the direction of the single axis strain is parallel to the length of the device channel 12. Do.

Before the compression strain induction liner 55 is formed, the device channel 12 is in a biaxial compression strain state because the magnitude of the strain produced in the direction perpendicular to the device channel 12 is such that the device channel 12 This is because it is equal to the magnitude of the strain created in a direction parallel to. By application of the compression strain induction liner 55 a single-axis strain is produced in a direction parallel to the device channel 12, where the magnitude of the compression strain perpendicular to the device channel 12 is applied to the device channel 12. Smaller than the size of parallel compression strain. Furthermore, the lattice constant in the pFET device 45 perpendicular to the device channel 12 is greater than the lattice constant along the device channel 12.

Referring again to FIG. 3, in another embodiment of the present invention, SiGe compression strain induction well 60 is located adjacent to device channel 12. Compression strain induction well 60 including intrinsic compression SiGe may be grown epitaxially over the recess of biaxial compression strain semiconductor layer 26, and SiGe compression strain induction well 60 described with reference to FIG. 2. Similar to Preferably, the SiGe compression strain induction well 60 erodes below the sidewall space 4 adjacent to the gate electrode 3 of the gate region 5.

Now, the method of forming the pFET 45 of the present invention will be described in more detail. In a first processing step, a laminate structure 10a is provided having a biaxial compressive strain semiconductor layer 26 over a Si: C strain inducing layer 18, wherein the Si: C strain inducing layer 18 is Si It is formed on the containing substrate 9. The Si-containing substrate 9 shown in FIG. 3 is similar to the Si-containing substrate 9 described above with reference to FIG. 1.

The Si: C strain inducing layer 18 is formed on the entire Si-containing substrate 9 using epitaxial growth treatment, wherein the C component of the Si: C strain inducing layer 18 is about 6 atomic percent. Less than%, preferably in the range of 0.5% to 4%. Typically, Si: C strain inducing layer 18 may be grown to a thickness ranging from about 10 nm to about 100 nm.

A biaxial compressive strain semiconductor layer 26 is then formed over the Si: C strain inducing layer 18. The biaxial compressive strained semiconductor layer 26 comprises an epitaxially grown Si containing material having a lattice dimension that is larger than the lattice dimension of the underlying Si: C strain inducing layer 18. Biaxial strained semiconductor layer 26 may be grown to a thickness below its critical thickness. Typically, biaxial compressive strained semiconductor layer 26 may be grown to a thickness in the range of about 10 nm to about 100 nm.

Alternatively, biaxial compressive strained semiconductor layer 26 may be formed directly on the insulating layer to provide an insulator directly strained silicon (SSDOI) substrate. In this embodiment, the compressive strained semiconductor layer 26 comprising epitaxial Si is grown on a handling wafer with a Si: C surface. The compressive strained semiconductor layer 26 is then bonded to the dielectric layer of the support substrate using a bonding method such as thermal bonding. After bonding, the handling wafer with Si: C surface is removed using smart cut and etching techniques, thereby providing a biaxial compressive strained semiconductor layer 26 bonded directly to the dielectric layer.

After the stacked structure 10a is formed, a pFET device 75 is formed over the biaxial compressive strained semiconductor layer 26 as described with reference to FIG.

Referring again to FIG. 3, in the next processing step, the compressive strain induction liner 55 is exposed surface of the biaxial compressive strain semiconductor layer 26 at least above and near the gate region 5. Deposited on top. The compression strain induction liner 55 is similar to the compression strain induction liner described above with reference to FIG. 2.

Preferably, the compressive strain induction liner 55 comprises a nitride such as Si ₃ N _4, and the processing conditions of the deposition process are selected to provide true compressive strain in the deposited layer. For example, plasma enhanced chemical vapor deposition (PECVD) can provide nitride stress inducing liners with compressive internal stress. The stress state of the deposited nitride stress inducing liner can be set by changing the deposition conditions to change the reaction rate in the deposition chamber, where the deposition conditions are SiH ₄ / N ₂ / He gas flow rate, pressure, RF power, and electrodes. Includes gaps.

Similar to the embodiment shown in FIG. 2, a compression strain induction well 60, preferably comprising intrinsic compression SiGe, and a compression strain induction isolation region 65, preferably comprising intrinsic compression dielectric filler, are shown in FIG. Can be formed. Preferably, the compressive strain induction well 60 erodes below the sidewall spacer 4 adjacent the gate electrode 3 in the gate region 5.

Referring to FIG. 4, in another embodiment of the present invention, on the same substrate 100, including the nFET device 20 of the present invention shown in FIG. 1 and the pFET device 45 of the present invention shown in FIG. CMOS structures are provided. Each nFET device 20 has a device channel 12 in which the lattice constant in a direction parallel to the nFET device channel 12 is greater than the lattice constant in a direction perpendicular to the nFET device channel 12, where the lattice constant difference Is induced by tensile uniaxial strain. Each pFET device 45 has a device channel 12 in which the lattice constant in the direction perpendicular to the pFET device channel 12 is greater than the lattice constant in the direction parallel to the pFET device channel 12, where the lattice constant difference Is induced by compression uniaxial strain. The CMOS structure shown in FIG. 4 is formed using the method described above for creating the nFET device 20 and the pFET device 45.

More specifically, as described above with reference to FIG. 1, a stacked structure 100 is first provided that includes a biaxial tensile strained semiconductor layer 15 formed over a SiGe strain inducing layer 17. An nFET device 20 is then formed in the nFET device region 120 of the substrate 100 and the pFET device 45 is formed in the pFET device region 140 of the substrate 100, at which time the nFET device Region 120 and pFET device region 140 are separated by isolation region 70. Similar to the previous embodiment, biaxial strain generated within pFET device region 140 and nFET device region 120 may be increased by filling isolation region 70 with intrinsic compression or intrinsic tensile dielectric filler.

The pFET device region 140 and nFET device region 120 are then selectively processed using a conventional block mask. For example, a first block mask is formed over the pFET device region 140 and the nFET device region 120 remains exposed. Next, nFET device region 120 is processed to produce nFET device 20, tensile strain inducing liner 25 and tensile strain inducing well 30 as described above with reference to FIG. 1. The nFET device region 120 and the pFET device region 140 are separated by an isolation region 70, where the intrinsic tensile or intrinsic compressed dielectric filler is responsible for biaxial strain in the nFET or pFET device regions 120, 140. Can be increased.

Next, the first block mask is removed and a second block mask is formed over the nFET device region 120 and the pFET device region 140 is left exposed. The pFET device region 140 is then processed to produce the pFET device 45, the compressive strain induction liner 55 and the tensile strain induction well 60 as described above with reference to FIG. 2. Then, the second block mask is removed.

Referring to FIG. 5, in another embodiment of the present invention, a CMOS structure is provided that includes an nFET device 20 shown in FIG. 1 and a pFET device 75 shown in FIG. 3 on the same substrate. The CMOS structure shown in FIG. 5 provides an improvement in the pFET drive current as well as an additional increase in nFET drive current in the same substrate 105.

The CMOS structure shown in FIG. 5 is formed using the above-described method for creating an nFET device 20 as shown in FIG. 1 and a pFET device 75 as shown in FIG. 3, where nFET A block mask is used to selectively process the portion of the CMOS structure in which device 20 and pFET device 75 are formed.

First, at least a biaxial compressive strained semiconductor layer 26 over the Si: C strain inducing layer 18 in the pFET device region 140 and biaxial tension over the SiGe strain inducing layer 17 in the nFET device region 120. A strained Si substrate 105 with a strained semiconductor layer 15 is provided. Strained Si substrate 105 may be formed by deposition, epitaxial growth, photolithography and etching. A more detailed description relating to the formation of biaxially strained Si substrates 105 comprising a compressive strained semiconductor layer 26 and a tensile strained semiconductor layer 15 is referred to as 'Strained Si on Multiple Materials for Bulk or SOI Substrates' ( Strained Si on Multiple Materials for Bulk or SOI Substrate) is disclosed in US Patent Application No. 10 / 859,736, filed June 3, 2004.

In a next processing step, a first block mask is formed over the pFET device region 140 and the biaxial tensile strained semiconductor layer 15 of the nFET device region 120 is left exposed. The biaxial tensile strained semiconductor layer 15 is then processed to provide an nFET device 20 that includes a tensile strain inducing liner 25 and a tensile strain inducing well 30, wherein the tensile uniaxial strain Is generated in nFET device channel 12. The nFET device 20 is processed according to the method described above with reference to FIG.

After the nFET device 20 is formed, the first block mask is peeled off to expose the biaxial compressive strained semiconductor layer 26 and the second block mask is located in the biaxial tensile strained semiconductor layer 15. 20 is formed above. The biaxial compressive strain semiconductor layer 26 is then processed to provide a pFET device 75 including a compressive strain inducing liner 55 and a compressive strain inducing well 60, where a single axis compressive strain Is generated in device channel 12 of pFET device 75. The pFET device 75 is processed according to the method described above with reference to FIG.

Referring to FIG. 6, in another embodiment of the present invention, an n-type field effect transistor (nFET) 20 having a single-axis tensile strain in a portion of the device channel 12 of the relaxed substrate 85 is provided, where The monoaxial tensile strain is in a direction parallel to the longitudinal direction of the device channel 12. Uniaxial tensile strain along device channel 12 of nFET device 20 is created by a combination of tensile strain inducing liner 25 and tensile strain inducing well 30.

The term "relaxing substrate" means a substrate having no internal strain, where a grid in a direction parallel to the channel plane (x direction), a direction perpendicular to the channel plane (y direction) and a channel plane outward direction (z direction) The dimensions are the same. Relaxed substrate 85 is a non-limiting example as Si, strained Si, Si _{1 - y} C _y, Si _{1 -x- y} Ge _x C _y, Si _{1 - x} Ge _x, Si alloys, Ge, Ge alloys, And any semiconductor material, including GaAs, InAs, InP, as well as other Group III-V and II-VI semiconductors. Mitigating substrate 85 may also be an insulator silicon (SOI) substrate or an insulator SiGe (SGOI) substrate. The thickness of the relaxed substrate 85 is not critical to the present invention. Preferably, the relaxed substrate 85 comprises a Si containing material.

Tensile strain induction liner 25 preferably comprises Si ₃ N ₄ and is located above the gate region 5 and above the exposed surface of the relaxed substrate 85 in the vicinity of the gate region 5. Tensile strain induced liners 25 may be formed of nitrides, oxides, doped oxides such as boron phosphate silicate glass, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , HfSiO, other dielectric materials common in semiconductor processing, or any combination thereof. It may include. Tensile strain induction liner 25 may have a thickness in the range of about 10 nm to about 500 nm, preferably about 50 nm. Tensile strain induced liner 25 may be deposited by plasma enhanced chemical vapor deposition (PECVD) or rapid thermal chemical vapor deposition (RTCVD).

Preferably, the tensile strain induction liner 25 comprises a nitride, such as Si ₃ N _4, and the processing conditions of the deposition process are selected to provide true tensile strain in the deposited layer. For example, plasma enhanced chemical vapor deposition (PECVD) can provide nitride stress inducing liners with intrinsic tensile strain. The stress state of the nitride stress inducing liner deposited by PECVD can be controlled by changing the deposition conditions to change the reaction rate in the deposition chamber. More specifically, the stress state of the deposited nitride strain induction liner can be set by changing deposition conditions such as SiH ₄ / N ₂ / He gas flow rate, pressure, RF power, and electrode gap. In another example, rapid thermal chemical vapor deposition (RTCVD) can provide a nitride tensile strain inducing liner 25 with an internal tensile strain. The size of the internal tensile strain produced in the nitride tensile strain induced liner 25 deposited by RTCVD can be adjusted by changing the deposition conditions. More specifically, the size of the tensile strain in the nitride tensile strain induction liner 25 may be set by changing deposition conditions such as precursor composition, precursor flow rate and temperature.

Tensile strain induction wells 30 are located near the device channel 12 of the respective source and drain regions 13, 14. The tensile strain induction well 30 may include carbon doped silicon (Si: C) or carbon doped silicon germanium (SiGe: C). Tensile strain induction wells 30 including intrinsic tensile Si: C may be grown epitaxially over the recesses of the relaxed substrate 85.

Tensile strain induction well 30, along with tensile strain induction liner 25, creates a monoaxial tensile strain in a direction parallel to nFET device channel 12 within device channel 12. The combination of tensile strain induced liner 25 and strain induced well 30 produces a single axial compressive strain in the device channel 12 in the range of about 100 MPa to about 2000 MPa, where the direction of the single axial strain is It is parallel to the length of the channel 12. The structure forming method shown in FIG. 1 provides the structure shown in FIG. 6 except that the structure forming method shown in FIG. 6 includes a relaxed substrate 85 rather than the strained substrate of the previous embodiment. Can be applied for

Referring to FIG. 7, in another embodiment of the present invention, a p-type field effect transistor (pFET) 45 having a single-axis compression strain in the portion of the device channel 12 of the relaxation substrate 85 is provided, where The single axial compression strain is in a direction parallel to the length of the device channel 12. Compression strain induction liner 55, along with compression strain induction well 60, produces a compressive uniaxial strain along the device channel 12 portion of the relaxed substrate 85, where the uniaxial compression strain is parallel to the device channel. Provides increased carrier mobility in the pFET device 45.

The relaxed substrate 85 is similar to the relaxed substrate shown in FIG. 6. Applying the compression strain induction liner 55 together with the compression strain induction well 60 produces a single axial compression strain in a direction parallel to the device channel 12. Therefore, the lattice constant in pFET device 45 across device channel 12 is greater than the lattice constant along device channel 12.

Compression strain induction liner 55 may be formed of nitride, oxide, doped oxide, such as boron phosphate silicate glass, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , HfSiO, other dielectric materials common in semiconductor processing, or any combination thereof. It may include. Compression strain induction liner 55 may have a thickness in the range of about 10 nm to about 100 nm, preferably about 50 nm. Compression strain induction liner 55 may be deposited by plasma enhanced chemical vapor deposition (PECVD).

Preferably, the compressive strain induction liner 55 comprises a nitride such as Si ₃ N _4, and the processing conditions of the deposition process are selected to provide intrinsic tensile strain in the deposited layer. For example, plasma enhanced chemical vapor deposition (PECVD) can provide nitride stress inducing liners with compressive internal stress. The stress state of the deposited nitride stress inducing liner can be set by changing the deposition conditions to change the reaction rate in the deposition chamber, where the deposition conditions are SiH ₄ / N ₂ / He gas flow rate, pressure, RF power and electrodes. Includes gaps.

Compression strain induction well 60 is located adjacent to device channel 12 in respective source and drain regions 13, 14. Compression strain induction well 60 may comprise SiGe. Compression strain induction wells 60, including intrinsic compression SiGe, may be epitaxially grown over recesses in the relaxed substrate 85.

The combination of compression strain induction liner 55 and compression strain induction well 60 produces a single axial compression strain in the range of about 100 MPa to about 2000 MPa on device channel 12, where the direction of the uniaxial compression strain Is parallel to the length of the device channel 12. The structure forming method shown in FIG. 2 may be applied to provide the structure shown in FIG. 7 except that the structure forming method shown in FIG. 7 includes a relaxation substrate 85.

Referring to FIG. 8, in another embodiment of the present invention, two-axis strain with at least one field effect transistor (FET) 151 having a single-axis strain along the device channel 12 of the relaxed substrate region 150. A CMOS structure is provided that includes at least one FET 149 with a single axis strain along the device channel 12 of the substrate region 160.

Uniaxial strain in the relaxed substrate region 150 is provided by a combination of strain induced liner 152 over FET 151 and strain induced well 153 near FET 151. Strain induction liner 152 and strain induction well 153 may be used to induce tensile strain on device channel 12 of relaxed semiconductor surface 85 as described above with reference to FIG. 6, or from above with reference to FIG. 7. As described, it may be treated to induce compressive strain on device channel 12 of relaxed semiconductor surface 85.

Uniaxial strain in biaxial strain substrate region 160 is provided by a combination of strain guide liner 161 and / or strain guide well 154 and strain guide layer 155 under device channel 12. Strain induction layer 155 in biaxial strained substrate region 160 includes carbon doped silicon (Si: C) or carbon doped silicon germanium (SiGe: C) as described above with reference to FIG. A strained semiconductor surface can be provided or a biaxial tensile strained semiconductor surface can be provided as described above with reference to FIGS. 1 and 2, including silicon germanium (SiGe). Isolation regions 170, including intrinsic tensile strains or intrinsic compressive strained dielectric filler, can increase the biaxial strain generated within biaxial strained substrate region 160.

Strain induction well 154 in biaxial strained substrate region 160 includes silicon germanium (SiGe), and as described above with reference to FIGS. 2 and 3, the device of biaxial strained substrate region 160. Compressed uniaxial strain can be provided in the channel 12. Strain induction well 154 also includes carbon doped silicon (Si: C) or carbon doped silicon germanium (SiGe: C), as described above with reference to FIG. 1, of biaxial strained substrate region 160. Tensile monoaxial strains can be provided in the device channel 12. Strain induction liner 161 is a biaxial strained substrate region to provide tensile or compressive uniaxial strain to device channel 12 of biaxial strained substrate region 160 as described above with reference to FIGS. Over FET 149 of 160.

The CMOS structure shown in FIG. 8 may be formed using a method similar to the method used to provide the CMOS structure shown in FIG. 7 except that no strain inducing layer is present in the relaxed substrate region 150. . Alternatively, the strain inducing layer may be present in the relaxed substrate region 150 as long as the semiconductor surface over the strain inducing layer is grown to a thickness above its critical thickness.

The following examples are intended to further illustrate the invention and illustrate the advantages that may arise therefrom. These examples are for illustrative purposes only, and thus the invention is not limited to the examples described below.

Example 1

Formation of Compressed or Tensile Dielectric Capping Layer on Biaxial Strained SGOI Substrates

In this example, a dielectric capping layer (compression or tensile strain inducing layer) was used to improve the drive current by introducing single axial strain along the FET channel. When the dielectric capping layer was deposited on the SGOI FET, the grating structure was distorted in response to the combination of biaxial tensile strain and smaller uniaxial tensile or compressive stress. 9A schematically illustrates biaxial tensile strained silicon, wherein the longitudinal lattice dimension (x direction, parallel to the channel) is the transverse lattice dimension (y direction, in the same plane and in the device channel). Upright) and rectangular grid dimensions (z direction, outside the channel plane). FIG. 9B illustrates the lattice symmetry of the biaxial tensile strained silicon substrate shown in FIG. 9A, wherein the overlapping uniaxial tensile strain along the channel results in a longitudinal lattice dimension greater than the transverse lattice dimension and the rectangular lattice dimension . FIG. 9C illustrates the lattice symmetry of the biaxial tensile strained silicon substrate shown in FIG. 9A, wherein the overlapping uniaxial compressive strain along the channel results in a larger transverse lattice dimension than the longitudinal lattice dimension and the rectangular lattice dimension .

The devices were fabricated with a stress induced dielectric capping layer (strain induced liner) on a 300 mm diameter thermally mixed ultra thin SGOI substrate. The substrates showed excellent uniformity in Ge mole fraction [Ge] and the transverse thickness of the wafer (Std. Dev of [Ge] was 0.18% across a 300 mm diameter substrate and Std. Dev of substrate thickness was 300 mm). 0.85 nm across the diameter substrate). FETs (n-type and p-type) were provided on a substrate having a 55 nm channel length. A tensile or compressive dielectric capping layer (strain induced liner) was then formed over the FET.

FIG. 10 shows an nFET device 200 having a tensile longitudinal strain (parallel to the device channel) overlaid with a tensile strain induced dielectric capping layer and a compressed longitudinal strain (parallel to the device channel) with a compressive strain induced dielectric capping layer overlaid. Shows the I _on versus I _off measurement results for nFET device 250 with < RTI ID = 0.0 > A 1.0 V supply voltage was applied to the nFET device, resulting in I _on versus I _off data shown in FIG. 10. Uniaxial tension further improved the drive current of the strained Si nFET device. FIG. 10 shows that by changing the dielectric capping layer from the compressive strain induced dielectric capping layer to the tensile strain induced dielectric capping layer, the SGOI nFET can achieve a drive current improvement of about 10%.

Referring to FIG. 11, a pFET device 300 having a tensile longitudinal strain (parallel to the device channel) overlaid with a tensile strain induced dielectric capping layer and a compressed longitudinal strain (device channel with overlapped compressive strain induced dielectric capping layer) I _on versus I _off for the pFET device 350 with the A supply voltage of 0.9 V was applied to the pFET device, resulting in I _on to I _off data shown in FIG. 11. Single-axis compression further improves the drive current of strained Si pFET devices. FIG. 11 shows that the SGOI pFET can achieve about 5% drive current improvement by changing the dielectric capping layer from the tensile strain induced dielectric capping layer to the compressive strain induced dielectric capping layer.

While the present invention has been particularly shown and described with respect to preferred embodiments, it will be understood by those skilled in the art that various changes in form and details of the invention can be made without departing from the spirit and scope of the invention. Therefore, the invention is not limited to the forms and details shown and described herein, but only by the appended claims.

Claims (40)

In a semiconductor device, A substrate comprising a strained semiconductor layer over a strain induced layer, wherein the strain induced layer produces biaxial strain in the strained semiconductor layer; At least one gate region comprising a gate conductor over a device channel portion of the strained semiconductor layer, wherein the device channel portion separates a source and drain region near the at least one gate conductor; A strain induced liner positioned over the at least one gate region, wherein the strain induced liner is to create a uniaxial strain in a device channel portion of the strained semiconductor layer below the at least one gate region. . The semiconductor device of claim 1, wherein the strain inducing liner comprises an oxide, a doped oxide, a nitride, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , HfSiO, or a combination thereof. The strain-inducing layer of claim 2, wherein the strain-inducing layer comprises SiGe having Ge present at a concentration in the range of about 5% to about 50% by weight of atomic weight, wherein the biaxial strain in the strained semiconductor layer is tensioned. And wherein said strain inducing liner is in tension and said strain inducing liner provides said uniaxial strain in tension in a direction parallel to said device channel with said strain induction layer. The strain-inducing layer of claim 2, wherein the strain inducing layer comprises silicon doped with carbon, wherein the carbon is present at an atomic weight percent in a concentration ranging from about 1% to about 6% and in the strained semiconductor layer. Wherein the strain-inducing liner is in a compressed state, and the strain-inducing liner, together with the strain-inducing layer, provides the single-axis strain in a compressed state in a direction parallel to the device channel. 4. The semiconductor device of claim 3, further comprising an isolation region comprising an intrinsic tensile strained dielectric material, wherein the intrinsic tensile strained dielectric material increases the biaxial strain of the strained semiconductor layer in tension. . 5. The semiconductor device of claim 4, further comprising an isolation region comprising an intrinsic compressive strained dielectric material, wherein the intrinsic compressive strained dielectric material increases the biaxial strain of the strained semiconductor layer in a compressed state. . In a semiconductor device, A substrate comprising a strained semiconductor layer over a strain induced layer, wherein the strain induced layer produces biaxial strain in the strained semiconductor layer; At least one gate region comprising a gate conductor over a device channel portion of the strained semiconductor layer of the substrate, the device channel separating a source and a drain region; And a strain induced well near the at least one gate region, wherein the strain induced well near the at least one gate region creates a single axial strain in a device channel portion of the strained semiconductor layer. 8. The strain inducing structure of claim 7, wherein the strain inducing layer comprises SiGe having Ge present in a concentration ranging from about 5% to about 50%, producing the biaxial strain in a tensile state in the strained semiconductor layer, and The strain inducing well comprising the doped silicon or carbon doped silicon germanium is in a compressed state, and the strain inducing well, together with the strain inducing layer, removes the uniaxial strain in tension in a direction parallel to the device channel. It provides a semiconductor device. 8. The strain-inducing layer of claim 7, wherein the strain inducing layer comprises silicon doped with carbon, the carbon being present at a concentration ranging from about 1% to about 6% and compressing the biaxial strain in the strained semiconductor layer. And the strain inducing well comprises SiGe, the strain inducing well together with the strain inducing layer to provide the single axial strain in a compressed state in a direction parallel to the device channel. The semiconductor device of claim 8, further comprising an isolation region comprising an intrinsic tensile strained dielectric material, wherein the intrinsic tensile strained dielectric material increases the biaxial strain of the strained semiconductor layer in tension. . 10. The semiconductor device of claim 9, further comprising an isolation region comprising an intrinsic compressive strained dielectric material, wherein the intrinsic compressive strained dielectric material increases the biaxial strain of the strained semiconductor layer in a compressed state. . In a semiconductor device, A substrate comprising a compressive strained semiconductor surface and a tensile strained semiconductor surface, wherein the compressive strained semiconductor surface and the tensile strained semiconductor surface are biaxially strained; At least one gate region over said biaxial compressive strained semiconductor layer comprising a gate conductor over a device channel portion of said compressive strained semiconductor layer of said substrate; At least one gate region over said tensile strained semiconductor layer comprising a gate conductor over a device channel portion of said tensile strained semiconductor layer of said substrate; A compressive strain inducing liner over the at least one gate region on the compressive strain semiconductor surface—the compressive strain inducing liner is compressed in the compressive strain semiconductor layer in a direction parallel to the device channel portion of the compressive strain semiconductor surface To produce an axial strain; Tensile strain inducing liner over the at least one gate region on the tensile strain semiconductor layer—the tensile strain inducing liner is tensile in the tensile strain semiconductor layer in a direction parallel to the device channel portion of the tensile strain semiconductor layer To produce a uniaxial strain. The semiconductor device of claim 12, wherein the compressive strain inducing liner and the tensile strain inducing liner comprise oxide, doped oxide, nitride, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , HfSiO, or a combination thereof. 15. The method of claim 13, wherein the tensile strained semiconductor layer of the substrate is over a compressive strain inducing layer comprising SiGe with Ge present at a concentration in the range of about 5% to about 30% by weight of atomic weight of the substrate. Wherein the compressive strained semiconductor layer is over a tensile strain inducing layer comprising carbon doped silicon present in a concentration ranging from about 0.5% to about 6%. 13. The method of claim 12, wherein the isolation region near the compressive strained semiconductor surface including intrinsic compressive strained dielectric material—an isolation region near the compressive strained semiconductor surface increases biaxially the compressive strain of the compressive strained semiconductor surface. To; An isolation region near the biaxial tensile strained semiconductor surface including an intrinsic compressive strained dielectric material, wherein the isolation region near the biaxial tensile strained semiconductor surface is to increase the biaxial strain in a compressed state. Semiconductor device. In a semiconductor device, A substrate comprising a compressive strained semiconductor surface and a tensile strained semiconductor surface, wherein the compressive strained semiconductor surface and the tensile strained semiconductor surface are biaxially strained; At least one gate region over said compressive strained semiconductor layer comprising a gate conductor over said device channel portion of said compressive strained semiconductor layer of said substrate; At least one gate region over said biaxial tensile strained semiconductor layer comprising a gate conductor over a device channel portion of said biaxial tensile strained semiconductor layer of said substrate; Compressive strain induced wells near the at least one gate region on the biaxial compressive strain semiconductor surface—the compressive strain induced wells produce a compressive monoaxial strain in the compressive strain semiconductor layer, the compressive monoaxial strain being compressed In a direction parallel to the device channel portion of the strained semiconductor surface; Tensile strain induced wells near the at least one gate region on the tensile strained semiconductor layer—The tensile strain induced wells produce a tensile uniaxial strain of the tensile strained semiconductor layer, and the tensile monoaxial strain is the tensile strain And in a direction parallel to the device channel portion of the semiconductor layer. 17. The method of claim 16, wherein the tensile strained semiconductor layer of the substrate is over a compressive strain inducing layer comprising SiGe with Ge present at a concentration in the range of about 5% to about 30% in atomic weight percent, Wherein the compressive strained semiconductor layer is over a tensile strain inducing layer comprising carbon doped silicon present in a concentration ranging from about 0.5% to about 6%. 18. The semiconductor device of claim 17, wherein the compressive strain inducing well comprises SiGe, and the tensile strain inducing well comprises carbon doped silicon or carbon doped silicon germanium. 19. The isolation region of claim 18, wherein said isolation region near said compressive strained semiconductor surface comprises an intrinsic tensile strained dielectric material, said isolation region near said compression strained semiconductor surface increasing tensile biaxial strain in tension. ; And an isolation region near the tensile strained semiconductor surface including an intrinsic compressive strained dielectric material, wherein the isolation region near the tensile strained semiconductor surface is to increase the biaxial strain in a tensile state. In a semiconductor device, A semiconductor substrate; At least one gate region comprising a gate conductor over a device channel portion of the semiconductor substrate, the device channel portion separating a source and a drain region; A strain induction well near said at least one gate region; And a strain induced liner positioned in the at least one gate region, wherein the strain induced liner and the strain induced well are in the semiconductor substrate in a direction parallel to the device channel. The semiconductor device of claim 20, wherein the strain inducing liner comprises an oxide, a doped oxide, a nitride, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , HfSiO. 22. The strain inducing well of claim 21 wherein the semiconductor substrate comprises a biaxial tensile strain induced by a lower strain inducing layer comprising SiGe with Ge present at a concentration ranging from about 5% to about 50%, And silver-doped silicon or carbon-doped silicon germanium, wherein the uniaxial strain is in tension. The semiconductor substrate of claim 21, wherein the semiconductor substrate comprises a biaxial compressive strain induced by a lower strain induced liner comprising silicon doped with carbon, the carbon being present at a concentration ranging from about 1% to about 6%. Wherein the strain inducing well comprises SiGe and the uniaxial strain is in a compressed state. The method of claim 20, wherein the semiconductor substrate is Si, strained Si, Si _1-y C _y , Si _1-xy Ge _x C _y , Si _1-x Ge _x , Si alloy, Ge, Ge alloy, GaAs, InAs And a relaxed crystal structure comprising an InP, an insulator silicon (SOI) substrate, or an insulator SiGe (SGOI) substrate. 25. The strain inducing liner of claim 24 wherein the strain inducing liner and the strain inducing well have an internal tensile strain, the strain inducing well comprises carbon doped silicon or carbon doped silicon germanium, and the strain induction liner comprises And a tensile uniaxial strain parallel to the device channel portion of the semiconductor substrate with strain induced wells. 25. The semiconductor device of claim 24, wherein the strain induced liner and the strain induced wells comprise internal compressive strain, the strain induced wells comprise SiGe, and the uniaxial strain is in a compressed state. In a semiconductor device, A substrate comprising a first device region having a biaxial strained semiconductor surface and a second device region having a relaxed semiconductor surface; At least one gate region on the biaxial strained semiconductor surface having a gate conductor over a device channel portion of the biaxial strained semiconductor surface; At least one gate region on said relaxed semiconductor surface having a gate conductor over a device channel portion of said relaxed semiconductor surface; A strain induced liner over the at least one gate region over the relaxed semiconductor surface and over the at least one gate region over the biaxial strained semiconductor surface; Strain induced wells near the at least one gate region on the relaxed semiconductor surface—the strain induced wells together with the strain induced liner in a direction parallel to the device channel portion of the relaxed semiconductor surface in the second device region. Creating an axial strain, wherein the biaxial strained semiconductor surface is to produce a monoaxial strain in a direction parallel to the device channel portion of the biaxial semiconductor surface in the first device region with the strain inducing liner. A semiconductor device comprising. 28. The semiconductor device of claim 27, wherein the strain induced wells are in the first device region and the second device region. In a semiconductor device, A substrate comprising a first device region having a biaxial strained semiconductor surface and a second device region having a relaxed semiconductor surface; At least one gate region on the biaxial strained semiconductor surface having a gate conductor over a device channel portion of the biaxial strained semiconductor surface; At least one gate region on said relaxed semiconductor surface having a gate conductor over a device channel portion of said relaxed semiconductor surface; Strain induced wells near the at least one gate region on the relaxed semiconductor surface and near the at least one gate region on the biaxial strained semiconductor surface; Strain induced liner over the at least one gate region over the relaxed semiconductor surface—the strain induced liner is united with the strain induced well in a direction parallel to the device channel portion of the relaxed semiconductor surface in the second device region. Creating an axial strain, wherein the biaxial strained semiconductor surface is to produce a uniaxial strain in a direction parallel to the device channel portion of the biaxial semiconductor surface in the first device region with the strain inducing well. A semiconductor device comprising. In the method of manufacturing a semiconductor structure, Providing a substrate having at least one strained semiconductor surface, the at least one strained semiconductor surface having internal strains of equal magnitude in a first direction and a second direction, the first direction being within the same plane Perpendicular to the second direction; Creating at least one semiconductor device on the at least one strained semiconductor surface, the at least one semiconductor device including a gate conductor over a device channel portion of the semiconductor surface, the device channel defining a source and a drain region; To separate; Forming a strain induced liner over the at least one gate region—the strain induced liner creates a uniaxial strain in a direction parallel to the device channel within the at least one semiconductor surface, the strain induced liner Wherein the size is different from the second direction. 31. The method of claim 30, wherein providing the substrate with the at least one strained semiconductor layer comprises providing a tensile strained semiconductor layer epitaxially grown over a SiGe layer, wherein the SiGe layer is about Has Ge present at a concentration ranging from 5% to about 30%; Wherein the strain inducing liner comprises an oxide, nitride, doped oxide, or combination thereof deposited using chemical vapor deposition under conditions that produce compressive or tensile stresses. 31. The method of claim 30, wherein providing the substrate with the at least one strained semiconductor layer comprises providing a compressive strained semiconductor layer epitaxially grown over a carbon doped silicon layer, The carbon doped silicon layer has carbon present at a concentration ranging from about 0.5% to about 6%; Wherein the strain inducing liner comprises an oxide, nitride, doped oxide, or combination thereof deposited using chemical vapor deposition under conditions that produce compressive or tensile stresses. In the method of manufacturing a semiconductor structure, Providing a substrate having at least one strained semiconductor surface, the at least one strained semiconductor surface having internal strains of equal magnitude in a first direction and a second direction, the first direction being within the same plane Perpendicular to the second direction; Creating at least one semiconductor device on the at least one strained semiconductor surface, the at least one semiconductor device including a gate conductor over a device channel portion of the semiconductor surface, the device channel defining a source and a drain region; To separate; Forming a strain induced well near the at least one gate region—the strain induced well generates a uniaxial strain in a direction parallel to the device channel within the at least one strained semiconductor surface, Wherein the size of the strain is different from the second direction. 34. The method of claim 33, wherein forming the strain inducing well comprises etching a surface of the strained growth semiconductor surface to provide a recess and epitaxially growing a silicon-containing strain induced material in the recess. And silicon doped with carbon in a concentration ranging from about 0.5% to 6% in the recess provides a tensile strain induction well and in which the Ge is present in a concentration ranging from about 5% to about 50%. Germanium is to provide a compression strain induction well. 35. The method of claim 34, wherein forming the etch includes an etching process including directional and omnidirectional etching, wherein the recess undercuts the spacer near the at least one gate region. In the method of manufacturing a semiconductor structure, Providing a mitigating substrate; Creating at least one semiconductor device over the relaxed substrate, the at least one semiconductor device including a gate conductor over a device channel portion of the semiconductor surface, the device channel separating a source and a drain region; Forming a strain induced well near said device channel; Forming a strain induced liner over the at least one gate region, wherein the strain induced liner and the strain induced wells provide uniaxial strain in the device channel. In the method of manufacturing a semiconductor structure, Providing a substrate having a first device region and a second device region; Creating at least one semiconductor device over a device channel portion of the substrate in the first device region and the second device region; Generating uniaxial strain in the first device region and in the second device region in a direction parallel to the device channels of the first device region and the second device region. 38. The method of claim 37, wherein the single axial strain of the first device region and the second device region is in a tensioned or compressed state, and the single axial strain of the first device region is the same as the second device region or Another method for producing a semiconductor structure. The method of claim 38, wherein generating a single axis strain in the first device region and the second device region comprises: A first combination of a biaxial strained semiconductor surface below the at least one semiconductor device and a strain induction liner above the at least one semiconductor device, the biaxial strained semiconductor surface below the at least one semiconductor device and the at least one A second combination comprising a strain induction well near a semiconductor device of said biaxial strain semiconductor surface below said at least one semiconductor device, a strain induction liner above said at least one semiconductor device and a vicinity of said at least one semiconductor device A third combination including strain induced wells, or a relaxation substrate under the at least one semiconductor device, the strain induction liner above the at least one semiconductor device on the relief surface and the strain induction wells near the at least one semiconductor device. Including the fourth combination Processing the first device region and the second device region to provide a combination of strain inducing structures, wherein the combination of the strain inducing structure in the first device region comprises inducing the strain in the second device region. A method of making a semiconductor structure that is the same as or different from the combination of structures. 38. The semiconductor structure of claim 37 wherein the uniaxial strain of the first device region is in a tension state and includes at least one nFET and the second device region is in a compressed state and includes at least one pFET. Manufacturing method.

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