KR20070030230A - Integrated circiut device and signal transmission system - Google Patents

Abstract

Some interface signals are selected from among the signals of a plurality of different parallel interfaces and then multiplexed onto a serial connection. A transmitter of a signal transmission system includes an interface signal selector (IFS) and a transfer programmer (TP) that provides a control signal to instruct a selection of the interfaces and that realizes a multiplexing of the parallel data in such a manner that satisfies the specification of the parallel interfaces. Moreover, the transfer programmer (TP) can changes, as occasion requires, the control signal as to which interfaces to select, thereby dynamically changing the interface signals to be multiplexed, while multiplexing them onto the serial connection. ® KIPO & WIPO 2007

Description

Integrated circuit device and signal transmission system {INTEGRATED CIRCIUT DEVICE AND SIGNAL TRANSMISSION SYSTEM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device for serializing high-speed transmission of parallel data of a plurality of parallel interfaces and a signal transmission system equipped with such an integrated circuit device.

In general, in many systems, it is necessary to send and receive signals between the components constituting the system and various devices, such as data to be processed, various control signals, and the like. For this purpose, it is widely used to connect semiconductor chips or components in accordance with a method of transmitting and receiving a signal called an interface in which transmission frequencies, bit widths of data signals, control signal configurations, transmission / reception protocols, and the like are defined. As interfaces for exchanging such signals, there are an interface having a plurality of bit widths of data signals (called "parallel interfaces") and an interface having a single bit width (called "serial interfaces"). In addition, the signal transmission and reception of a single bit width here does not require one signal player, but rather a signal having a different phase (for example, complementary phase between normal phase and reverse phase). This includes the case where the signal is transmitted as an enemy signal. Then, conventionally, in order to reduce the number of signal lines, the parallel / serial which serializes the signals of the parallel interface, transfers them between devices, components, and semiconductor chips to the serial interface and restores them to parallel signals once again. There are techniques for conversion and serial / parallel conversion. As such a technique, "Digital Circuit", 齊藤 忠 夫 著, Korona Co., Ltd., 57, p108-p110 (prior art 1), Japanese Patent Laid-Open No. 6-103025 (prior art 2), Japanese Patent Laid-Open No. 6-96017 ( Prior art 3) and Unexamined-Japanese-Patent No. 10-22838 (prior art 4) are mentioned.

The technique disclosed in (Prior Art 1) discloses converting parallel data belonging to a single interface into a serial signal by a transmitter and transmitting the same, and restoring the parallel data to the receiver once again for use. Since the serial connection is used for sending and receiving signals, the number of wirings can be reduced. This reduces the number of wires on the cable or printed circuit board, which can reduce the size of the equipment and reduce the system cost. However, in the case where a plurality of different parallel interfaces exist, serialization and parallelization for signals of the plurality of parallel interfaces have not been studied. Here, the plurality of different interfaces means that there are a plurality of interfaces having different transmission frequencies, bit widths of data signals, control signal configurations, and transmission / reception protocols. The same problem exists with respect to the parallel / serial conversion and the serial / parallel conversion disclosed in (Prior Art 2). The technique disclosed in (Prior Art 3) multiplexes signals between a plurality of devices, but serial connection is used as a bus connection of a plurality of devices (three devices in FIG. 1). Here, a technique has been exhibited in which a plurality of devices do not transmit signals at the same time by allocating in advance in advance which devices send signals over a serial connection. In this technique as well, serialization of a plurality of different interfaces is not considered, and furthermore, since the premise of bus connection is assumed, high speed (high frequency) is affected by the signal reflection at the branch of the signal line. It may also be a problem that it is difficult to send and receive signals. The inventors have found that a large number of integrated circuits are mounted in one system, and that they are connected by a large number of parallel signals may hinder the miniaturization and cost reduction of the system. My thoughts have gone mad. Therefore, the idea is driven to the configuration of the present invention to selectively serially transfer a plurality of parallel interfaces. In addition, when a plurality of parallel interfaces are selected and multiplexed and transmitted, a system configuration effectively connected to a network is provided. On the other hand, in the technique disclosed in (Prior Art 4), a communication unit as shown in FIGS. 5 to 8 of FIG. 1 combines and serializes a plurality of different interfaces, and then transfers them between devices to parallelize them. An example is to restore it. Such a communication unit is merely a static serialization of a predetermined parallel signal of a plurality of devices, and it is conceivable to selectively serialize or dynamically change the selection from interface signals of a plurality of devices. none. Brief descriptions of representative ones of the disclosed inventions are as follows. An integrated circuit device in which parallel data of a plurality of parallel interfaces is multiplexed into serial data, and a signal transmitting circuit for outputting the data stored in the storage device to the transmission path connected to the integrated circuit device by one bit, and the plurality of parallel devices. The parallel data of the interface is configured to be input, and has an interface signal selector for outputting parallel data of the selected parallel interface to the storage device, and a transfer programr for issuing a control signal for notifying the interface signal selector of the parallel interface. do. In addition, the chip receiving the serial signal has a first register relating to the frame structure of the serial transmission, and extracts the corresponding data according to the first register. The chip which transmits the serial signal has a second register relating to the frame structure of the serial transmission, and generates serial data from the corresponding data in accordance with the second register. This register can also be changed. In addition, the transmission based on the parallel interface is used for distinguishing whether to transfer the data based on the parallel interface, the transmission frequency and the transmission band as parallel data, or serialize the serial transmission. Hereinafter, the integrated circuit device and the signal transmission system according to the present invention will be described in detail by using an embodiment.

1 is a diagram showing the configuration of a signal transmitter in the signal transmission system of the present invention.

Fig. 2 is a diagram showing the configuration of a signal receiver in the signal transmission system of the present invention.

Fig. 3 is a diagram showing another configuration of the signal transmitter in the signal transmission system of the present invention.

Fig. 4 is a diagram showing a frame structure of serial transmission in the signal transmission system of the present invention.

5 is a diagram showing still another configuration of the signal transmitter in the signal transmission system of the present invention.

6 (a) and 6 (b) show the structure of the transfer programmer.

Fig. 7 (a) is a diagram showing the configuration of a transfer programmer who assigns priority between interfaces, and Fig. 7 (b) is a diagram showing the construction of a transfer program with a variable priority.

8 (a) and 8 (b) are diagrams showing the structure of a transfer programmer with variable interface information.

Fig. 9 is a diagram showing a first configuration column of the interface signal selector.

Fig. 10 is a diagram showing a second configuration column of the interface signal selector.

Fig. 11 is a diagram showing a third configuration column of the interface signal selector.

12 (a) and 12 (b) are diagrams showing an example of the configuration of the signal transmission system of the present invention.

13 (a) and 13 (b) are diagrams showing another configuration example of the signal transmission system of the present invention.

14 is a diagram showing an example of the configuration of a repeater.

Fig. 15 is a diagram for explaining data classification processing in the repeater.

Fig. 16 is a diagram showing a method for setting a bit allocation register of the present invention.

Fig. 17 is a diagram for explaining the data merging process in the repeater.

18 is a diagram showing still another configuration example of the signal transmission system of the present invention.

19 is a diagram showing another configuration example of the repeater.

2 is a diagram showing still another configuration example of the signal transmission system of the present invention.

21 is a configuration example of a peripheral module.

22 shows an example where the signal transmission system is applied to a folding cellular phone.

EMBODIMENT OF THE INVENTION Hereinafter, it demonstrates in detail, referring an accompanying drawing according to the suitable embodiment of the signal transmission system which concerns on this invention, and the integrated circuit used for it. 1, the basic configuration of the signal transmitter 100 in the signal transmission system will be described. The signal transmitter 100 includes a signal generation circuit 101 for generating signals corresponding to a plurality of parallel interfaces IF-A to D, and serializes output data generated from the signal generation circuit to transfer path 106. Send it out. Signal generation circuits IF-SG-A to D are provided corresponding to each of the parallel interfaces IF-A to D, and each signal generation circuit IF-SG generates each bit value of the corresponding interface. Each of the signal generation circuits IF-SG-A to D is configured similarly to the signal generation circuit for a conventional single interface. The interface signal selector IFS selectively extracts signals for each interface generated by the signal generation circuits IF-SG-A to D and outputs them to the serial bit array SBAT. The operation of the interface signal selector IFS is controlled by the control information 301 from the transfer programmer TP. The control information 302 indicates an interface selected by the interface signal selector IFS. The serial bit array SBAT is a memory or register, which receives the output from the interface signal selector IFS and holds it as a serial data string. The signal transmission circuit TX converts the data stored in the serial bit array SBAT to a voltage or current level matched to the physical specifications specified for the transmission path 106, and then converts the data into a transmission path ( To 106). When the signal transmitting circuit Tx outputs data of the first bit of the serial bit array SBAT, the internal bit of the serial bit array SBAT is shifted 1 bit toward the head. As a result, the signal transmitting circuit TX always extracts the head data of the serial bit array, converts it to a voltage or current conforming to the specified physical specification, and then sends the signal to the transmission path 106. 2, the basic structure of the signal receiver 200 in the signal transmission system will be described. The signal receiving circuit RX receives a signal from the transmission path 201 at a voltage or current level that matches the physical specifications specified for the transmission path 201 and converts it to a signal level used by the signal receiver 200. . The converted signal level is generally the signal level of digital data used in the system or semiconductor. The serial bit array SBAR is a memory or a register, and holds, as a serial data string, data in which the signal reception circuit RX has converted the signal level in order. Here, when the signal transmitter 100 transmits a serial signal to the transmission path, the reception programmer RP receives information from the signal transmitter 100 of which interface is selected from among a plurality of interfaces and in which order to multiplex. Based on this, the data stored in the serial bit array SBAR is restored to a plurality of parallel interface data before multiplexing, and the data is output to the parallel bit array PBA as parallel data of each interface. The parallel bit array PBA is a memory or register that holds parallel data of each interface. The parallel data output to the parallel bit array PBA is passed to the signal receiving circuits IF-SR-A to D corresponding to each interface and received. In this manner, the signal transmitter 100 and the signal receiver 200 control whether the transmission programmer TP and the reception programmer RP select which of the plurality of interfaces to multiplex and restore. According to the procedure where the signal of the interface selected by the signal transmitter 100 is multiplexed on the serial connection, the signal receiver 200 needs to restore data before the selected interface is multiplexed. Therefore, the receiving programmer RP must specify which interface is multiplexed and where the serial data corresponds to which interface. As a method, (1) the multiplexing is fixed as a module, (2) multiplexing information is included in each frame of the serial data, and (3) multiplexing information is transmitted only when the multiplexing method is changed. The method of (1) is most easily realized when there is room in the system. The method of (3) has a high level of flexibility and a good transmission efficiency. The following describes a method in which the transmission programmer TP in the signal transmitter 100 selects and multiplexes an interface among a plurality of interfaces. 1 shows an example of a first multiplexing method. The transfer programmer TP monitors the output signals 302, 303, 304 and 305 of the plurality of interface signal generation circuits IF-SG-A to D to select an interface to be stored in the serial bit array SBAT. The first example is suitable for a protocol having a manner of changing a specific bit (or group of bits) when starting transmission among signals defined as protocols. For example, a widely used PCI interface is one such standard interface. In the PCI interface, the frame signal is set to a low level prior to data transmission. The transfer programmer TP detects that this particular bit or group of bits (frame signal in the case of the PCI interface) changes, indicating that the interface is about to start transmission. Therefore, the transmission programmer TP selects that a change of a specific bit (bit group) as described above is detected among the plurality of interfaces, and transfers these interface signals to the serial bit array SBAT. 3 shows a second multiplexing method as an example. In this example, the circuit block 406 (e.g., MPU) for supplying data to the inputs of the plurality of interface signal generation circuits IF-SG-A to D is a signal (RA, RB, RC, RD) indicating transmission start. Outputs The transport programmer TP is an explicit signal (RA, RB, RC, RD).

(402, 403, 404, 405) is selected, and the interface to be stored in the serial bit array SBAT is selected. 1 and 3 can also be used in combination with each other. That is, the method of FIG. 3 can be used when the circuit block which is the source of data can be notified about the use of an explicit interface, and the method of FIG. 3 can be used even when an explicit notification cannot be obtained. Do. Next, how signals of a plurality of selected interfaces are arranged in the serial bit array SBAT of the signal transmitter 100 will be described with reference to Figs. 4 (a) to 4 (c). In either case, the interface IF-A, IF-C, and IF-D are selected, and the corresponding signals A1 to A3, C1 to C2, and D1 to D2 are selected. It shows arrangement in case of input. In FIG. 4A, the bit data 501, 502, 503 of the interfaces IF-A, IF-C, and IF-D are stored in order from the beginning of the serial bit array SBAT. However, since the signal receiver 200 does not know that the signal transmitter 100 performs such data arrangement, it is impossible to restore the data. Therefore, there is a need for a method of transferring information about the data arrangement in the serial bit array SBAT from the signal transmitter 100 to the signal receiver 200. 4 (b) shows an example of the first bit data arrangement for transferring data arrangement information. In addition to the bit data 501, 502, 503 of each interface in the serial bit array SBAT, header information SLH regarding bit arrangements subsequent to the bit positions preceding them are arranged. The header information SLH indicates which interface data is arranged in which bit. In this example, the signal of the interface IF-A is arranged in the first area 504 (that is, the interface IF-A is selected). The bit data arrangement position of the interface IF-A is, for example, started. Starting from the bit position stb1 stored in the second area 505 indicating the bit position, and up to the bit position enb1 stored in the third area 506 indicating the end bit position. The same applies to the interfaces IF-C and IF-D. For example, the first region 504 is composed of 2 bits, and the second region 505 and the third region are composed of 6 bits, respectively. In addition, the exchange between the signal transmitter 100 and the signal receiver 200 with respect to such data arrangement information may be performed at a time point at which the selection condition of the interface changes. Therefore, in the example of Fig. 4B, the header information SLH indicating the state is transmitted to the signal receiver 200 at the time when the selected interface becomes IF-A, IF-C, or IF-D. It is desirable to continue the transmission in a format that does not include the header information SLH until a change is made to the selected interface. 4 (c) shows an example of the second bit data arrangement for transferring data arrangement information. In this example, the bit examples of the serial bit array SBAT are divided into slots of a predetermined size in advance. In the header information SLH, information 5051,5081,5091 indicating which interface is used for each slot is stored. In this example, an interface (interface IF-A) using the first slot SL1 in the first region 5051 and an interface (interface IF-C) using the second slot SL2 in the second region 5081 are designated as the third region. In the area 5091, an interface (interface IF-D) using the third slot SL3 is indicated. According to this method, since it is not necessary to indicate the start bit position or the end bit position of each interface, it is possible to reduce the data amount of the batch information preceding the original bit data. For example, in the second example, each of the first to third areas of the header information SLH is two bits, and the amount of data required for the header information SLH can be greatly reduced compared to the first example. In addition, since the size of the slot is predetermined, it is also possible to simplify the bit position detector mechanism for detecting the bit position which is the boundary of another interface with the signal receiver 200. Fig. 5 shows another method of selecting and multiplexing several interfaces among a plurality of interfaces in the signal transmitter 100, and the interface signal generation circuit IF- without passing through the interface signal selector IFS controlled by the transfer programmer TP. The configuration directly connecting SG-A to D and the serial bit array SBAT is shown. In this configuration, in order to arrange all bit data of all interfaces in the serial bit array SBAT, it is necessary for the serial bit array SBAT to have an arrangement area corresponding to the bit width of each interface. In other words, the bit size of the serial bit array SBAT requires the bit width of all interfaces. As described above, the serial bit array SBAT performs a 1-bit shift operation whenever the signal transmission circuit TX connected to the leading bit transmits 1-bit data. Therefore, when the frequencies of the respective interfaces are different, the shift operation is performed when the interface signal generation circuits IF-SG-A to D store bit data at respective frequencies in the respective areas 602 to 605 of the serial bit array SBAT. The data may be destroyed by doing so. Therefore, in order for all the bit data of both interfaces to be transmitted from the signal transmitting circuit TX, it is necessary to make the data of the serial bit array SBAT replaceable at regular intervals. 6 (a) and 6 (b) illustrate a method in which the transfer programmer TP selects some interfaces from a plurality of interfaces and transfers bit data to the serial bit array SBAT. Here, a description will be given of a control method in which the transfer programmer TP assigns an interface to a slot in the case of performing transmission by the slot configuration as shown in Fig. 4C. The transfer programmer TP indicates an interface information table 701 which describes a frequency F and a bit width BW for each of a plurality of interfaces, and indicates which interface signal is to be placed in which slot in the serial bit array SBAT by using the same. It has a slot aligner SL-AL for generating a control signal. Subsequently, when several interfaces are selected from the plurality of interfaces in the same order as described with reference to Figs. 1 and 3, the interfaces IF-A, IF-C, and IF-D are selected. In other words, it is assumed that the interfaces IF-A, IF-C, and IF-D actually require data transmission. Serial transmission operates at a frequency of 1920 MHz and assumes a data transmission band of 1920 Mbps (bit per second). In addition, the area where each interface bit data of the serial bit array SBAT is stored is 32 bits wide, and data stored at a frequency of 60 MHz can be replaced. Furthermore, the 32 bit width is divided into 8 bit wide slots. It shall be done. Therefore, the transmission band per slot is determined as 60 MHz x 8 = 480 Mbps. The transport programmer TP compares the transmission band used by each interface with the transmission band per slot in advance, and determines which slot of which cycle the signal of each interface is to be placed. Now, as shown in Fig. 6 (a), the interfaces IF-A to D are 30 MHz x 32 bits (960 Mbps), 10 MHz x 32 bits (320 Mbps), and 15 M, respectively.

If a data transmission band of Hz x 56 bits (840 Mbps) and 2 MHz x 8 bits (16 Mbps) is used, adding all these data transmission bands requires a band of 2136 Mbps.  The slot aligner SL-AL in Fig. 6 (a) selects all of the interfaces IF-A, IF-B, IF-C, and IF-D regardless of which interface actually requires data transmission. The control signal 301 is output to the interface signal selector IFS.  For example, a control signal 703 is generated which instructs to select all four types of interfaces IF-A to D registered in the interface information table 701 in order.  At a frequency of 60 MHz, 32 bits of data (4 slots (slots SL1 to 4, respectively) of the serial bit array SBAT are used for each cycle. ) Is replaced to place bit data of each slot in order from the first cycle according to each interface bit width.  In this case, the transfer programmer TP outputs a control signal 704 that receives the bit data of the interface IF-A in order to arrange the signal of the interface IF-A in the first cycle.  Since the interface IF-A is 32 bits wide, it can be arranged by occupying one cycle (first cycle) of four slots of the serial bit array SBAT.  Next, the transfer programmer TP outputs a control signal 705 that receives the bit data of the interface IF-B to arrange the signal of the interface IF-B.  Since the interface IF-B is also 32 bits wide, it can be arranged to occupy one cycle (second cycle) of four slots of the serial bit array SBAT.  Next, the transfer programmer TP outputs a control signal 706 that receives the bit data of the interface IF-C to arrange the signal of the interface IF-C.  Since the interface IF-C is 56 bits wide, it is not allocated only by occupying one cycle (third cycle) of four slots of the serial bit array SBAT, and uses the remaining three slots in the fourth cycle because the remaining bit data is disposed. The control signal 707 is outputted so as to.  Further, in the control signal 707, one empty slot is used to arrange the signal of the interface IF-D.  Since the interface IF-D is 8 bits wide, in 4 cycles, the number of bits corresponding to the sum of the bit widths of all interfaces can be obtained.  However, the method of transferring all the bit data from the interface registered in the simple interface information table 701 to the serial bit array SBAT is easy to implement, but the shortage of the transmission band is likely to occur.  Here, the interface is put on the interface IF-A.  Interface IF-A needs to transfer 32-bit data at 30MHz.  In contrast, the data stored in the serial bit array SBAT is a cycle of 60 MHz, which is 32 bits of data for 4 cycles.  Thus, only 32-bit data is placed in cycles of 15 MHz.  This cannot satisfy the data transmission band of the interface IF-A, which must transmit 32 bits of data in a cycle of 30 MHz.  Therefore, in this transfer method, a state in which data necessary for the interface IF-A cannot be transferred occurs.  However, as described above, bit data may not always be transmitted from all interfaces, and some interfaces may require data transfer at some time.  Fig. 6 (b) shows another method in which the transfer programmer TP places data in the serial bit array SBAT when the interfaces actually requiring data transfer are IF-A, IF-C, and IF-D.  As in Fig. 6 (a), the 32-bit data (4 slots equivalent) of the serial bit array SBAT is replaced every cycle at a frequency of 60 MHz.  The transfer programmer TP outputs a control signal 709 that accepts bit data of the interface IF-A which arranges the signal of the interface IF-A in the first cycle.  Next, the transfer programmer TP detects that it is not necessary to transmit the signal of the interface IF-B, and does not arrange the serial bit array SBAT for the interface IF-B.  Instead, a control signal 710 for receiving bit data of the interface IF-C is output in a second cycle in order to arrange the signal of the interface IF-C.  Since the interface IF-C is 56 bits wide, even though it occupies 4 slots of the serial bit array SBAT, not all data is yet placed in the serial bit array SBAT.  However, the transfer programmer TP outputs a control signal 711 that receives the bit data of the interface IF-A in the third cycle in order to place the signal of the interface IF-A in the serial bit array SBAT.  Next, 24 bits (56 bits (data width of the interface IF-C)-32 bits (in the second cycle, the serial bit array SBAT) are not yet assigned to the serial bit array SBAT in the data of the interface IF-C in the fourth cycle. The control signal 712 is outputted so that the number of arranged bits)) is arranged in the remaining three slots.  Further, in the control signal 712, one empty slot is used to arrange the signal of the interface IF-D.  Hereinafter, this 4 cycle is repeated.  Then, in the case of the transfer as shown in FIG. 6 (b), in the interface IF-A, 32 bits of data are transferred to the serial bit array SBAT using four slots in the first and third cycles, respectively. have.  That is, 32 bits of data are placed every two cycles.  Thus, 32-bit data is placed in the serial bit array SBAT in a cycle of 30 MHz, which is half of 60 MHz, and can be transmitted through the signal transmitter TX.  This is equivalent to the transmission band 30 MHz x 32 bits required by the interface IF-A.  Next, when the interface IF-C is taken into account, data for a total of seven slots are arranged using four slots and three slots in the second and fourth cycles, respectively.  Therefore, 56 bits of data can be transmitted in four cycles.  That is, it has 56-bit transmission band at 15 MHz, which is 1/4 of 60 MHz, which is the same as the transmission band required by interface IF-C.  Further, in the interface IF-D, data is arranged using one slot for the fourth cycle.  That is, 8-bit data transmission is possible at 15 MHz, which is 1/4 of 60 MHz.  This corresponds to 15 MHz x 8 bits = 120 Mbps.  On the other hand, since the transmission band required by the interface D is 2 MHz x 8 bits = 16 Mbps, the transmission band is smaller than the 120 Mbps and no transmission band problem occurs.  In this way, by varying the multiplexing method according to the selected interface, the possibility of a shortage of transmission bands can be reduced.  FIG. 7 (a) is another example of a control method in which the transmission programmer TP allocates an interface to a slot, and is an example in which the transmission programmer TP is allocated in consideration of the demand satisfaction for the transmission band between interfaces.  Such a control method is suitable for a case where the problem as a system is small even when the demand satisfaction degree varies depending on the interface, and the transmission band cannot be kept on the low demand satisfaction interface.  In this example, the transfer programmer TP places the bit data from each interface in the serial bit array SBAT, taking into account the stringency of this transmission band requirement.  In this example, the serial transmission operates at a frequency of 1280 MHz, has a data transmission band of 1280 MHz, and replaces the data stored in the 32-bit wide serial bit array SBAT for each 40 MHz frequency. In the example of FIG. 7A, priority P is attached to each interface as an index indicating the degree of satisfaction of the request in the interface information table 801.  Priority is given in the order of interfaces IF-D, IF-B, IF-A, and IF-C. Therefore, if interfaces IF-A, IF-C, and IF-D are selected, the interface with higher priority P Quickly place bit data in cycles.  The priority slot aligner P-SL-AL outputs a control signal 803 that receives the bit data of the interface IF-D in the first cycle in order to arrange the signal of the interface IF-D having the highest priority P. do.  Since the data of the interface IF-D is 8 bits wide, it is placed in the first cycle in the size 1 slot of the serial bit array SBAT.  Also, the transfer programmer TP detects that it is not necessary to transmit the signal of the interface IF-B of the second priority, and the control program 803 uses the control signal 803 to arrange the signal of the interface IF-A of the third priority. Accepts bit data of interface IF-A in the remaining slot of one cycle.  Thus, 24 bits of the interface IF-A are first arranged in three slots of the serial bit array SBAT.  Next, the priority slot aligner P-SL-AL outputs a control signal 804 to arrange the remaining 8-bit data of the interface IF-A in the second cycle.  The control signal 804 arranges the next 24-bit data of the interface IF-A in the remaining three slots of the second cycle.  Subsequently, in order to arrange the remaining 8-bit data of the interface IF-A, a control signal 805 that receives the bit data of the interface IF-A is output in the third cycle.  The control signal 805 places the next 24-bit data of the interface IF-A in the remaining three slots of the third cycle.  In the fourth cycle, a control signal 806 that receives the bit data of the interface IF-A is output in order to arrange the remaining 8-bit data of the interface IF-A.  The control signal 806 places 24 bits of data of the interface IF-C in the remaining 3 slots of the fourth cycle.  In addition, since the interface IF-C is 56 bits of data, the remaining 32 bits are not yet arranged.  In the fifth cycle, a control signal 807 that receives the bit data of the interface IF-A is output in order to place the next data of the interface IF-A in the serial bit array SBAT.  In the sixth cycle, a control signal 808 for receiving bit data of the interface IF-A is further outputted in order to arrange the next data of the interface IF-A.  In the seventh cycle, a control signal 809 which receives the bit data of the interface IF-A is output in order to place the next data of the interface IF-A in the serial bit array SBAT.  In the eighth cycle, a control signal 810 for receiving the bit data of the interface IF-C is outputted in order to place the next data of the interface IF-C into the serial bit array SBAT.  Hereinafter, the above 8 cycles are repeated.  In the case of performing the above-described transmission, it is confirmed whether data transmission can be performed while satisfying the transmission band required by each interface.  First, with regard to the interface IF-D, one slot of data is arranged in the first cycle, and no data is arranged until the eighth cycle thereafter.  Thus, 8 bits of data are transmitted once at a frequency of 5 MHz (40 MHz / 8), i.e., this is a data transmission band of 5 MHz x 8 bits, which is a problem because it is smaller than the transmission band required by the interface IF-D. It does not occur (the excess of the data transmission band can be handled by not placing data).  Next, in the interface IF-A, 12 slots are arranged in each of the first to fourth cycles and the fifth to eighth cycles.  Therefore, 32 x 3 bits of data transmission are performed per 10 MHz (40 MHz / 4), which is the same as the transmission band 30 MHz x 32 bits required by the interface IF-A.  Next, when the interface IF-C is taken into account, data for a total of seven slots are arranged using three slots and four slots in the fourth and eighth cycles, respectively.  Therefore, 56 bits of data can be transmitted in 8 cycles.  That is, it has a 56-bit transmission band at 5 MHz (40 MHz / 8), which is smaller than 15 MHz x 56 bits of the transmission band required by the interface IF-C, and cannot satisfy the transmission band of the interface IF-C.  However, if the requirements of interface IF-C are lower than other interfaces (i.e., IF-A or IF-D in this case), the lack of a transmission band in this interface C is preferable to the lack of a transmission band of another interface. Can be said.  Fig. 7B shows an example in which the priority P in the interface information table 813 is implemented as writing to a variable register or memory without setting the priority P as a fixed value.  This makes it possible to flexibly change the priorities 811 or 812 after system design or after system startup, without determining the priority between fixed interfaces during system manufacture.  Fig. 8A shows a configuration in which the information of each interface can be changed in the interface information table even after the system is manufactured.  That is, in the interface information table 901, in addition to the information 902 and 903 of previously registered interfaces, other interface information 906 and 907 are registered in an area 904 and 905 different from the area in which these are stored, after system manufacturing. Can be.  All the interface information may be registered after the system is manufactured.  FIG. 8 (b) shows an example in which interface information is additionally registered after system manufacturing or after system operation with respect to the prioritized interface information table.  9 to 11 illustrate a configuration example of the interface signal selector IFS.  The interface signal selector IFS has a function of taking out data of some selected interfaces from a plurality of interfaces generated by the signal generation circuit and outputting them to the serial bit array SBAT.  The selection of the interface is made based on the control information 301 received from the transfer programmer TP.  In Fig. 9, the interface signal selector IFS receives a plurality of interface signals 2101 and selects an interface to be output to the serial bit array SBAT by the control signal 301 from the transfer programmer.  Each of the signals from the plurality of interfaces is input to the selector 2105 connected to the output 2103 to the serial bit array SBAT.  The signal of the interface selected by the control signal 301 from the transfer programmer TP is selected by the selector 2105 controlled by the selector controller SELCON and placed in the serial bit array SBAT.  10 is a diagram illustrating another configuration example.  When the frequencies of the plural interfaces are the same, the signals from the respective interfaces are stored in the memory 2106 in synchronization with the reference signal 2107 in order to temporarily store the signals from each interface, and then output to the selector 2105.  As a result, even when there is a difference in input timing between signals from a plurality of interfaces, once it is synchronized to the reference signal 2107 and stored in the memory 2106, it is synchronized to the reference signal 2107 again. By outputting at the same timing, it is possible to prevent the influence of the timing difference on the signal propagation path after the selector 2105. Such a memory 2106 can be realized by a circuit which stores and outputs a value in synchronization with a clock signal such as a D flip-flop.  1 is a diagram showing another configuration example.  When the frequencies of the plurality of interfaces are different, when temporarily storing signals from each interface, the memory is stored in synchronization with the other reference signals 2108, 2109, 2110, and 2111, and then again stored in another reference report 2112. The output is synchronized.  Fig. 12A is a configuration example of the signal transmission system of the present invention, and is provided with a microprocessor CPU1 and two peripheral modules PM1 and PM2 on a printed board 1001.  A peripheral module is, for example, a microcontroller such as a camera module, a liquid crystal display module, a memory module, a device controlled by a microprocessor, a microprocessor such as a storage device for the microprocessor, or an auxiliary processor that performs dedicated operations such as image processing and audio processing. Points to components other than processors.  Precisely, the camera module and the liquid crystal display module include not only an integrated circuit but also a main body of a camera or a liquid crystal display, but only the integrated circuit portion on the printed circuit board 1001 is shown in the drawing.  The microprocessor MCU 1 includes a transmitting unit for multiplexing and transmitting a plurality of interface signals shown in FIG. 1 toward a serial signal, and a receiving unit for receiving the multiplexed serial signals as shown in FIG. 2 and restoring them to parallel signals of respective interfaces. We shall have.  In the example of the figure, data and clock are transmitted in a differential signal transmission path in which two signal lines are paired.  The differential serial signal transmission line connected to the microprocessor GPU1 includes a differential signal transmission line 1003 for data transmitted from the microprocessor MPUI to the peripheral module PM1, and a differential signal transmission line 1005 for data received by the microprocessor GPU1. Four sets of the clock signal differential signal transmission line 1004 in synchronization with the transmission data from the microprocessor GPU1, and the clock signal differential signal transmission line 1006 in synchronization with the data received by the microprocessor GPU1.  In the figure, as a part of understanding, the signal direction is indicated by an arrow beside the transmission line.  It is assumed that the peripheral modules PM1 and PM2 used in the system configuration of Fig. 12A have a conventional parallel interface.  For this reason, repeaters RL1 and RL2 for transmitting and receiving parallel signals conforming to the parallel interface of each peripheral module are required.  The configuration of the repeater will be described later in detail with reference to other drawings, but only the functions will be described here.  The repeater RL1 receives the multiplexed serial signal transmitted from the microprocessor GPU1 through the differential serial signal transmission path 1003, converts the signal into a parallel signal, selects only the signals necessary for the peripheral module PM1, and executes the parallel signal transmission path 1015. A function of transmitting to the peripheral module PM1 via the parallel signal transmitted from the peripheral module PM1 through the parallel signal transmission path 1015, and receiving the serial signal transmitted from the repeater RL2 via the differential serial signal line 1009. It receives and generates a multiplexed serial signal from these received signals, and transmits them to the microprocessor GPU1 via the differential signal transmission line 1005.  In addition, the repeater RL1 has a function of receiving the multiplexed serial signal transmitted from the microprocessor GPU1 through the differential serial signal transmission path 1003 and transmitting it to the relay RL2 via the differential serial signal transmission path 1007.  Repeater RL2 has almost the same function as repeater RL1, but differs from repeater RL1 in that there is no connection to another repeater.  This signal transmission is performed when only two data transfers between the microprocessor and the peripheral module exist, such as in the case of the two camera modules and the liquid crystal display module, and there is no data transfer between the peripheral modules. It is a signal transmission to  On the other hand, data transfer between peripheral modules may exist.  For example, when the peripheral module is a memory and an image processing processor, both the image processing processor and the microprocessor may access the memory, or there may be transmission and reception of signals between the image processing processor and the microprocessor.  In this case, the repeater RL1 converts the serial signal transmitted from the microprocessor GPU1 into a parallel signal, selects only a signal necessary for the peripheral module PM1, and transmits the signal to the peripheral module PM1 through the parallel signal transmission path 1015, as well as the repeater RL2. The serial signal transmitted from S1 is converted into a parallel signal, and only a signal necessary for the peripheral module PM1 is selected and transmitted to the peripheral module PM1 through the parallel signal transmission path 1015.  In addition, when receiving the parallel signal transmitted from the peripheral module PM1 through the parallel signal transmission path 1015 and determining whether to transmit it to the microprocessor CPU1 or the peripheral module PM2, and to transmit it to the microprocessor GPU1, Then, a multiplexed serial signal is generated by combining with the serial signal transmitted from the repeater RL2 and transmitted to the microprocessor GPU1 through the differential serial signal transmission path 1005.  On the other hand, when transmitting to the peripheral module PM2, a multiplexed serial signal is generated by combining with the serial signal transmitted from the microprocessor GPU1, and transmitted to the relay RL2 via the differential serial signal transmission path 1007.  Thus, considering that all of the parallel transmission lines 1015 and 1016 in FIG. 12A must be connected to the microprocessor MCU 1, the number of signal transmission paths connected to the microprocessor can be reduced more than before. It is easy to understand that there is.  An example of using a so-called one-wire transmission line called a single ended in place of the differential transmission line of FIG. 12 (a) is shown in FIG. 12 (b).  The input / output circuits in the microprocessor and repeater are different in the one-wire and two-wire systems, but in the one-wire system, known techniques such as TTL, SSTL, HCMOS, and two-wire LVDS or CML can be used. O) omitted.  In the present invention, these input / output circuits are not limited.  12 (a) and 12 (b), the clock signal is transmitted in synchronization with the serial data on the transmitting side.  In Fig. 12A, a differential signal transmission path 1004 for transmitting a clock signal synchronized with serial data transmitted from the microprocessor GPU1, and a clock signal synchronized with serial data transmitted from the repeater RL1 to the microprocessor GPU1 are transmitted. The differential signal transmission path 1006 transmits a clock signal synchronized with the serial data transmitted from the repeater RL1 to the repeater RL2 and the clock signal synchronized with the serial data transmitted from the repeater RL2 to the repeater RL1. The clock signal transmission path is configured by the differential signal transmission path 1010 that transmits.  Similarly, in Fig. 12B, a signal transmission path 1019 for transmitting a clock signal synchronized with serial data transmitted from the microprocessor GPU1, and a clock signal for synchronizing serial data transmitted from the repeater RL1 to the microprocessor GPU1 are transmitted. Signal transmission line 1020, which transmits a clock signal synchronized with the serial data transmitted from the repeater RL1 to the repeater RL2, and transmits a clock signal synchronized with the serial data transmitted from the repeater RL2 to the repeater RL1. The signal transmission path 1024 constitutes a clock signal transmission path.  When performing high-speed serial data transfer, it is necessary to minimize the time difference between the data called skew and the clock, and the length and the path are the same as long as the signal transmission line of the clock and the data can be as shown in the figure. In this case, a method is used in which the transmitting side transmits a clock together with serial data so as to extend side by side.  FIG. 13 is another example of the configuration of the signal transmission system of the present invention, and is supplied with a clock different from FIG.  Fig. 13A is suitable for the case where the transmission frequency of the serial data is relatively low.  In this configuration, the clock signals are distributed to all the modules by the clock signal transmission line 1101 from the microprocessor GPU1.  In this figure, an example in which the clock signal transmission line is transmitted as one signal rather than a differential signal is shown.  On the contrary, in the case of performing a serial transmission faster than that in Figs. 12A and 12B, even a small skew between the data and the clock becomes a problem, and as shown in Fig. 13B, What is necessary is just to use the so-called clock-and-data recovery circuit which inserts and transmits a clock with data at a transmission side, and reproduces data and a clock from a reception signal at a reception side, without performing a clock transfer.  Since these techniques are well known, the description is omitted here.  Fig. 14 is a diagram showing in detail the internal structure of the repeater RL1 of the signal transmission system shown in Fig. 12A.  From the microprocessor MCU1, data transmitted to two peripheral modules is multiplexed and transmitted to the differential signal transmission line 1003, and a clock signal synchronized with serial data is transmitted to the differential signal transmission line 1005.  Repeater RL1 receives a differential signal from serial receiver SR1.  The received serial data is input to the serial / parallel converter SP1.  The received clock is distributed to a clock divider CDV1, a serial / parallel converter SP1, a parallel / serial converter PS1, and a serial transmitter ST1 by a clock signal line 1214 inside the repeater.  Hereinafter, this clock signal will be referred to as "first serial clock".  The clock divider CDV1 divides the first serial clock to generate a clock having a frequency lower than that of the first serial clock.  Hereinafter, this is called "first parallel clock."  The first parallel clock is distributed to a serial / parallel converter SPI, a data classifier DD1, a parallel / serial converter PS1, and a parallel transmission / reception circuit PTV1 as a clock signal line 1216 inside the repeater.  In the serial / parallel converter SP1, serial data is converted into parallel data.  Serial / parallel converters can be easily realized, for example, by using a shift register.  For example, when the parallel data is 16 bits, the frequency ratio of the first serial clock and the second parallel clock is set to 16 to 1, and the serial clock is used as the shift clock of the shift register. Serial / parallel conversion is performed by extracting data from the data.  The generated parallel data is input to the data classifier DD1.  In the data classifier, bit data corresponding to data to be transmitted to the peripheral module PM1 is selected from the parallel data according to a predetermined rule and passed to the parallel transceiver PM1 to the peripheral module PM1 through the parallel signal transmission line 1015. Send.  The function of the data classifier DD1 is the same as that of the reception programmer RP in the above-described embodiment of FIG.  The parallel data is passed to the parallel / serial converter PS1, and once again converted into serial data, and transmitted from the serial transmitter ST1 to the relay RL2 via the differential serial signal transmitter 1007.  In the figure, the parallel data input to the parallel / serial converter PS1 represents the number of bits excluding the parallel data transmitted to the peripheral module PM1.  The original parallel data may be serially converted as it is and sent.  In this case, the repeater RL1 can be configured as a general purpose irrespective of the peripheral module to be connected.  On the other hand, the parallel data bits transmitted to the peripheral module PM1 may be transmitted as arbitrary data such as H level and L level.  In this case, the communication load can be reduced by making the frequency component in subsequent serial transmission simpler.  In addition, a signal path (not shown) for transmitting the serial data received from the microprocessor GPU1 to the repeater RL2 without passing through the serial / parallel converter SP1 or the parallel / serial converter PS1 may be provided.  The repeater RL2 serializes the data transmitted to the microprocessor MCU 1 and transmits it to the differential signal transmission line 1008, and a clock signal synchronized with the serial data is transmitted to the differential signal transmission line 1010.  Repeater RL1 receives a differential signal as serial receiver SR2.  The received serial data is input to the serial / parallel converter SP2.  The received clock is distributed to the clock divider CDV2, the serial / parallel converter SP2, the parallel / serial converter PS2, and the serial transmitter ST2 as the clock signal line 1215 in the repeater RL1.  Hereinafter, this clock signal will be referred to as "second serial clock."  The clock divider CDV2 divides the second serial clock to generate a clock having a frequency lower than that of the serial clock.  Hereinafter, this is called "second parallel clock."  The second parallel clock is distributed to the serial / parallel converter SP2, the data combiner DJ1, the parallel / serial converter PS2, and the parallel transceiver PTV1 as the clock signal line 1217 inside the repeater.  In the serial / parallel converter SP2, serial data is converted into parallel data.  The converted parallel data is input to the data combiner DJ1.  On the other hand, from the peripheral module PM1, parallel data is transmitted via the parallel signal transmission line 1015 and received by the parallel transceiver PTV1.  Parallel data is input to the data combiner DJ1.  The data joining DJ1 generates one parallel data in which two inputted parallel data are arranged according to a predetermined rule, and inputs the same to the parallel / serial converter PS2.  In the parallel / serial converter PS2, the input parallel data is converted into serial data and transmitted from the serial transmitter ST2.  The serial data and the second serial clock are transmitted to the microprocessor GPU1 through the differential signal transmission line 1004 and the differential signal transmission line 1006.  In Fig. 14, the relationship with Figs. 1 and 2 will be described.  In FIG. 14, for simplicity of explanation, the viewpoint of selecting another interface is not discussed.  Therefore, the correspondence relationship is shown here.  1 is a configuration included in the parallel / serial converter PS1 and the serial transmitter ST1, or the parallel / serial converter PS2 and the serial transmitter ST2.  2 is a configuration included in the serial / parallel converter SP1 and the serial receiver SR1, or the serial / parallel converter SP2 and the serial receiver SR2.  Next, the data classification operation in the repeater will be described with reference to FIG.  It is assumed that the serial data 1300 transmitted from the microprocessor GPU1 and received by the repeater RL1 progresses from the left side to the right side of the figure.  The serial data is synchronized with the serial clock signal 1306 to treat a continuous data range called the frame 1301 as one group.  The structure of the frame is defined as a protocol of the signal transmission system.  In this example, the first three bits of frame sync bits 1302 and 1303 are inserted in order to determine the boundary of the frame with 16 bits of data as one frame.  In addition, 9 bits 1304 in which the transmission data to the repeater RL2 follow the frame synchronization bit, and 4 bits 1305 remaining in the transmission data to the peripheral module PM1.  In serial / parallel conversion SP1, data is converted into parallel data for each frame of 16 bits.  Therefore, the parallel clock 1307 is a clock divided into one sixteenth of the serial clock.  One frame of parallel data 1308 is received by the data classifier DD1, and the data classifier DD1 selects only the parallel data 1309 to be transmitted to the peripheral module PM1, and transfers it from the parallel transmission / reception circuit PTV1 to the peripheral module PM1.  Parallel data 1308 is once again serialized and transmitted as a serial data 1310 to repeater RL2.  The bit allocation register 1311 is used to select the parallel data 1309 to be transmitted to the peripheral module PM1.  In this embodiment, the bit allocation register 1311 has a structure in which 1 is stored in a bit position to be selected and 0 is stored in other bit positions.  In addition to this structure, for example, a structure for storing the start bit position and the last bit position of the selected bit, or a structure for storing the start bit position and the number of bits can also be taken.  The allocation register exists not only in the relay RL1 but also in the relay RL2.  By rewriting the contents of the bit allocation register, it is possible to change which transmission line is assigned to which transmission line.  For example, as shown in Fig. 16 (a), it is also possible to set the bit allocation registers of the repeaters after starting the system (S2001) (S2001), and then perform system processing in accordance with the setting (S2003 to 2005). .  When the bit allocation register is not changed, for example, the repeater may store the data in a nonvolatile memory (for example, a read-only memory or a flush memory) not shown and read it at startup.  On the other hand, it is also possible to change the bit allocation register according to the system operation situation during the system operation.  For example, as shown in Fig. 16 (b), an appropriate bit allocation register may be set for each process (S2013, S2015, S2017) (S2012, S2014, S2016).  This makes it possible to use an effective signal transmission line.  This bit allocation register is changed in accordance with the instruction of the microprocessor GPU1.  For example, it is possible to realize by providing a control line for instructing such a change in the bit allocation register between the microprocessor and the CPU1.  Next, the data joining operation in the repeater will be described with reference to FIG.  In FIG. 17, it is assumed that the serial data 1401 received by the repeater RL1 from the repeater RL2 proceeds from the right side to the left side of the figure.  Also in this example, the serial data assumes the same frame structure as in the example of FIG. 15, but in this figure, frame synchronization bits are omitted and only 13 bits corresponding to the bit data are shown.  The transmission data from the repeater RL2 to the microprocessor GPU 1 is the first 5 bits.  In serial / parallel conversion SP2, parallel data is converted in one frame unit.  One frame of parallel data 1403 converted in parallel is received by the data combiner DJ1.  The 8-bit parallel data 1404 received from the peripheral module PM1 is also received by the data combiner DJ1.  In the data combiner DJ1, parallel data 1404 for transferring the peripheral data PM1 to the microprocessor GPU1 is inserted into the 13-bit parallel data 1403 in which the serial data from the repeater RL2 is converted in parallel.  The bit position to be inserted is determined by referring to the bit allocation register 1406.  As in Fig. 15, the structure is that 1 is stored in the bit position to be inserted and 0 is stored in the other bit positions.  The parallel data 1405 thus produced is converted into serial data 1402 by the parallel / serial converter PS2 and transmitted to the microprocessor GPU1.  The bit allocation register 1406 can also be set as described with reference to Figs. 16A and 16B.  In addition, in this invention, a repeater is not necessarily limited to connecting with one peripheral module.  For example, Fig. 18 is a system configuration which has a plurality of parallel transceivers and is connectable with a plurality of peripheral modules.  FIG. 18 is an example of a system composed of a microprocessor GPU1 and two peripheral modules PM1, PM2 on the printer substrate 1001 as in FIG.  The difference is that the repeater RL3 is connected to both peripheral modules PM1 and PM2 via parallel transmission lines 1015 and 1016.  19 shows the internal structure of the repeater RL3.  From the microprocessor GPU1, serial signals multiplexed to two peripheral modules are transmitted to the differential signal transmission line 1003, and a clock signal synchronized with the serial data is transmitted to the differential signal transmission line 1005.  Repeater RL3 receives a differential signal from serial receiver SR3.  The received serial data is input to the serial / parallel converter SP3.  The received clock is distributed to the clock divider CDV3 and the serial / parallel converter SP3 by the clock signal line 1214 inside the repeater.  Hereinafter, this clock signal will be referred to as "first serial clock."  The clock divider CDV3 divides the first serial clock to generate a clock having a frequency lower than that of the serial clock.  Hereinafter, this is called "first parallel clock."  The first parallel clock is distributed to the serial / parallel converter SP3, the data sorter DD2, the parallel transceivers PTV2, and PTV3 as a clock signal line 1216 in the repeater.  The serial / parallel converter SP3 converts serial data into parallel data.  The generated parallel data is input to the data classifier DD2.  In the parallel data, the data classifier DD2 selects the bits corresponding to the data transmitted to the peripheral module PM1 and transmits them to the parallel transceiver PTV2 according to a predetermined rule, and selects the bits corresponding to the data transmitted to the peripheral module PM2. Delivers to parallel transceiver PTV3.  The parallel transmitter PTV2 transmits the received parallel signal to the peripheral module PM1 through the parallel signal transmission line 1015, and the parallel transmitter PTV3 transmits the received parallel signal to the peripheral module PM2 through the parallel signal transmission line 1016.  In addition, there is a PLL-Phase Locked Loop 1602 that generates a high speed second serial clock and a low speed second parallel clock to transmit serial data to the microprocessor GPU1.  The clock source 1605 is input to the PLL 1602.  The clock source 1605 may be supplied from the microprocessor MCU 1 or from another clock source on the printed board.  The second serial clock is supplied to the serial / parallel converter PS3 and the serial transmitter ST3 as a clock signal line 1604 in the repeater.  The second parallel clock is distributed to the data combiner DJ2, the parallel / serial converter PS3, the parallel transceivers PTV2, and PTV3 by the clock signal line 1603 inside the repeater.  From the peripheral module PM2, parallel data is transmitted via the parallel signal transmission line 1016, and the parallel data received by the parallel transmitter PTV3 is input to the data combiner DJ2.  On the other hand, from the peripheral module PM1, parallel data is transmitted via the parallel signal transmission line 1015, and the parallel data received by the parallel transmitter PTV2 is input to the data combiner DJ2.  In the data combiner DJ2, one parallel data in which two inputted parallel data are arranged in accordance with a predetermined rule is generated and input to the parallel / serial converter PS3.  In the parallel / serial converter PS3, the input parallel data is converted into serial data.  The serial data and the second serial clock transmitted from the serial transmitter ST3 are transmitted to the microprocessor GPU1 through the differential signal transmission line 1004 and the differential signal transmission line 1006.  More than.  The peripheral module itself may have the function of the repeater described.  FIG. 20A shows an example of the configuration when the peripheral module has a function of a repeater inside.  In Fig. 20A, the peripheral module PM3 receives a multiplexed serial signal from the microprocessor GPU1, receives only the data transmitted to itself, and transmits serial data to the peripheral module PM4, and from the peripheral module PM4. Receives a serial signal, generates a multiplexed serial signal of the data to be sent to the microprocessor itself, and transmits it to the microprocessor GPU1.  The peripheral module PM4 has a function of receiving serial data, accepting only data transmitted to itself, and transmitting the data to be transmitted to the microprocessor as a serial signal.  Fig. 20B is a configuration example in which the peripheral module has a function of directly transmitting and receiving serial signals without going through a repeater, or so-called bus connection in which a plurality of peripheral modules are connected to a serial signal transmission line. It is.  In this example, the receiving method of the serial signals of the microprocessor CPU1, the peripheral modules PM3, and PM4 is the same as in Fig. 20A, but care is required during transmission.  When multiple modules drive the transmission line at the same time, signal collisions occur and normal data transmission is prevented.  Here, the control for driving the transmission line is necessary only when transmitting the bits allocated to each module.  In addition, since there is a branch in the signal transmission line, signal reflection occurs, which is not suitable for high-frequency serial transmission.  Fig. 21 shows the internal structure of the peripheral module PM3 of Fig. 20A.  The peripheral module PM3 consists of a transfer unit 1801 and a main circuit 1802.  The transmission unit 1801 is a circuit portion that achieves the same function as a repeater in the configuration example of FIG.  The difference is that, for example, the parallel transceiver PTV1 in the repeater RL1 at 14 degrees is replaced with the bus connection circuit BCC1 for exchanging data with the internal bus 1804 of the main circuit.  The main circuit 1802 is a circuit portion which performs the operation itself of each peripheral module.  By storing the transfer unit 1801 as a design asset IP and reusing or circulating it widely, many peripheral modules can be connected to the system configuration of the present invention without a repeater.  Furthermore, the present invention is not limited to a signal transmission system on a single printer substrate, but is also applicable to a signal transmission system for transmitting signals through a cable to a plurality of substrates or to a signal transmission system between a plurality of devices.  Fig. 22 shows an example of application to a folding cellular phone as an application embodiment to a signal transmission system between a plurality of printer substrates.  The folding cellular phone 1901 has a configuration in which a main light housing 1902 and a sub light housing 1403 are connected to a movable hinge portion 1904. have.  Mainly, operation keys are provided on the main light body, and the camera 1913 and the liquid crystal display 1914 are provided on the negative light body.  The microprocessor GPU 2 is installed on the main board 1905 stored in the main light 1902.  Originally, on the main board 1905, not only a microprocessor but also many integrated circuits and passive elements are integrated at a high density. However, since the diagram is not related to the nature of the description, it is omitted. Thus, the microprocessor and the parallel signal transmission line are omitted. Shows only the memory module MM1 that is connected.  On the other hand, the camera control integrated circuit CC1 and the liquid crystal control integrated circuit LCDC1 are provided on the sub-substrate 1906 and are stored in the negative light body 1903.  The camera control integrated circuit CC1 is connected to the camera 1913, and the liquid crystal control integrated circuit LCDC1 is connected to the liquid crystal display device 1914 with a parallel cable.  The microprocessor GPU 2 needs to be connected to the camera control integrated circuit CC1 and the liquid crystal control integrated circuit LCDC1 in order to perform data transfer.  In the prior art, since a parallel cable is connected, it is necessary to pass a large number of cables through a narrow hinge portion.  As the hinge portion rotates, the wiring cable is pressed and disconnected.  Moreover, the electromagnetic radiation noise radiated | emitted from many wiring through a hinge part also became a problem.  According to the signal transmission system of the present invention, the liquid crystal control integrated circuit LCDC1 and the camera control integrated circuit CC1 are connected by a serial transmission line on the sub-substrate 1906, and the number of cables is between the microprocessor GPU2 and the liquid crystal control integrated circuit LCDC1. A small serial cable (1910) is connected.  This makes it possible to significantly reduce the number of wiring cables passing through the hinge portion, as compared with the prior art, thereby reducing the problem of disconnection and noise.  In the configuration of Fig. 22, the memory module MM1 mounted on the main board is connected in a parallel signal transfer method instead of serial signal transfer.  There are two reasons for this.  The first reason is the placement of peripheral modules and microprocessors.  The memory module MM1 is one of peripheral modules connected to the microprocessor similarly to the liquid crystal control integrated circuit LCDC1 and the camera control integrated circuit CC1. The liquid crystal control integrated circuit LCDC1 and the camera control integrated circuit CC1 are the camera 1913 or the liquid crystal display device ( Unlike the one mounted on the sub-substrate 1906 because the 1914 is provided close to the sub-optical body 1903, the connection of the memory module MM1 is disposed close to the microprocessor on the main substrate 1905.  This transfer to other substrates is one of the reasons for changing the transfer method, in that the effect of applying the serial signal transfer method of the present invention, which can reduce the number of wiring wires, is greater than the transfer in the same board.  In particular, in this example, as described above, it is necessary for the transmission cable to the sub-substrate to pass through the narrow hinge portion, so that the effect of reducing the wiring line is more significant.  The second reason is the difference in data rates of peripheral modules and microprocessors.  If the memory module is a 16-bit wide SDRAM operating at 66 MHz, the data transfer rate is 1 Gbps.  In the case of serial transmission, this must be done with a 1 GHz serial clock.  On the other hand, in a camera or a liquid crystal display device, a signal rate of about 200 Mbps, that is, a 200 MHz serial clock is sufficient.  Transmitting 1 GHz to the substrate of the cellular phone causes an increase in design cost and noise countermeasure component cost for proper signal transmission.  As described above, in the transmission system of FIG. 22, one feature is that multiplexed serial transmission is used between modules mounted on different boards, and parallel transmission is used between modules mounted on the same board.  Similarly, parallel transmission can be used between a plurality of modules (chips) mounted in one package, and multiplexed serial transmission can be used between modules (chips) mounted on a board mounted on the package.  In this transmission system, one of the features is that the signal transmission rate between modules connected in parallel is higher than the signal transmission rate between modules connected in series.  Of course, these features have been described with respect to common examples, and are determined in consideration of cost savings and trade off- trade-offs in individual systems, and serial transmission is between different boards and at lower speeds. It is not limited only to the transmission of the bit rate.  For example, even at a transmission rate of GHz or higher, if the system is originally performing high speed signal transmission such as a server or a router, the design cost for performing high speed signal transmission and the increase in the noise countermeasure parts cost may not be so great. In this case, application of the present invention becomes easy.  In the case of transmission within the same substrate, serial transmission may be performed when the package cost can be greatly reduced by reducing the number of pins of the integrated circuit, or when the substrate cost can be greatly reduced by reducing the number of circuit board layers. Sometimes it is suitable.  

General Purpose Processor, Signal Processing Processor, Application Specific Integrated Circuit (ASIC), Gate Array, Field Programmable Gate Array (FPGA), Image Processing Processor, Semiconductor Memory, Memory Module, Liquid Crystal Display, Plasma Display, Camera Module, Sound Source The present invention can be applied to a chip or the like, a computer system connected to a printed board or a cable, a portable appliance system, a consumer electronic system, a system in a package, or a package that is a system.

Claims (21)

An integrated circuit device for multiplexing parallel data of a plurality of parallel interfaces to serial data, A selected parallel interface comprising a storage device, a signal transmission circuit for outputting data stored in the storage device by one bit to a transmission path connected to the integrated circuit device, and parallel data of the plurality of parallel interfaces. And a transmission programmer for issuing a control signal for notifying the interface signal selector of an interface signal selector for outputting parallel data of the data to the storage device. The method of claim 1, And the plurality of parallel interfaces have at least one of a transmission frequency, a bit width, a configuration of a control signal, and at least one of transmission and reception protocols. The method of claim 1, The transfer program detects a change of predetermined one or a plurality of bits of data included in parallel data of the parallel interface, and selects the parallel interface having the change as the parallel interface to be selected by the interface signal selector. Integrated circuit device for determining. The method of claim 1, The transfer programr receives an external selection signal indicative of the necessity of selection for each of the plurality of parallel interfaces from an external device, and determines a parallel interface to be selected by the external selection signal. Integrated circuit device. The method of claim 1, And the transmission programmer holds first information about a transmission frequency and a bit width of each of the plurality of parallel interfaces, and generates the selection signal based on the first information. The method of claim 5, And the transfer programr also holds second information about the priority of a plurality of parallel interfaces, and generates the selection signal based on the first information and the second information. The method of claim 1, And the memory device stores information for specifying the serialized parallel interface. An integrated circuit device for recovering parallel data of a plurality of parallel interfaces multiplexed from serial data, A first memory device for storing serial data received from a transmission path connected to the integrated circuit device, a second memory device for separately storing serial data stored in the first memory device in parallel data for each parallel interface; A reception programmer for controlling the transmission from the first storage device to the second storage device based on a predetermined multiplexing rule, wherein the predetermined multiplexing rule is set in advance or other integration which transmits the serial data. An integrated circuit device, which is notified from the circuit device. A first integrated circuit device, a second integrated circuit device for performing serial transmission with the first integrated circuit device, and a third integrated circuit device for performing parallel transmission with the second integrated circuit device; Extracts the partial data to be transmitted to the third integrated circuit device from the first serial data serially transmitted from the first integrated circuit device, and transmits the partial data to the third integrated circuit device in parallel; And an integrated circuit device serializes data transmitted in parallel from the third integrated circuit device and serially transmits the data serially transmitted to the first integrated circuit device as second serial data. The method of claim 9, And the second integrated circuit device has a first register and specifies the partial data to be extracted from the first serial data based on the information of the first register. The method of claim 10, And the information stored in the first register is read at the time of startup of the signal transmission system. The method of claim 10, The information stored in the first register is set for each process executed by the signal transmission system. The method of claim 9, And the second integrated circuit device has a second register, and serializes data transmitted in parallel from the third integrated circuit device based on the second register information to generate the second serial data. The method of claim 13, And the information stored in the second register is read at the start of the signal transmission system. The method of claim 13, The information stored in the first register is set for each process executed by the signal transmission system. The method of claim 9, The first integrated circuit device transmits a first clock signal for decoding the first serial data to the second integrated circuit device, and the second integrated circuit device is configured to transmit the second serial data. And a second clock signal to decode the signal. The method of claim 9, And a fourth integrated circuit device for performing serial transmission with the second integrated circuit device, wherein the second integrated circuit device stores second serial data corresponding to the first serial data serially transmitted from the first integrated circuit device. A signal transmission system for serial transmission to the fourth integrated circuit device. The method of claim 17, And the second integrated circuit device generates second serial data by replacing bits corresponding to the partial data among the first serial data with predetermined bits. A signal transmission system in which a plurality of integrated circuit devices are mounted on a substrate, The plurality of integrated circuit devices include first to fourth integrated circuit devices, and data transmission between the first integrated circuit device and the second integrated circuit device is defined by a first parallel interface, and the third integrated circuit. Data transmission between the device and the fourth integrated circuit device is defined by a second parallel interface, the transmission frequency of the first parallel interface is higher than the transmission frequency of the second parallel interface, and the first integrated circuit and the second parallel interface. The data transfer between integrated circuits transfers parallel data of the first parallel interface in parallel, and the data transfer between the third integrated circuit device and the fourth integrated circuit device performs serial transfer of parallel data of the second parallel interface. Signal transmission system. In a signal transmission system in which a plurality of integrated circuit devices are mounted on a plurality of substrates, The plurality of integrated circuit devices include a first to fourth integrated circuit device, wherein the first to third integrated circuit device is mounted on a first substrate, the fourth integrated circuit device is mounted on a second substrate, Data transmission between the first integrated circuit device and the second integrated circuit device is defined by a first parallel interface, and data transmission between the third integrated circuit device and the fourth integrated circuit device is defined by a second parallel interface. The data transfer between the first integrated circuit device and the second integrated circuit device includes parallel transmission of parallel data of the first parallel interface, and data transmission between the third integrated circuit device and the fourth integrated circuit device. And serial transmission of parallel data of the second parallel interface. In a signal transmission system in which a plurality of integrated circuit devices are mounted on a plurality of substrates, The plurality of integrated circuit devices may include first to fourth integrated circuit devices, wherein the first to third integrated circuit devices are mounted on the same package, and at the same time, the package is mounted on a substrate. Is mounted on the substrate, data transmission between the first integrated circuit device and the second integrated circuit device is defined by a first parallel interface, and data transmission between the third integrated circuit device and the fourth integrated circuit device is performed. A data transfer between the first integrated circuit device and the second integrated circuit device, defined by a second parallel interface, transfers parallel data of the first parallel interface in parallel, and transmits the parallel data of the first integrated circuit device to the fourth integrated circuit device. Data transmission between integrated circuit devices is a signal transmission system for serial transmission of the parallel data of the second parallel interface.

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