KR20070030002A - High efficiency analog-digital converter - Google Patents

Abstract

A high efficiency analog-digital converter is provided to reduce a size of the whole chip in the converter by reducing the number of capacitor arrays which perform a bit conversion by charging a voltage in the analog-digital converter. A high efficiency analog-digital converter includes a charging/discharging circuit, a voltage recording circuit(10), and a voltage switch circuit(SR1,SR2,SR3). The charging/discharging circuit has five capacitors and five charge switches which are connected to an input terminal of a comparator(COM2) in parallel. The voltage recording circuit(10) stores a voltage charged in the charging/discharging circuit every upper four bit and lower four bit. The voltage switch circuit(SR1,SR2,SR3) performs switching for bit conversion of the upper four bit and the lower four bit.

Description

High Efficiency Analog-to-Digital Converters {HIGH EFFICIENCY ANALOG-DIGITAL CONVERTER}

1 is a view showing a circuit configuration of a conventional analog-to-digital converter,

2 is a circuit diagram illustrating a high efficiency analog-to-digital converter according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: voltage memory circuit, 20: control circuit,

COM2: Comparator. 2 ⁰ C, 2 ⁰ C, 2 ¹ C, 2 ² C, 2 ³ C: capacitors,

S _-1 , S _0, S _1, S _2, S ₃ : Charge switch, S ^R1 , S ^R2 , S ^R3 : Voltage switch,

S _SP : Ground switch.

The present invention relates to an analog-to-digital converter, and more particularly, to a high-efficiency analog-to-digital converter for implementing a SAR analog-to-digital converter (ADC) in a low power area.

As is well known, various digital signal processing apparatuses that receive an analog signal, such as a sensor device, use an analog-to-digital converter (ADC) as a means for converting an input analog signal into a digital signal.

That is, Figure 1 is a diagram showing the circuit configuration of a conventional analog-to-digital converter.

The analog-to-digital converter shown in FIG. 1 is a weighted-C SAR analog-to-digital converter in which a plurality of capacitors (2 ⁰ C to 2 ⁿ C) are connected in parallel to the non-inverting terminal (+) of the comparator COM1, respectively. Each capacitor (2 ⁰ C to 2 ⁿ C) is connected to a plurality of charge switches (S- ₁ , S _{0 to} S _n ) so that the ground side or input voltage (V _IN ) It is connected to the voltage switch (S ^R ) for selectively switching the voltage (V _REF ).

In addition, the non-inverting terminal (+) of the comparator (COM1) is connected to the ground switch (S _SP ) that is switched to the ground side, the inverting terminal (-) is directly connected to the ground side, the output through the output terminal The voltage V _O is generated.

On the other hand, the plurality of capacitors (2 ⁰ C ~ 2 ⁿ C) is increased by 2 times as the bit increases based on the basic capacity, and in the case of N bits, the capacity can be increased by 2 N times.

The SAR analog-to-digital converter performs a process of digitally converting an analog signal through three steps of sampling, holding, and redistribution. In the sampling step, the voltage switch S _R is applied to an input voltage. In addition to switching to the (V _IN ) side, in a state where the ground switch S _SP is switched and grounded, a plurality of charge switches S- ₁ and S _{0 to} S _n are respectively switched to switch all capacitors (2 ⁰ C). 2 ⁿ C) are charged by the input voltage V _IN , respectively.

Further, in the holding step, the ground switch S _SP is switched off to be separated from the ground, and the plurality of charge switches S- ₁ , S _{0 to} S _n are switched to the ground side, respectively, so that the non-inverting of the comparator COM1 is performed. The voltage (V _X ) input to the terminal (+) becomes the negative input voltage (-V _IN ).

Next, in the distribution step, after switching the voltage switch S _R to the reference voltage V _REF , a charge switch (MSB) of the plurality of charge switches S ₋₁ , S _{0 to} S _n ( S _n ) to LSB, the charge switch S ₋₁ , which is sequentially connected to the reference voltage V _REF . First, when the charge switch S _n is connected, the input voltage V of the comparator COM1 is connected. _X ) value, the output voltage (V _O ) value of the comparator (COM1) is a "High" signal is output when the input voltage (V _X ) is greater than "0V", than "0V" If it is small, a "low" signal is output.

When the output voltage V _O is “high”, the corresponding charge switch S _n is switched back to the ground side, and when the output voltage V _O is “low”, the state connected to the reference voltage V _REF is maintained. In this way, the positions of the switches are also determined in the same manner as in the above-described charge switches S _{n-1 to} S ₀ , and the positions of the switches are converted digital values.

On the other hand, CMOS circuits have many advantages such as low power consumption and high noise resistance. Recently, CMOS circuits have been implemented not only in digital circuits but also in analog circuits. It is suitable for implementation of analog-to-digital converters up to 10 bits because it is suitable and is less affected by the stray capacitance of the capacitor array.

However, in the conventional analog-to-digital converter, in the case of N bits, the size of the capacitor corresponding to the MSB becomes 2N times the size of the capacitor corresponding to the LSB. For example, when implementing an analog-digital converter of 10 bits, Since the capacitor of the capacitor is 1,024 times larger than the capacitor of the smallest capacity, the area of the capacitor increases exponentially as the number of bits increases, which requires a large silicon area in a circuit implemented in CMOS.

Accordingly, the present invention has been made in view of the above-described conventional situation, and an object thereof is to efficiently reduce the number of capacitors by a charge redistribution method and to implement an analog-to-digital converter having a high efficiency analog-to-digital converter. To provide.

In order to achieve the above object, according to the present invention, a charge-discharge circuit having five capacitors and a charge switch each connected in parallel to the input terminal side of the comparator, and the voltage charged in the charge-discharge circuit and the upper 4 bits Provided is a high-efficiency analog-to-digital converter characterized by consisting of a voltage memory circuit for storing the next lower 4 bits, and a voltage switch circuit for switching the bit of the upper 4 bits and the lower 4 bits.

Hereinafter, the present invention configured as described above will be described in detail with reference to the accompanying drawings.

That is, Figure 2 is a diagram showing the circuit configuration of a high efficiency analog-to-digital converter according to the present invention.

As shown in FIG. 2, the high-efficiency analog-to-digital converter according to the present invention includes five capacitors 2 ⁰ C, 2 ⁰ C, 2 ¹ C, in parallel to the non-inverting terminals (+) of the comparator COM2, respectively. 2 ² C, 2 ³ C) are connected, and each of the capacitors (2 ⁰ C, 2 ⁰ C, 2 ¹ C, 2 ² C, 2 ³ C) has five charge switches (S _-1 , S _0, S _1, S _{2, and} S ₃ ) are respectively connected correspondingly.

One end of the five charge switches S- ₁ , S _0, S _1, S _{2, and} S ₃ is connected to the ground side, and the other end of the five charge switches S- ₁ , S _0, S _1, S _{2, and} S ₃ is connected to the first to third voltage switches S ^R1 , S ^R2 , S ^R3 is commonly connected to each other, and the first voltage switch S ^R1 switches the application of the input voltage V _IS , and the second voltage switch S ^{R2 is} connected to the reference voltage V _REF . The third voltage switch S ^R3 is adapted to switch the application of the reference voltage / 16 (V _REF / 16).

In addition, the non-inverting terminal (+) of the comparator (COM1) is connected to the ground switch (S _SP ) which is switched to the ground side, and is connected to the voltage memory circuit 10, the inverting terminal (-) of the ground Directly connected to the side, the output end thereof is connected to the control circuit 20.

When the analog-to-digital converter according to the present invention is applied to an analog device such as a small sensor, it is often implemented in the same chip as the sensor, so it should not occupy a large area. Use charge redistribution and reduce the overall area by reducing the number of capacitors in the weighted capacitor array to five. In other words, by using a three-bit or four-bit charge redistribution method to obtain an 8-bit resolution.

The voltage memory circuit 10 stores the voltage of the upper plate of the capacitor arrays 2 ⁰ C, 2 ⁰ C, 2 ¹ C, 2 ² C, 2 ³ C after the conversion of the upper four bits is completed. This voltage is used to convert the next four bits.

The conversion to the next lower 4 bits is performed by connecting each of the charge switches S- ₁ , S _0, S _1, S _{2, and} S ₃ to the ground side with the ground switch S _SP open. Each capacitor 2 ⁰ C, 2 ⁰ C, 2 ¹ C, 2 ² C, 2 ³ C is charged with the voltage stored in the voltage memory circuit 10.

Next, in the state where the third voltage switch S _{R3 is} connected to the reference voltage / 16 (V _REF / 16), the respective charge switches S- ₁ , S _0, S _1, S _{2, and} S ₃ ) is the MSB of the charge switch (S ₃₎ from the LSB of the charge switch (S _-1) sequentially to the reference voltage / 16 (V _REF / 16) connected with the lower four bits of the car by performing the bit conversion performed by the conversion You lose.

Therefore, after the upper 4 bits are converted, the next lower 4 bits are converted, so that a total of 8 bits are converted.

On the other hand, the area for each component appearing when the analog-to-digital converter according to the present invention is manufactured as a practical chip, the actual area for each block for the conventional SAR analog-to-digital converter and the analog-to-digital converter of the present invention When calculated and compared numerically, in the conventional SAR analog-to-digital converter, the area of the capacitor array is 1.152 mm2, the area of the charge switch portion is 0.00195 mm2, and the total area of the analog block occupies 1.15395 mm2. It occupies an area of 0.0225 mm 2 and the total area of the chip occupies an area of 1.17645 mm 2.

On the other hand, in the analog-to-digital converter of the present invention, the area of the capacitor array portion is 0.072 mm 2, the area of the voltage memory circuit is 0.0425 mm 2, and the area of the charge switch part is 0.00225 mm 2, so that the total area of the analog block is 0.10745 mm 2. On the other hand, since the digital block portion requires an area of 0.04 mm 2, the total area of the chip to which the present invention is applied occupies an area of 0.14745 mm 2.

That is, the area of the capacitor array of the present invention is reduced by about 16 times the area of the capacitor array of the conventional analog-to-digital converter, and considering the voltage storage circuit requiring an area of 0.0425 mm2, the analog block portion is About 1 times the area can be reduced.

In addition, the digital block portion of the analog-to-digital converter of the present invention increases the number of states that can control more voltage than in the prior art, but has a large effect on the overall chip area because the difference in area is not large compared to the conventional. In consideration of the total chip area, the chip size can be reduced by about 8 times.

On the other hand, the present invention is not limited to the above-described typical preferred embodiments, but can be carried out in various ways without departing from the gist of the present invention, various modifications, alterations, substitutions or additions are common in the art Those who have knowledge will easily understand. If the implementation by such improvement, change, replacement or addition falls within the scope of the appended claims, the technical idea should also be regarded as belonging to the present invention.

As described above, according to the present invention, by configuring a voltage redistribution circuit capable of significantly reducing the number of capacitor arrays that perform bit conversion by charging a voltage in an analog-digital converter used in an analog device such as a sensor, This has the effect that it is possible to significantly reduce the overall chip size of the analog-to-digital converter.

Claims (4)

A charge / discharge circuit having five capacitors and a charge switch connected in parallel to the input terminal side of the comparator, A voltage memory circuit for storing the voltage charged in the charge / discharge circuit in the upper 4 bits and the lower 4 bits; And a voltage switch circuit configured to perform switching for bit conversion of the upper 4 bits and the lower 4 bits. The method of claim 1, The charge / discharge circuit has five capacitors connected in parallel to each of the non-inverting terminals of the comparator, and five charge switches are correspondingly connected to each capacitor, and the five capacitors and the charge switch are connected to the voltage. High-efficiency analog-to-digital converter characterized in that the common connection to the switch circuit. The method according to claim 1 or 2, The voltage switch circuit may include a ground switch for switching the five capacitors to the ground side, a first voltage switch for switching an application of an input voltage V _IS , a second voltage switch for switching an application of a reference voltage V _REF , And a third voltage switch for switching the application of reference voltage / 16 (V _REF / 16). The method of claim 3, wherein And said one end of the five charge switches is connected to the ground side and the other end thereof is commonly connected to the first to third voltage switches.

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