KR20070023847A - Semiconductor memory device having circuit for wafer burn in test mode and method for wafer burn in test - Google Patents

Abstract

A semiconductor memory device having a circuit for a wafer burn-in test mode and a wafer burn-in test method are provided to prevent the decrease of sensing stress among bit lines in a dummy cell block while executing a wafer burn-in test as a sense amplifier is not connected to the dummy bit lines biased at power voltage, bit line precharge voltage, or ground voltage. A semiconductor memory device having a circuit for a wafer burn-in test mode is composed of dummy cell blocks(DA1,DA2) having plural memory cells and plural dummy cells; plural normal memory cell blocks(A0~Ak) provided with plural memory cells and arranged between the dummy cell blocks; sense amplifier blocks(B0~Bk+1) disposed between the adjacent normal memory cell blocks and between the normal memory cell block and the dummy cell block; and a test sense amplifier(100) connected to dummy bit lines(BL0~BLn) which are formed in the dummy cell blocks and not connected with sense amplifiers(10,SA) of the sense amplifier blocks, to make test conditions of the dummy cell blocks similar to that of the normal memory cell blocks.

Description

Semiconductor memory device having circuit for wafer burn in test mode and method for wafer burn in test}

1 is a schematic diagram of a structure of a relaxed open bit line type memory cell array in a conventional semiconductor memory device.

2 is a schematic diagram of a structure of a memory cell array of a semiconductor memory device having a circuit for a wafer burn-in test mode in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

DA1, DA2: dummy cell block A0 to Ak: normal memory cell block

B0 ~ Bk + 1: Sense amplifier block 10, SA: Sense amplifier

100: test sense amplifier

The present invention relates to a semiconductor memory device, and more particularly, to a circuit for a wafer burn-in test mode and a wafer burn-in test method for use in a test for initial failure elimination of a semiconductor memory device.

In general, as semiconductor memory devices are highly integrated and high performance, cell array structures including memory cells, bit lines, word lines, sense amplifiers, and the like included in the semiconductor memory devices have also changed.

In the case of DRAM, an open bit line method, a relax open bit line method, a folded bit line method, or the like as a sense amplifier method. Is used.

Here, the open bit line method, as is well known, can arrange the memory cells at both the intersections of the bit line and the word line, thereby reducing the area of the memory cell portion. There is a burden of placing a sense amplifier for every bit line pitch, which makes layout of the sense amplifier extremely difficult.

In the relaxed open bit line method, memory cells are disposed at all intersections of word lines and bit lines, and one sense amplifier is disposed within two bit line pitches. It is easier to design the layout of the sense amplifier than the open bit line method.

In the folded bit line method, since a memory cell may be disposed at only half of the intersection point of the word line and the bit line, the memory cell area is increased, thereby increasing the chip size. One sense amplifier is placed on four bit line pitches, which makes it easier to design than the open bit line method. It has a strong advantage against noise because a pair of bit lines is formed in one cell block.

As described above, the open bit line method has a problem that the open bit line method has a small memory cell area but the design dimension of the sense amplifier is very strict and the arrangement of the sense amplifier is difficult, whereas the folded bit line method is a sense amplifier. The design dimension of the circuit can be significantly relaxed, but there is a problem in that the area of the memory cell is large and the chip size is large. Therefore, an appropriate method is adopted according to the implementation purpose or the user's request.

1 illustrates a structure of a relaxed open bit line memory cell array in a conventional semiconductor memory device.

As shown in FIG. 1, a memory cell array in a conventional semiconductor memory device includes k + 1 (k is an arbitrary natural number) normal memory cell blocks A0 to Ak and first and second dummy. ) Cell blocks DA1 and DA2.

The first dummy cell block DA1 is positioned at one edge of the normal memory cell blocks A0 to Ak, that is, in the direction of the 0th normal memory cell block A0, and the second dummy cell block DA2 is It is located at the other edge of the normal memory cell blocks A0 to Ak, that is, in the direction of the kth normal memory cell block Ak.

Sense amplifier blocks B0 to Bk + 1 including a plurality of sense amplifiers SA are respectively disposed between the normal memory cell blocks A0 to Ak and the first and second dummy cell blocks DA1 and DA2. And bit lines BL formed in the normal memory cell blocks A0 to Ak and the first and second dummy cell blocks DA1 and DA2 are connected to the sense amplifiers SA, respectively. .

The 0th normal memory cell block A0 will be described in detail as an example.

In the zeroth normal memory cell block A0, a plurality of memory cells are arranged in a predetermined structure. For example, the structure is connected to the normal bit line BL in the column direction and to the word line in the row direction.

The 0th sense amplifier block B0 and the 1st sense amplifier block B1 are disposed on both sides of the 0th normal memory cell block A0. The normal bit lines BL formed in the zeroth normal memory cell block A0 are sense amplifiers SA of the zeroth sense amplifier block B0 and sense amplifiers of the first sense amplifier block B1. (SA) are alternately connected to each other. That is, when the 0th normal bit line BL0 in the 0th normal memory cell block A0 is connected to the sense amplifier SA in the 0th sense amplifier block B0, the 1st normal bitline BL1 is connected. ) Is connected to the sense amplifier SA in the first sense amplifier block B1. Of course, the opposite case, if the 0th normal bit line BL0 in the 0th normal memory cell block (A0) is connected to the sense amplifier (SA) in the first sense amplifier block (B1), the first The burn normal bit line BL1 may be connected to the sense amplifier SA in the sense amplifier block B0.

The first sense amplifier 10 in the zeroth sense amplifier block B0 is the first bit line BL0 in the first dummy cell block DA1 and the first in the zeroth normal memory cell block A0. It is connected to the bit line BL0. The sense amplifier 10 is laid out on two bit line pitches. That is, the sense amplifiers SA in the zeroth sense amplifier block B0 including the sense amplifier 20 are located in the normal memory cell block A0 located on the right side of the zeroth sense amplifier block B0. The odd-numbered bit lines BL1, BL3, BLn and the even-numbered bit lines BL0, BL2, BLn-1 in the first dummy cell block DA1 are respectively connected. Alternatively, the sense amplifiers SA in the zeroth sense amplifier block B0 may have even-numbered bit lines BL0 and BL2 in the normal memory cell block A0 positioned at both sides of the zeroth sense amplifier block B0. And BLn-1 and the odd-numbered bit lines BL1, BL3, and BLn in the first dummy cell block DA1. Here, n is assumed to be odd.

As described above, since the sense amplifiers SA of FIG. 1 are laid out on two bit line pitches, there is an advantage in that the sense amplifiers are easily aligned as compared to the sense amplifiers laid out on one bit line pitch.

In this case, the bit lines in the dummy cell blocks DA1 and DA2 positioned at both edges of the normal memory cell blocks A0 to Ak are connected to the sense amplifiers SA in the normal sense amplifier blocks B0 to Bk + 1. The bit lines are normal bit lines connected to memory cells, and the bit lines not connected to the sense amplifiers SA are dummy bit lines connecting dummy cells. In the case of FIG. 1, even-numbered bit lines BL0, BL2, ..., BLn-1 in the first dummy cell block DA1 are normal bit lines, and odd-numbered bit lines BL1, BL3, ..., BLn) is a dummy bit line. Meanwhile, odd-numbered bit lines BL1, BL3, ..., BLn in the second dummy cell block DA2 are normal bit lines, and even-numbered bit lines BL0, BL2, ... BLn-1 are dummy. Bit line.

Since the dummy bit lines BL1, BL3, and BLn are in a floating state, in order to prevent this, the dummy bit lines BL1, BL3, and BLn are commonly applied with a power supply voltage, a bit line precharge voltage VBL or a ground voltage.

The operation and structure of the open bit line type semiconductor memory device in which the sense amplifier SA is laid out on two bit line pitches as described above are well known to those skilled in the art. Since it is known, further description thereof will be omitted.

In the open bit line type semiconductor memory device as described above, when the wafer burn-in test for removing the initial defect is performed, the problem of under stress of the bit lines in the dummy cell block in the wafer burn-in mode is dominant. . Wafer burn-in tests are those that are higher than typical operating voltages (e.g., 5.0V) in high temperature (e.g., 125 degrees Celsius) environments that are worse than the conditions under which the product will be used prior to supplying the semiconductor device to the end consumer. Is a test for determining whether there is an abnormality in the semiconductor device, and is mainly performed in a post-production process of the semiconductor device.

In this wafer burn-in test, the sensing stresses between the bit lines in the dummy cell block are not connected to the dummy bit lines biased by the supply voltage or the bit line precharge voltage or the ground voltage. Is less than that of normal memory cell blocks. Therefore, even if the wafer burn-in test is performed, defects in the dummy cell block may not be properly filtered, which may cause quality defects of the semiconductor memory device.

Accordingly, an object of the present invention is to provide a semiconductor memory having a circuit for a wafer burn-in test mode for performing a wafer burn-in test under the same or similar conditions as a center memory cell block to solve the above problems. An apparatus and a wafer burn-in test method are provided.

Another object of the present invention is to sense between the bit lines in the dummy cell block during wafer burn-in test because the sense amplifier is not connected to the dummy bit lines biased by the supply voltage or bit line precharge voltage or ground voltage. The present invention provides a semiconductor memory device and a wafer burn-in test method including a circuit for a wafer burn-in test mode to solve a problem in which a stress is less than that of normal memory cell blocks.

It is still another object of the present invention to provide a semiconductor memory device and a wafer burn-in test method including a circuit for a wafer burn-in test mode capable of reducing or minimizing quality defects of an open bit line type semiconductor memory device.

In accordance with an aspect of the present invention, a semiconductor memory device includes: dummy cell blocks each including a plurality of memory cells and dummy cells; A plurality of normal memory cell blocks having a plurality of memory cells and disposed between the dummy cell blocks; Sense amplifier blocks disposed between normal memory cell blocks adjacent to each other and between normal memory cell blocks and dummy cell blocks adjacent to each other; And a dummy not connected to sense amplifiers constituting the sense amplifier blocks among bit lines inside the dummy cell blocks to make the test condition of the dummy cell blocks similar to the test condition of the normal memory cell blocks. And a test sense amplifier connected to the bit line.

Here, the test may be a wafer burn-in test, and the bias voltage applied to prevent the dummy bit line from floating during the wafer burn-in test may be stopped.

In addition, the test sense amplifier may sense a signal applied to the dummy bit line at the same time as the sensing time of the sense amplifiers constituting the sense amplifier blocks in the wafer burn-in mode.

A wafer burn-in test method of a semiconductor memory device according to an aspect of the present invention for achieving the above objects is a test condition of the dummy cell blocks each having a plurality of memory cells and dummy cells, the plurality of memory cells and the dummy To be similar to the test condition of a plurality of normal memory cell blocks disposed between cell blocks, dummy bit lines not connected to sense amplifiers constituting the sense amplifier blocks among the bit lines inside the dummy cell blocks. And a test sense amplifier connected to the sensing circuit, in the wafer burn-in mode, a signal applied to the dummy bit line is sensed at substantially the same time as a sensing time of the sense amplifiers constituting the sense amplifier blocks.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Since the descriptions in the following embodiments are merely illustrated and limited by way of example and without intention other than the intention of a person having ordinary knowledge in the art to which the present invention pertains more thorough understanding of the present invention, It should not be used to limit the scope.

2 is a schematic diagram of a structure of a memory cell array of a semiconductor memory device having a circuit for a wafer burn-in test mode in accordance with an embodiment of the present invention.

Referring to FIG. 2, the semiconductor memory device includes dummy cell blocks DA1 and DA2, normal memory cell blocks A0, A1,... Ak, sense amplifier blocks B0, B1, ..., Bk + 1) and a circuit for a test mode.

The dummy cell blocks DA1 and DA2 each include a plurality of memory cells and dummy cells. The odd-numbered bit lines BL1, BL3, ... of the first dummy cell block DA1 among the dummy cell blocks are the sense amplifier blocks B0, B1, ..., Bk + 1. The dummy bit lines are not connected to the dummy bit lines, and even-numbered bit lines BL0, BL2,... Of the second dummy cell block DA2 are dummy bit lines.

The normal memory cell blocks A0, A1,..., Ak are provided with a plurality of memory cells and are disposed between the dummy cell blocks DA1, DA2. The bit lines BL0, BL1, ..., BLn of the normal memory cell blocks A0, A1, ..., Ak are the sense amplifier blocks B0, B1, ..., Bk + 1. Is connected to the sense amplifier SA. For example, even-numbered bit lines BL0, BL2, ... of the normal memory cell block A0 are connected to one sense amplifier of the sense amplifier block B1, respectively, and odd-numbered bits of the normal memory cell block A0 are connected. The lines BL1, BL3, ... are connected to one sense amplifier of the sense amplifier block B0, respectively.

The sense amplifier blocks B0, B1, ..., Bk + 1 are disposed between normal memory cell blocks adjacent to each other, and between normal memory cell blocks and dummy cell blocks adjacent to each other. For example, the sense amplifier block B0 of the sense amplifier blocks B0, B1, ..., Bk + 1 is disposed between the normal memory cell block A0 and the dummy cell block DA1, and is a sense amplifier block. B1 is disposed between the normal memory cell block A0 and the normal memory cell block A1.

The test mode circuit includes a test sense amplifier 100. The test sense amplifier 100 performs the test conditions of the dummy cell blocks DA1 and DA2 to be similar to the test conditions of the normal memory cell blocks A0, A1,..., Ak. Of the bit lines in the dummy cell blocks DA1 and DA2, the dummy bit lines BL1, BL3,... Which are not connected to the sense amplifiers SA constituting the sense amplifier blocks B0 and Bk + 1. .)

The test is preferably a wafer burn-in test for initial defect removal.

In the test mode circuit, bias voltages VBL1 and VBL2 such as a power supply voltage, a bit line precharge voltage, or a ground voltage are supplied to prevent floating of the dummy bit lines BL1, BL3,... Alternatively, switches SW1 and SW2 may be further provided to cut off. The switches SW1 and SW2 are turned on when the test sense amplifier 100 is disabled, that is, when the test sense amplifier 100 does not perform a sensing operation. As can be seen, the bias voltages VBL1 and VBL2 are supplied. However, when the test sense amplifier 100 is enabled, the switches SW1 and SW2 are turned off to cut off the supply of the bias voltages VBL1 and VBL2. The switches SW1 and SW2 may be implemented with, for example, a MOS transistor.

The operation in the wafer burn-in test mode of the semiconductor memory device having the wafer burn-in test mode circuit will be briefly described as follows.

Initially, the bias voltages VBL1 and VBL2 are supplied to the dummy bit lines BL1, BL3,..., And the wafer burn-in enable signal PWBE is applied when the wafer burn-in test mode is entered. At the same time or sequentially, the switches SW1 and SW2 are turned off to cut off the supply of the bias voltages VBL1 and VBL2. The data stored in the dummy cells of the dummy cell block are loaded on the dummy bit lines BL1, BL3, ... by the sensing trigger signal, and the input signal DA1 of the test sense amplifier is loaded. The signals input from the dummy bit lines BL1, BL3, ..., and the signals input from the dummy bit lines BL1, BL3, ... of DA2 are signals having complementary data, and are the test sense amplifiers 100 for the test. Is sensed by Sense amplifier blocks B0, B1, ... in wafer burn-in mode for portions other than those sensed by the test sense amplifier 100, i.e., normal memory cell blocks A0, A1, .... ) Is the same as the conventional operation.

In this case, the test sense amplifier 100 is at the same time as the sensing time of the sense amplifier SA constituting the sense amplifier blocks B0, B1, ... in the wafer burn-in mode, the dummy bit line. The signal applied to (BL1, BL3, ... of DA1 and BL0, BL2, ... of DA2) is sensed.

In this way, the sensing stress of the test sense amplifier 100 is applied to the normal bit lines (BL0, BL2, ... of DA1 and BL1, BL3, ... of DA2) of the dummy cell blocks DA1 and DA2. As a result, a condition similar to the sensing stress applied to the bit lines of the normal memory cell blocks A0, A1,...

Referring to FIG. 2, a wafer burn-in test method of a semiconductor memory device according to example embodiments of the inventive concepts will be described below.

A wafer burn-in test method of a semiconductor memory device according to an embodiment of the present invention includes a test condition of dummy cell blocks DA1 and DA2 each including a plurality of memory cells and a dummy cell, and including a plurality of memory cells. In order to be similar to the test condition of the plurality of normal memory cell blocks A0, A1,... Ak disposed between the dummy cell blocks DA1 and DA2, the dummy cell blocks DA1 and DA2 are provided. Test sense connected to dummy bit lines BL1, BL3, ... of DA1 and BL0, BL2, ... of DA2 which are not connected to sense amplifiers constituting the sense amplifier blocks among the internal bit lines. The amplifier 100 is applied to the dummy bit line at the same time as the sensing time of the sense amplifier constituting the sense amplifier blocks B0, B1, ..., Bk + 1 in the wafer burn-in mode. Sense the signal.

Thus, dummy cell blocks can be burned-in under similar conditions as in normal memory cell blocks. Therefore, it is possible to eliminate the initial defects, thereby reducing the quality defects.

As described above, the semiconductor memory device and the wafer burn-in test method including the circuit for the wafer burn-in test mode according to the embodiment of the present invention are not limited to the above-described embodiments, and are variously designed without departing from the basic principles of the present invention. It will be apparent to those skilled in the art to which the present invention pertains.

As described above, the present invention provides a semiconductor memory device having a wafer burn-in test mode circuit and a wafer burn-in test method, whereby the dummy memory cell block can be subjected to wafer burn-in test under the same or similar conditions as the center memory cell block. have.

In addition, the present invention provides a semiconductor memory device having a wafer burn-in test mode circuit and a wafer burn-in test method, whereby a sense amplifier is separately provided to dummy bit lines biased by a power supply voltage or a bit line precharge voltage or a ground voltage. Due to the disconnection, the sensing stress between the bit lines in the dummy cell block during the wafer burn-in test may be reduced compared to the normal memory cell blocks.

In addition, the present invention can provide a semiconductor memory device and a wafer burn-in test method having a circuit for a wafer burn-in test mode, it is possible to reduce or minimize the poor quality of the open bit line-type semiconductor memory device.

Claims (6)

In a semiconductor memory device: Dummy cell blocks each having a plurality of memory cells and dummy cells; A plurality of normal memory cell blocks having a plurality of memory cells and disposed between the dummy cell blocks; Sense amplifier blocks disposed between normal memory cell blocks adjacent to each other and between normal memory cell blocks and dummy cell blocks adjacent to each other; And In order to make the test condition of the dummy cell blocks similar to the test condition of the normal memory cell blocks, dummy bit lines not connected to sense amplifiers constituting the sense amplifier blocks among the bit lines inside the dummy cell blocks. And a test sense amplifier connected to the semiconductor memory device. The method of claim 1, And the test is a wafer burn-in test. The method of claim 2, And a bias voltage applied to prevent the dummy bit line from floating during the wafer burn-in test. The method of claim 3, And the test sense amplifier senses a signal applied to the dummy bit line at a time substantially equal to a sensing time of a sense amplifier constituting the sense amplifier blocks in a wafer burn-in mode. In the wafer burn-in test method of a semiconductor memory device: In order to make the test condition of the dummy cell blocks each having a plurality of memory cells and dummy cells similar to the test condition of the plurality of normal memory cell blocks having a plurality of memory cells and disposed between the dummy cell blocks, A test sense amplifier is connected to a dummy bit line which is not connected to the sense amplifiers constituting the sense amplifier blocks among the bit lines in the dummy cell blocks to configure the sense amplifier blocks in a wafer burn-in mode. And a signal applied to the dummy bit line at substantially the same time as the sensing time of the sense amplifier. The method of claim 5, And a bias voltage applied to prevent the dummy bit line from floating during the wafer burn-in test.

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