KR100961070B1 - Parallel testing apparatus and method for sram - Google Patents

Abstract

The present invention relates to an apparatus and method for parallel testing of SRAM, which is a parallel test apparatus for an SRAM divided into a plurality of memory cell groups, which is connected to a plurality of memory cell groups to determine whether a failed memory cell exists in each memory cell group. Provided are a parallel test apparatus and method for SRAM that includes a plurality of parallel test circuits for simultaneously testing based on various test patterns, each parallel test circuit being connected to a pair of bit lines in each group of memory cells.

SRAM, Parallel Test, Precharge, Predischarge

Description

Parallel testing apparatus and method of SRM A {PARALLEL TESTING APPARATUS AND METHOD FOR SRAM}

The present invention relates to an apparatus and method for parallel testing of SRAM. More particularly, the present invention relates to a block test unit that can detect various failures and reduce a number of errors and test times that occur during SRAM implementation using a low-volume semiconductor process. A parallel test apparatus and method.

1 is a flowchart illustrating a memory test sequence according to the prior art. Referring to FIG. 1, first, a process of sequentially accessing and testing all memory cells through external input / output of an SRAM memory is performed (S10). Then, a process of determining whether a faulty memory cell exists is performed (S20), and if there is a faulty memory cell, redundancy replacement is performed on the faulty memory cell (S30).

As such, the conventional memory test is performed by sequentially accessing the entire memory cell through the write and read process through the memory chip I / O. As the number of memory cells increases, the test time is proportional to the number of memory cells or squared. Inevitably increase. That is, when using MARCH, CHECKER, WALKING 0s, WALKING 1s, and Surround Disturb Patterns as the memory test algorithm, the time spent for the memory test increases in units of O (n) when n is the number of memory cells. In addition, when an algorithm test such as Exhaustive Test or GALPAT (Galloping Pattern) is used, test time is consumed in units of O (n ² ) because all patterns that can occur in the memory are tested. For example, exhaustive testing of 256 KB of memory requires testing at k × 256,000 × 256,000 at a minimum of k × 256,000 (k is the memory access time). This takes about 10 minutes at 2.56 ms, assuming k is 10 ns.

Meanwhile, in the display field, a System on Panel (SOP) system for integrating part and all of a circuit required for driving a display into a display panel is progressing. At present, such efforts are being made by LCD companies such as CG silicon, NEC, and Sharp in Japan. SOP can reduce power consumption and interconnection delay when applied to all systems using displays, but low temperature polysilicon (LTPS) used for SOP has low yield. There is this. In order to overcome such low yield, effective redundancy replacement is required through efficient testing, but the existing memory test is inefficient because it takes more time as the capacity is increased, and thus, the method of reducing the test time while increasing the accuracy of the memory test is urgently required. do.

The present invention is to overcome the above-mentioned conventional problems, the problem to be solved by the present invention is to provide a parallel test apparatus and method that can be tested at high speed, and can detect a variety of failures.

It is another object of the present invention to provide a parallel test apparatus and method using various test patterns that can detect various failures such as neighborhood sensitive faults and improve test detection rate.

It is still another object of the present invention to provide a parallel test apparatus and method capable of designing parallel test circuit units in groups so that they can be applied to hierarchical bit lines and divided word line memory structures.

According to an exemplary embodiment of the present invention, a parallel test apparatus for an SRAM divided into a plurality of memory cell groups, which is connected to the plurality of memory cell groups and simultaneously tests whether a failed memory cell exists in each memory cell group. A plurality of parallel test circuits are provided, and each parallel test circuit is provided with a parallel test apparatus of SRAM connected to a pair of bit lines of each memory cell group.

Each of the parallel test circuits is connected to the bit line pairs to precharge the bit line pairs; Precharge test circuitry for detecting a pull down fault of memory cells in the memory cell group; A predischarge circuit connected to the bit line pair for predischarge the bit line pair; And a predischarge test circuit for detecting a pull down fault of the memory cells in the memory cell group.

The precharge test circuit may include: a first switching unit and a second switching unit respectively connected to the bit line pair and driven according to an output of the bit line pair; And a first test input / output line pair connected to the first switching unit and the second switching unit, respectively, to output data corresponding to an output value of the bit line pair, wherein the predischarge test circuit includes the bit line. A third switching unit and a fourth switching unit respectively connected to the pair and driven according to an output of the bit line pair; And a second test input / output line pair connected to the third switching unit and the fourth switching unit, respectively, and outputting data corresponding to an output value of the bit line pair.

If there is no pull down failure in all the memory cells in the memory cell group, the first test input / output line pair has a complementary output value, and if there is no pull up failure in all the memory cells in the memory cell group, The two test input / output line pairs are characterized by having complementary output values.

The precharge test circuit further includes a precharge unit for precharging the first test input / output line pair and a precharge test enable unit for initiating the operation of the precharge test circuit, and configured to constitute the first switching unit. A gate terminal of the switching element is connected to the bit line, one terminal of the source / drain terminals is connected to any one of the first test input / output line pair, and the other terminal is connected to the precharge test enable unit. A gate terminal of the switching element constituting the second switching unit is connected to the bit line bar, one terminal of the source / drain terminals is connected to the other line of the first test input / output line pair, and the other terminal is the precharge test enable unit. The precharge unit is connected to one end of the first test input / output line pair and connected to the first test input / output line pair. A pair of source / drain terminals of a switching element constituting the precharge input / output line pair, the terminal connected to ground, and the other terminal connected to the first switching unit and the second switching unit. do.

The predischarge test circuit further includes a predischarge unit for predischarging the second test input / output line pair and a predischarge test enable unit for initiating an operation of the predischarge test circuit. The gate terminal of the switching element constituting the three switching unit is connected to the bit line, one terminal of the source / drain terminals is connected to any one of the second test input and output line pair, and the other terminal is the predischarge test enable A gate terminal of a switching element constituting the fourth switching unit is connected to a bit line bar, one terminal of a source / drain terminal is connected to the other line of the second test input / output line pair, and the other terminal is A predischarge test enable unit is connected to the predischarge test enable unit, and the second test input / output line Is connected to one end of the second test input / output line pair, and precharges the second test input / output line pair, one terminal of a source / drain terminal of a switching element constituting the predischarge test enable unit is connected to a driving power source, and the other terminal is It is connected to the third switching unit and the fourth switching unit.

According to another embodiment of the invention, partitioning an SRAM array into a plurality of memory cell groups; Parallel testing the plurality of memory cell groups simultaneously using a plurality of parallel test circuit units connected to the plurality of memory cell groups; Selecting a memory cell group in which a failed memory cell is detected; And sequentially testing all of the memory cells in the selected memory cell group.

 The parallel testing may include precharging or predischarging a pair of bit lines in each memory cell group, and then sensing pull-up or pull-down driving capability of the memory cells in each memory cell group.

Detecting pull-up or pull-down driving capability of the memory cells includes writing a test pattern in each memory cell group; Precharging or predischarging a pair of bit lines in each memory cell group; Selecting memory cells according to a test pattern in each memory cell group to read the test pattern; Detecting an output of a test input / output line pair for outputting data corresponding to an output value of the bit line pair; And determining whether a failed memory cell exists in each of the memory cell groups.

The determining of the existence of the failed memory cell may include determining that the failed memory cell does not exist in the memory cell group when the output of the test input / output line pair is a complementary output, and the output of the test input / output line pair is complementary. If not, the step of determining that there is a failed memory cell in the memory cell group.

Writing the random test pattern includes inputting the same data into each memory cell group, and selecting memory cells in each memory cell group selects all memory cells in each memory cell group It includes a step.

The writing of the random test pattern may include writing first data in a memory cell connected to a first word line of each memory cell group; And writing second data into memory cells connected to second word lines of each of the memory cell groups, wherein the first and second word lines are even and odd word lines, respectively, or the first and second word lines. The second word line is an odd-numbered and even-numbered wordline, respectively.

Selecting memory cells in each memory cell group includes selecting all bit line pairs in each memory cell group and sequentially selecting word lines in each memory cell group, wherein the test input / output line pairs The sensing of the output may be performed in the order in which the memory cells are selected.

The writing of the arbitrary test pattern may include writing first data to a memory cell connected to a first bit line pair of each memory cell group; And writing second data to a memory cell connected to a second bit line pair of each memory cell group, wherein the first and second bit line pairs are each even and odd bit line pairs, or The first and second bit line pairs are odd and even bit line pairs, respectively.

Selecting memory cells in each memory cell group may include selecting memory cells in which first data in each memory cell group is written and selecting memory cells in which second data in each memory cell group is written. And selecting the memory cells in which the first data is written, sequentially selecting a word line in each memory cell group, and selecting a pair of bit lines in each memory cell group by selecting the first bit line pair. The selecting of the memory cells in which the second data is written may include sequentially selecting a word line in each of the memory cell groups, a pair of bit lines in each of the memory cell groups, and selecting a second bit line pair. Detecting the output of the input / output line pairs is performed in the order that the memory cells are selected. do.

The recording of the arbitrary test pattern may include inputting second data into all memory cells in each memory cell group; Writing first data into a memory cell located at an intersection of a first bit line pair and a first word line of each memory cell group; And writing first data into a memory cell located at an intersection of a second bit line pair and a second word line of each memory cell group, wherein the first and second bit line pairs are each even and An odd bit line pair or the first and second bit line pairs are odd and even bit line pairs, respectively, and the first and second word lines are even and odd word lines, respectively, or the first And the second word line is an odd-numbered and even-numbered word line, respectively.

Selecting memory cells in each memory cell group may include selecting memory cells in which first data in each memory cell group is written and selecting memory cells in which second data in each memory cell group is written. And selecting the memory cells in which the first data is written, sequentially selecting word lines in each of the memory cell groups, and pairs of bit lines in each of the memory cell groups in the first and second bit line pairs. And alternately selecting the memory cells in which the second data is written, sequentially selecting word lines in each of the memory cell groups, and pairing bit lines in each of the memory cell groups. And alternately selecting according to the order of the first bit line pair, and detecting the output of the test input / output line pair. It characterized in that the memory cells are performed according to the selected order.

According to the present invention, the memory cell group in which the failed memory cell exists is found in parallel using the internal bit line of the SRAM, and the memory cells in the memory cell group in which the failed memory cell exists are sequentially tested. Test time is reduced compared to the test.

Precharge Test Through the predischarge test, the pull down driving capability or the pull up driving capability of the memory cells is sensed to determine whether the memory cells have failed, thereby increasing the test detection rate.

In addition, by performing parallel tests using various test patterns, various failures such as neighbor sensitive failures can be detected, thereby increasing the test detection rate.

In addition, by configuring the parallel test circuit unit to be designed in units of memory cell groups, an effect that can be applied to hierarchical bit lines and divided word line memory structures is obtained.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a schematic diagram of an SRAM parallel test apparatus according to the present invention, and FIG. 3 is a functional block diagram of an SRAM parallel test apparatus according to the present invention.

Referring to FIG. 2, first, an SRAM is divided into a plurality of memory cell groups, and the parallel test apparatus of the SRAM according to the present invention is connected to each memory cell group to simultaneously determine whether a failed memory cell exists in each memory cell group. It includes a number of parallel test circuits for testing. Each parallel test circuit is connected to a pair of bit lines in each group of memory cells.

In the present embodiment, for convenience of description, the SRAM shows only the first to fourth memory cell groups G1 to G4, and the first to fourth parallel test circuit units PTC1 to PTC4 represent the first to fourth memory cells. Connected to each group, each group of memory cells is tested in parallel at the same time.

Referring to FIG. 3, each parallel test circuit unit connected to each memory cell group includes a precharge circuit 100, a predischarge circuit 200, a precharge test circuit 300, a predischarge test circuit 400, and a column. Pass transistor 500.

The precharge circuit 100 is connected to a pair of bit lines in the memory cell group to perform a function of precharging the pair of bit lines, and the predischarge circuit 200 includes a pair of bit lines in the memory cell group. Is connected to the bit line to predischarge the pair of bit lines.

The precharge test circuit 300 precharges a pair of bit lines in a group of memory cells, and then measures whether the precharged bit line pair is sufficiently pulled down for a predetermined time to detect pull down faults of the memory cells. Play a role.

The predischarge test circuit 400 predischarges a pair of bit lines in a group of memory cells, and then measures whether the predischarged bit line pair is sufficiently pulled up for a predetermined time, thereby pulling up a pull up fault of the memory cells. It serves to detect.

The column pass transistor 500 separates the memory cell group under test from the existing local input / output line. In other words, the column pass transistor 500 may separate an arbitrary memory cell group from an adjacent memory cell group so that the test may be performed for each memory cell group. As a result, the precharge time, predischarge time and test time are reduced.

According to the parallel test apparatus of the SRAMs shown in FIGS. 2 and 3, first, a parallel test is performed on a plurality of memory cell groups simultaneously using a plurality of parallel test circuit units built in each memory cell group. The test time is reduced by sequentially testing all the memory cells only in the memory cell group in which the failed memory cell exists after performing the parallel test.

In the present exemplary embodiment, the parallel test circuit unit is included in each memory cell group as an example. However, the present invention is not limited thereto and the neighboring memory cell groups may be designed in such a manner that they share one parallel test circuit unit. It may be.

FIG. 4 is a diagram illustrating failure areas that may occur in 6T SRAM, and FIG. 5 is a table showing failure areas detectable by a precharge test and a predischarge test.

As shown in FIG. 4, a cell of an SRAM is composed of six transistors, and a memory cell fault may occur due to a transistor failure or weakening (1-6) and an interconnection failure (7-9). Can be. Failure or weakening of the transistor results in a decrease in the pull-up and pull-down capability of the memory cell.

FIG. 5 illustrates a failure site detectable by the precharge test and the predischarge test. Referring to FIG. 5, it can be seen that all possible failures shown in FIG. 4 can be detected through the precharge test and the predischarge test. That is, the 3, 4, and 8 parts of the 6T SRAM are components that pull down the 6T SRAM. To check the capability of these components, a precharge test is performed and the capabilities of the 1, 2, and 7 parts are checked. To do this, run the predischarge test. And, in order to check the capability of the 5, 6 and 9 parts, any of the precharge test and the predischarge test may be performed.

FIG. 6 is a schematic circuit diagram of a parallel test apparatus of SRAM, FIG. 7A is a precharge test circuit diagram of a parallel test apparatus of SRAM, and FIG. 7B is a predischarge test circuit diagram of a parallel test apparatus of SRAM.

Referring to FIG. 6, the parallel test apparatus includes a precharge circuit 100, a predischarge circuit 200, a precharge test circuit 300, a predischarge test circuit 400, and a column pass transistor 500. do.

7A and 7B, the precharge test circuit 300 is connected to the bit line pairs, respectively, and the first switching unit 310 (M1, M2, M3) and the second driving unit are driven according to the output of the bit line pair. It is connected to the switching unit 320: M4, M5, M6 and the first switching unit 310: M1, M2, M3 and the second switching unit 320: M4, M5, M6, respectively, and output values of the pair of bit lines And a first test input / output line pair 330 for outputting data corresponding to the first test input / output line pair 330. In addition, a precharge unit 340 for precharging the first test input / output line pair 330 and a precharge test enable unit 350 for starting an operation of the precharge test circuit 300 are included.

The predischarge test circuit 400 is connected to the bit line pairs, respectively, so that the third switching unit 410: M7, M8, M9 and the fourth switching unit 420: M10, M11 are driven according to the output of the bit line pair. M12 and third switches 410: M7, M8, and M9 and fourth switches 420: M10, M11, and M12, respectively, to output data corresponding to output values of the bit line pairs. Two test input / output line pairs 430. In addition, the predischarge unit 440 for predischarging the second test input / output line pair 430 and the predischarge test enable unit 450 for starting the operation of the predischarge test circuit 400 are included. do.

Referring to a process of performing a precharge test of a memory cell group using the precharge test circuit illustrated in FIG. 7A, first, arbitrary test pattern data is input to a memory cell group, and then a bit line and a bit bar line are set to VDD. Precharge and turn on the wordline according to the test pattern. Since the same data is stored in the selected memory cell in the memory cell group, the pair of bit lines outputs complementary data. That is, when all memory cells in the memory cell group are normal, any one of the first switching unit 310 (M1-M3) and the second switching unit 320: M4-M6 of the precharge test circuit is turned on. On, the remaining group is turned off, such that the first test input / output line pair 330 has outputs that are complementary to each other. However, if there is a pull-down failure in any memory cell in the memory cell group, either the bit line pair is high or one of the bit line pairs is weak, which causes the pull-down to fail below the threshold voltage Vth. I can't. As a result, the first test input / output line pair 330 has outputs that are not complementary to each other.

The process of performing the predischarge test of the memory cell group using the predischarge test circuit shown in FIG. 7B detects a pull-up failure in the same principle as the precharge test. However, since the bit line is pulled up to a maximum of VDD-| Vth |, the threshold voltages of the third and fourth switching units 410 and 420 of the predischarge circuit are set to VDD-2 | Vth |. To this end, as shown in FIG. 7B, the pull-up current switch M13 is used as an NMOS so that VDD-Vth are applied to the sources of the third and fourth switching units.

Looking at the configuration of the precharge test circuit 300 shown in FIG. 7A in detail, the precharge test circuit 300 includes a first switch 310 (M1, M2, M3), the second switch 320 (M4, M5) , M6), a first test input / output line pair 330, a precharge unit 340, and a precharge test enable unit 350. The gate terminal of the transistor constituting the first switching unit 310 is connected to the bit line, one terminal of the source / drain terminals is connected to any one of the first test input / output line pairs, and the other terminal is the precharge test in It is connected to the enable unit 350. The gate terminal of the transistor constituting the second switching unit 320 is connected to the bit line bar, one terminal of the source / drain terminals is connected to the other line of the first test input / output line pair, and the other terminal is precharge test enable. It is connected to the unit 350. The precharge unit 340 is connected to one end of the first test input / output line pair 330 to precharge the first test input / output line pair and the source / drain of the transistor constituting the precharge test enable unit 350. One terminal of the terminals is connected to the ground, and the other terminal is connected to the first switching unit 310 and the second switching unit 320.

Referring to the configuration of the predischarge test circuit 400 shown in FIG. 7B in detail, the precharge test circuit 400 may include the third switching unit 410: M7, M8, M9, and the fourth switching unit 420: M10, M11 and M12, a second test input / output line pair 430, a predischarge unit 440, and a predischarge test enable unit 450. The gate terminal of the transistor constituting the third switching unit 410 is connected to the bit line, one terminal of the source / drain terminals is connected to one line of the second test input / output line pair, and the other terminal is a predischarge test. It is connected to the enable unit 450. The gate terminal of the transistor constituting the fourth switching unit 420 is connected to the bit line bar, one terminal of the source / drain terminals is connected to the other line of the second test input / output line pair, and the other terminal is a predischarge test in. It is connected to the enable unit 450. The predischarge unit 340 is connected to one end of the second test input / output line pair 430 to predischarge the second test input / output line pair and constitutes the predischarge test enable unit 450. One terminal of the source / drain terminal is connected to the driving power source V _DD , and the other terminal is connected to the third switching unit 410 and the fourth switching unit 420.

On the other hand, the type or number of switching elements used in the present embodiment is only one of various embodiments of the present invention, the scope of the technical idea of the present invention is not limited thereto, and can be variously modified.

FIG. 8A illustrates a precharge test result, and FIG. 8B illustrates a predischarge test result.

FIG. 8A shows a result of performing a precharge test, and a result of a normal case and a failure memory cell. FIG. 8B shows a result of performing a predischarge test, a case of a normal case and a failure memory cell. The output result of is shown.

8 and 8B, when all of the memory cells in the memory cell group are normal, the test input / output line pairs also have mutually complementary outputs corresponding to the output values of the bit line pairs. However, if there is a pull-down failure or a pull-up failure in any memory cell in the memory cell group, the output value of the bit line pair represents an uncomplementary output, and the test input / output line pair also has an output that is not complementary. .

9 is a diagram illustrating an example in which a parallel test apparatus according to the present invention is applied to a hierarchical bit line and a divided word line memory structure.

In the parallel test apparatus according to the present invention, as shown in FIG. 9, the parallel test apparatus may perform a test for each memory cell group in a hierarchical bit line and a divided word line memory structure.

The structure of modern memory arrays is designed by dividing the entire array into local word lines and bit line blocks hierarchically composed of global word lines and bit lines. This hierarchical configuration has the advantage of reducing power consumption and delay by reducing the capacitance of word lines / bit lines. The parallel test apparatus according to the present invention can be applied to the hierarchical bit line and divided word line memory structures shown in FIG. 9, and thus can be applied to the recent SRAM architecture design trend.

10 is a flowchart illustrating a parallel test method of an SRAM according to the present invention.

Referring to FIG. 10, the SRAM parallel test method according to the present invention is first performed by dividing an SRAM array into a plurality of memory cell groups (S1010).

A process of simultaneously testing a plurality of memory cell groups in parallel is performed (S1020). In this case, the parallel test is performed using a parallel test circuit unit connected to an internal bit line pair of each memory cell group. In the parallel test process, only a faulty memory cell exists in each memory cell group is detected.

A process of selecting a memory cell group in which a failed memory cell exists is performed (S1030). Additional tests are not performed on the memory cell group in which the failed memory cell does not exist, and additional tests are performed on the memory cell group in which the failed memory cell exists.

Thereafter, a process of sequentially testing all memory cells in the selected memory cell group is performed (S1040). The redundancy replacement is performed on the failed memory cell detected through the test process (S1050).

[Equation 1]

Prior Test Time = O (N _C / N _{I / O} )

[Equation 2]

Test time of the present invention = O (N _G / N _TC ) + O (N _FG )

Equation 1 discloses a test time according to the prior art, and Equation 2 discloses a test time according to the present invention.

Said N _C the capacity of the memory in the formula 1, and if as the number of input and output bit line of the memory N _{I / O,} is then subjected to a memory cell test for a total of N _C / N _{I / O,} perform a redundancy replacement. However, since N _{I / O} is very small compared to N _C , much test time was consumed in this process. That is, in the conventional memory, N _C is about GByte, but N _{I / O} is in 8-32bit units. Since N _C is overwhelmingly larger than N _{I / O} , a lot of test time is required according to the prior art.

In Equation 2, N _G is the number of memory groups in the total memory, N _TC is the total number of operations that can be parallel tested simultaneously through multiple parallel test circuits, and N _FG is in the memory cell group determined to be faulty. The memory cell number.

According to the parallel test method according to the present invention shown in FIG. 10, after performing N _G / N _TC conference parallel tests through a plurality of parallel test circuit units, N _FG conference individual memory cells only for the memory cell group in which a failure is detected. All you need to do is test it. That is, the parallel test can significantly reduce the test time by testing only N _FG times the time corresponding to N _C / N _{I / O} consumed when testing individual memory cells according to the prior art.

FIG. 11 is a flowchart illustrating a process of simultaneously testing a plurality of memory cell groups in parallel among the processes illustrated in FIG. 10.

Referring to FIG. 11, a process of parallel testing a plurality of memory cell groups simultaneously detects pull-up or pull-down driving capability of memory cells in each memory cell group after precharging or predischarging a pair of bit lines in each memory cell group. By doing so. The detection of the pull-up or pull-down driving capability of these memory cells is performed through the following process.

First, a process of writing an arbitrary test pattern in each memory cell group is performed (S1021). In this case, the test pattern may be variously modified, and various test patterns will be described in more detail with reference to the following embodiments.

Next, a process of precharging or predischarging a pair of bit lines in each memory cell group is performed (S1022). When sensing the pull-down driving capability of the memory cells, a process of precharging the bit line pair is performed, and when detecting the pull-up driving capability of the memory cells, the process of predischarging the bit line pair is performed. The predischarge test may be performed after the precharge test, or vice versa, and the precharge test may be performed after the predischarge test.

In order to read the test pattern after a predetermined time elapses, memory cells according to the test pattern in each memory cell group are selected (S1023). Thereafter, a process of detecting an output of a test input / output line pair for outputting data corresponding to an output value of the bit line pair is performed (S1024).

Through the output values of the test input / output line pairs, a process of determining whether a failed memory cell exists in each memory cell group is performed (S1025). At this time, it is determined whether a faulty memory cell exists as follows. If the output of the test input / output line pair is a complementary output, it is determined that a faulty memory cell does not exist in the memory cell group. If the output of the test input / output line pair is not a complementary output, the fault memory is included in the memory cell group. It is determined that the cell exists.

12 is a flowchart illustrating a precharge test process in a parallel test process using a test pattern according to a first embodiment of the present invention. The first embodiment of the present invention shown in FIG. 12 is an embodiment using a test pattern for applying the same data to all the memory cells in each memory cell group. Since the predischarge test process has the same principle as the precharge test process, a description thereof will be omitted below.

Referring to FIG. 12, first, a process of writing the same data to each memory cell group is performed (S1210). Next, a process of precharging a pair of bit lines in each memory cell group to V _DD is performed (S1220).

In order to read the test pattern, all memory cells in each memory cell group are selected (S1230), and then a process of sensing an output of a test input / output line pair for outputting data corresponding to an output value of a bit line pair is performed ( S1240).

Then, it is determined whether a failed memory cell exists in each memory cell group (S1250).

On the other hand, when performing a parallel test as in the case of the present embodiment, when a test pattern is constant, it may be difficult to detect a fault, such as a neighboring sensitivity fault. To overcome this problem, a method of inputting different data and executing a test between neighboring memory cells will be described in the following embodiments.

13A and 13B illustrate a process of performing parallel test using a test pattern according to a second embodiment of the present invention. The parallel test process according to the second embodiment of the present invention is generally similar to the process of parallel testing a plurality of memory cell groups shown in FIG. 11, except that writing a test pattern, selecting memory cells, and testing Only the step of sensing the output of the input and output line pairs are different, and hereinafter, the different processes will be described in detail.

FIG. 13A illustrates a process of recording a test pattern, and FIG. 13B illustrates a process of performing a test.

First, ① is activated to write 1 to the word line, and then ② is activated to write 0 to the word line to complete the test pattern. Then, when the test is performed, all column pass transistors are operated, and the word line driver is sequentially operated in order of Row _m , Row _{m + 1} , Row _{m + 2} , and Row _{m + 3} .

That is, in the process of writing the test pattern, the first data is written to the memory cells connected to the even word lines of each memory cell group (cycle 1), and the next cycle is connected to the odd word lines of each memory cell group. The second data is written to the memory cell (cycle 2). In addition, the order of period 1 and period 2 may be changed.

Then, in order to read the test pattern, in the process of selecting memory cells in each memory cell group, all bit line pairs in each memory cell group are selected, word lines in each memory cell group are sequentially selected, and the selected order is selected. As a result, the output of the test input / output line pair is sensed.

14A and 14B illustrate a process of performing a parallel test using a test pattern according to a third exemplary embodiment of the present invention. 14A illustrates a process of recording a test pattern, and FIG. 14B illustrates a process of performing a test.

The word line driver is always activated, and the column pass transistors are divided into 1 and 2 to be sequentially activated to complete the test pattern. Then, when performing the test, the word line driver is sequentially driven, and the column pass transistors are divided into even and odd numbers, and only the even column pass transistors such as Col _n and Col _{n + 2} are used during the first four periods. The test is performed by driving, and the test is performed by driving only odd-numbered column pass transistors such as Col _{n + 1} and Col _{n + 3} for the next four cycles.

That is, in the process of writing the test pattern, the first data is written to the memory cells connected to the even-numbered bit line pairs of each memory cell group (period 1), and the next period is written to the odd-numbered bit line pairs of each memory cell group. The second data is written to the connected memory cell (cycle 2). On the other hand, the order of the cycle 1 and the cycle 2 may be changed. When the recording order is changed, the following test pattern reading order is also changed accordingly.

Then, in order to read the test pattern, in the process of selecting the memory cells in which the first data in each memory cell group is written, the word lines in each memory cell group are sequentially selected, and the bit line pair in each memory cell group is The test is performed by selecting only even-numbered bit line pairs. In the process of selecting the memory cells in which the second data in each memory cell group is written, the word lines in each memory cell group are sequentially selected, and the bit line pair in each memory cell group is selected by testing only the odd bit line pair. Perform

15A and 15B illustrate a process of performing a parallel test using a test pattern according to a fourth exemplary embodiment of the present invention.

Three cycles are required when recording the test pattern according to the fourth embodiment of the present invention. First, write 0 in the entire memory cell (①), activate the even-numbered word line driver and the even-numbered column pass transistor, write 1 (②), and activate the odd-numbered word line driver and the odd-numbered column pass transistor. Record 1 (③) to complete the test pattern.

Then, when the test is performed, the word line driver is sequentially driven, and the column pass transistors are divided into even and odd numbers. During the first four periods, even-numbered column pass transistors such as Col _n and Col _{n + 2} and Col are _The test is performed by alternately driving odd-numbered column pass transistors such as _{n + 1} and Col _{n + 3} . The word line driver is sequentially driven during the next four cycles, and the test is performed by alternately driving the column pass transistors in the reverse order of the previous four cycles.

That is, in the process of writing the test pattern, the second data is input to all memory cells in each memory cell group (period 1), and the memory is located at the intersection of even-numbered bit line pairs and even-numbered word lines of each memory cell group. After writing the first data into the cell (period 2), the first data is written into the memory cell located at the intersection of the odd-numbered bit line pair and the odd-numbered word line of each memory cell group (period 3). On the other hand, the order of period 2 and period 3 may be changed. When the recording order is changed, the following test pattern reading order is also changed accordingly. Then, in order to read the test pattern, in the process of selecting the memory cells in which the first data in each memory cell group is written, the word lines in each memory cell group are sequentially selected, and the bit line pair in each memory cell group is The tests are performed by alternately selecting the even and odd numbers in order. In the process of selecting memory cells in which second data in each memory cell group is written, word lines in each memory cell group are sequentially selected, and bit line pairs in each memory cell group are odd-numbered and The tests are performed by alternately selecting them in the even order.

The test pattern records shown in Figs. 13A to 15B can be summarized in Table 1 below, and the test read period can be summarized in Table 2 below.

division Test pattern recording (cycle 1) Test pattern recording (cycle 2) Test pattern record (cycle 3) Second embodiment Row _m , Row _{m + 2} , All cols Row _{m + 1} , Row _{m + 3} , All cols N / A Third embodiment All rows, Coln, Col _{n + 2} All rows, Col _{n + 1} , Coln ₊₃ N / A Fourth embodiment All rows, all cols Row _m , Row _{m + 2} , Coln, Col _{n + 2} Row _{m + 1} , Row _{m + 3} , Col _{n + 1} , Col _{n + 3}

division Test (cycle 1) Test (cycle 2) Test (cycle 3) Test (cycle 4) Second embodiment Row _m all cols Row _{m + 1} , all cols Row _{m + 2} , all cols Row _{m + 3} , all cols Third embodiment Row _m , Col _n , Col _{n + 2} Row _{m + 1} , Col _n , Col _{n + 2} Row _{m + 2} , Col _n , Coln ₊₂ Row _{m + 3} , Col _n , Col _{n + 2} Fourth embodiment Row _m , Col _n , Col _{n + 2} Row _{m + 1} , Col _{n + 1} , Col _{n + 3} Row _{m + 2} , Col _n , Coln ₊₂ Row _{m + 1} , Col _{n + 1} Col _{n + 3} division Test (cycle 5) Test (cycle 6) Test (cycle 7) Test (cycle 8) Second embodiment N / A N / A N / A N / A Third embodiment Row _m , Col _{n + 1} , Col _{n + 3} Row _{m + 1} , Col _{n + 1} , Col _{n + 3} Row _{m + 2} , Col _{n + 1} , Col _{n + 3} Row _{m + 3} , Col _{n + 1} , Col _{n + 3} Fourth embodiment Row _m , Col _{n + 1} , Col _{n + 3} Row _{m + 1} , Col _n , Col _{n + 2} Row _{m + 2} Col _{n + 1} Col _{n + 3} Row _{m + 3} , Col _n , Col _{n + 2}

16 is a diagram simulating a test time ratio for comparing the performance of the parallel test according to the present invention.

In order to compare the performance of the parallel test, the test time ratio was defined as in Equation 3 below. The test time ratio assumes that at least one faulty memory cell exists in each memory group, and compares the execution time in parallel testing with the individual memory cell test time.

[Equation 3]

Where N _C is the capacity of the memory, T _ICT is the individual memory cell test time, and N _FG is the number of memory cells in the memory cell group determined to be faulty.

Based on Equation 3, a test time ratio according to the number of memory groups and the memory capacity is shown in FIG. 16.

Referring to FIG. 16, when the number of memory groups is 16 and the memory capacity is 16 Kbytes, a test time of about 1/15 is required, and when the number of memory groups is 1024 and the memory capacity is about 16 times, about 1000 times. It can be seen that it is efficient.

Accordingly, it can be seen that the larger the memory capacity N _C and the larger the number of memory groups, the higher the effect of the parallel test.

What has been described above is merely an exemplary embodiment of the parallel test apparatus and method of the SRAM according to the present invention, the present invention is not limited to the above-described embodiment, as claimed in the claims below, Without departing from the gist of the present invention, one of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

1 is a flowchart illustrating a memory test sequence according to the prior art.

2 is a schematic diagram of an SRAM parallel test apparatus according to the present invention, and FIG. 3 is a functional block diagram of an SRAM parallel test apparatus according to the present invention.

4 is a diagram illustrating a possible failure part in 6T SRAM.

FIG. 5 is a table summarizing the trouble spots detectable by the precharge test and the predischarge test.

6 is a schematic circuit diagram of a parallel test apparatus of SRAM.

FIG. 7A is a precharge test circuit diagram of an SRAM parallel test apparatus, and FIG. 7B is a predischarge test circuit diagram of an SRAM parallel test apparatus.

FIG. 8A illustrates a precharge test result, and FIG. 8B illustrates a predischarge test result.

9 is a diagram illustrating an example in which a parallel test apparatus according to the present invention is applied to a hierarchical bit line and a divided word line memory structure.

10 is a flowchart illustrating a parallel test method of an SRAM according to the present invention.

FIG. 11 is a flowchart illustrating a process of simultaneously testing a plurality of memory cell groups in parallel among the processes illustrated in FIG. 10.

12 is a flowchart illustrating a precharge test process in a parallel test process using a test pattern according to a first embodiment of the present invention.

13A and 13B illustrate a process of performing parallel test using a test pattern according to a second embodiment of the present invention.

14A and 14B illustrate a process of performing a parallel test using a test pattern according to a third exemplary embodiment of the present invention.

15A and 15B illustrate a process of performing a parallel test using a test pattern according to a fourth exemplary embodiment of the present invention.

16 is a diagram simulating a test time ratio for comparing the performance of the parallel test according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: precharge circuit

200: predischarge circuit

300: precharge test circuit

400: predischarge test circuit

500: Column Pass Transistor

Claims (17)

A parallel test device of SRAM divided into a group of memory cells, A plurality of parallel test circuits connected to the plurality of memory cell groups and simultaneously testing whether a failed memory cell exists in each memory cell group, Each of the parallel test circuits is connected to a pair of bit lines of each group of memory cells, Each parallel test circuit unit, A precharge circuit coupled to the bit line pair for precharging the bit line pair; Precharge test circuitry for detecting a pull down fault of memory cells in the memory cell group; A predischarge circuit connected to the bit line pair for predischarge the bit line pair; And And a predischarge test circuit for detecting a pull down fault of memory cells in the memory cell group. delete The method of claim 1, The precharge test circuit, A first switching unit and a second switching unit respectively connected to the bit line pair and driven according to an output of the bit line pair; And a first test input / output line pair connected to the first switching unit and the second switching unit, respectively, to output data corresponding to the output values of the bit line pairs. The predischarge test circuit, A third switching unit and a fourth switching unit respectively connected to the bit line pair and driven according to an output of the bit line pair; And a second test input / output line pair connected to the third switching unit and the fourth switching unit, respectively, and outputting data corresponding to the output values of the bit line pairs. The method of claim 3, If there is no pull down failure in all memory cells in the memory cell group, the first test input / output line pair has a complementary output value, And if there is no pull-up failure in all memory cells in the memory cell group, the second test input / output line pair has a complementary output value. The method of claim 3, wherein the precharge test circuit, A precharge unit for precharging the first test input / output line pairs and a precharge test enable unit for initiating an operation of the precharge test circuit; A gate terminal of the switching element constituting the first switching unit is connected to a bit line, one terminal of a source / drain terminal is connected to any one of the first test input / output line pairs, and the other terminal is the precharge test in Connected to the enable portion, A gate terminal of the switching element constituting the second switching unit is connected to a bit line bar, one terminal of a source / drain terminal is connected to the other line of the first test input / output line pair, and the other terminal is the precharge test enable. Connected to wealth, The precharge unit is connected to one end of the first test input / output line pair to precharge the first test input / output line pair, Parallel test of the SRAM, characterized in that one terminal of the source / drain terminals of the switching element constituting the precharge test enable unit is connected to the ground, and the other terminal is connected to the first switching unit and the second switching unit. Device. The method of claim 3, wherein the predischarge test circuit, A predischarge unit for predischarging the second test input / output line pair and a predischarge test enable unit for initiating an operation of the predischarge test circuit; A gate terminal of the switching element constituting the third switching unit is connected to a bit line, one terminal of a source / drain terminal is connected to any one of the second test input / output line pairs, and the other terminal is the predischarge test. Connected to the enable section, A gate terminal of the switching element constituting the fourth switching unit is connected to a bit line bar, one terminal of a source / drain terminal is connected to the other line of the second test input / output line pair, and the other terminal is the predischarge test in. Connected to the enable portion, The predischarge unit is connected to one end of the second test input / output line pair, and predischarges the second test input / output line pair. One of the source / drain terminals of the switching element constituting the predischarge test enable unit is connected to a driving power source, and the other terminal is connected to the third switch unit and the fourth switch unit. Parallel test device. Dividing the SRAM array into a plurality of memory cell groups; Parallel testing the plurality of memory cell groups simultaneously using a plurality of parallel test circuit units connected to the plurality of memory cell groups; Selecting a memory cell group in which a failed memory cell is detected; And Sequentially testing all memory cells in the selected memory cell group, The parallel test step, And detecting a pull-up or pull-down driving capability of the memory cells in each memory cell group after precharging or predischarging the pair of bit lines in each memory cell group. delete The method of claim 7, wherein the sensing of the pull-up or pull-down driving capability of the memory cells comprises: Writing a random test pattern into each memory cell group; Precharging or predischarging a pair of bit lines in each memory cell group; Selecting memory cells according to a test pattern in each memory cell group to read the test pattern; Detecting an output of a test input / output line pair for outputting data corresponding to an output value of the bit line pair; And And determining whether a faulty memory cell exists in each of the memory cell groups. The method of claim 9, wherein the determining of the presence of the failed memory cell comprises: When the output of the test input / output line pair is a complementary output, it is determined that a failed memory cell does not exist in the memory cell group. And determining that a faulty memory cell exists in a memory cell group when the output of the test input / output line pair is not a complementary output. 10. The method of claim 9, wherein writing the random test pattern comprises inputting the same data into each of the memory cell groups, Selecting memory cells in each memory cell group comprises selecting all memory cells in each memory cell group. The method of claim 9, wherein recording the arbitrary test pattern comprises: Writing first data to memory cells connected to first word lines of each memory cell group; And Writing second data to a memory cell connected to a second word line of each memory cell group, And the first and second word lines are even and odd word lines, respectively, or the first and second word lines are odd and even word lines, respectively. The method of claim 12, wherein selecting memory cells in each memory cell group comprises: Selecting all bit line pairs in each memory cell group, and sequentially selecting word lines in each memory cell group, Sensing the output of the test input / output line pairs according to the selected order of the memory cells. The method of claim 9, wherein recording the arbitrary test pattern comprises: Writing first data to a memory cell connected to a first bit line pair of each memory cell group; And Writing second data to a memory cell connected to a second bit line pair of each memory cell group, Wherein the first and second bit line pairs are even and odd bit line pairs, respectively, or the first and second bit line pairs are odd and even bit line pairs, respectively. . 15. The method of claim 14, wherein selecting memory cells in each memory cell group comprises selecting memory cells in which first data in each memory cell group is written and a memory in which second data in each memory cell group is written. Selecting cells; The selecting of the memory cells in which the first data is written comprises sequentially selecting word lines in each of the memory cell groups, and pairing bit lines in each memory cell group to select the first bit line pair. Selecting the memory cells in which the second data is written, sequentially selecting word lines in each of the memory cell groups, selecting a second bit line pair in the pair of bit lines in each of the memory cell groups, Sensing the output of the test input / output line pairs according to the selected order of the memory cells. The method of claim 9, wherein recording the arbitrary test pattern comprises: Inputting second data into all memory cells in each memory cell group; Writing first data into a memory cell located at an intersection of a first bit line pair and a first word line of each memory cell group; And Writing first data to a memory cell located at an intersection of a second bit line pair and a second word line of each memory cell group, The first and second bit line pairs are even and odd bit line pairs, respectively, or the first and second bit line pairs are odd and even bit line pairs, respectively. And the first and second word lines are even and odd word lines, respectively, or the first and second word lines are odd and even word lines, respectively. The method of claim 16, Selecting memory cells in each memory cell group may include selecting memory cells in which first data in each memory cell group is written and selecting memory cells in which second data in each memory cell group is written. Include, Selecting the memory cells in which the first data is written comprises sequentially selecting word lines in each memory cell group, and pairing bit lines in each memory cell group in the order of the first and second bit line pairs. Then alternately choose The selecting of the memory cells in which the second data is written comprises sequentially selecting word lines in each memory cell group, and pairing bit lines in each memory cell group in the order of the second and first bit line pairs. Alternately select, Sensing the output of the test input / output line pairs according to the selected order of the memory cells.

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