KR20070023770A - Method of forming a nanocluster charge storage device - Google Patents

Abstract

Multiple memory cell devices are formed by using an intermediate double polysilicon nitride control electrode stack overlying nanoclusters 24. The stack includes a first formed polysilicon nitride layer 126 and a second formed polysilicon containing layer 28. The second formed polysilicon containing layer is removed from the regions with the plurality of memory cells. In one form, the second formed polysilicon containing layer also has a nitride portion removed, thereby leaving the first formed polysilicon nitride layer in the memory cell devices. In another form, the second formed polysilicon containing layer does not contain nitride and the nitrided portion of the first formed polysilicon layer is also removed. In the latter form, a subsequent nitride layer is formed on the residual polysilicon layer 28. The upper part of the device is protected from oxidation. Gate electrodes of peripheral devices in memory cell devices also use a second formed polysilicon containing layer.

Nanoclusters, Polysilicon, Nitride Layers, Memory Cells

Description

Method of forming a nanocluster charge storage device

The present invention relates to semiconductor devices, and more particularly to devices with nanoclusters.

Some devices, such as memories (e.g., nonvolatile memories), store discrete charges called nanoclusters (e.g., silicon, aluminum, gold, or germanium) to store charge in the transistor's charge storage location. Use devices. In some examples, nanoclusters are placed between two lower dielectric layers and a control dielectric layer. Examples of such transistors include thin film transistors. Typically the memory contains an array of such transistors. Examples of nanocluster types include doped and undoped semiconductor clusters such as silicon nanocrystals, germanium nanocrystals and alloys thereof. Other examples of nanocluster types include various conductive structures such as metal nanoclusters (eg, gold nanoclusters and aluminum nanoclusters) and metal alloy nanoclusters. In some instances, nanoclusters are 10-100 angstroms in size.

Some memories with charge storage transistors with nanoclusters are implemented on integrated circuits that also include high voltage transistors in circuits used to charge and discharge the charge storage locations of the charge storage transistors. Charging or discharging the charge storage locations is used to store one or more bits of information and may be referred to as programming or erasing. These high voltage transistors typically comprise a relatively thick gate oxide. This gate oxide can be formed under severe oxidation conditions. This oxidizing atmosphere can penetrate the control dielectric of the charge storage transistors, undesirably oxidizing nanocrystals and undesirably increasing the underlying dielectric thickness. Thus, an improved method of manufacturing a device with nanoclusters is desirable.

The present invention can be understood with reference to the accompanying drawings, and numerous objects, features, and advantages thereof will be apparent to those skilled in the art.

The use of the same reference numerals in different drawings refers to similar or identical components. Those skilled in the art will appreciate that the components of the figures are shown for simplicity and clarity and are not to scale. For example, the dimensions of some components in the figures may be exaggerated relative to other components to help the implementation of the embodiments of the present invention.

The following is intended to provide a detailed description of at least one example of the invention and is not intended to limit the invention itself. Rather, any number of variations are within the scope of the invention as appropriately defined in the claims following this description.

1-16 of the figures are a series of partial side views of a semiconductor device at various stages of fabrication of an integrated circuit according to the first embodiment of the present invention.

1-10 and 16-23 of the figures are a series of partial side views of a semiconductor device at various stages of fabrication of an integrated circuit in accordance with a second embodiment of the present invention.

1-16 illustrate partial side views of a semiconductor wafer during steps in the manufacture of a memory including nanoclusters in accordance with a first embodiment of the present invention. As described below, the presently disclosed embodiment utilizes an intermediate double nitride-polysilicon control electrode stack comprising a first formed nitride-polysilicon structure and a second formed nitride-polysilicon structure. The second formed nitride-polysilicon structure is removed when the peripheral device control electrode is patterned, leaving the first formed nitride-polysilicon control electrode structure for memory cell devices. This technique protects the upper portion of the nanocluster oxide layer, thereby preserving the thickness and quality of this oxide layer.

1 illustrates a semiconductor device 10. The semiconductor device 10 is an integrated circuit die. The semiconductor device 10 includes a substrate 12 that is part of the entire wafer in the presently illustrated manufacturing stage. The semiconductor device 10 also includes various dopant wells 14, 18, 20 that form part of the functional circuit of the semiconductor device 10. The substrate also includes various preformed shallow trench isolation structures (not shown) to separate the different devices and laterally separate the wells discussed herein. The semiconductor device 10 also includes a lower oxide layer 22.

Dopant wells 14, 18, 20 may take various forms. The nonvolatile memory (NVM) well 18 forms part of the storage cell circuit of the nonvolatile memory array. In the illustrated embodiment, NVM well 18 is a p-well in which a storage cell array is to be placed. In the embodiments discussed herein, the peripheral devices include various devices outside the NVM storage cell array, although in some context the peripheral devices include only high voltage (HV) devices (eg, cell charge / discharge devices). HV devices, integrated circuit die input / output (I / O) devices, and low voltage (LV) devices (eg, logic devices). The high voltage (HV) well 14 forms part of the circuit (eg, high voltage transistors) for programming and erasing the cells of the NVM array. The illustrated HV well 14 is n well. The semiconductor device may alternatively or additionally include an HV p-well in a deep n-type isolation well. I / O well 20 forms part of the I / O circuit of semiconductor device 10. The illustrated I / O well 20 is n-well. The semiconductor device may alternatively or additionally include I / O wells in deep n-type isolation wells. In one embodiment, I / O well 20 is a double gate oxide (DGO) well.

Silicon dioxide layer 22 provides the tunnel dielectric layer. Other dielectrics may be used for the oxide layer 22, such as silicon oxynitride, hafnium oxide, aluminum oxide, ruthenium oxide, or lanthanum silicate. The dielectric layer 22 was formed on the substrate 12 by, for example, oxidation or chemical vapor deposition. In one embodiment, the bottom dielectric is 5 nanometers thick, but in other embodiments may be another thickness.

Referring to FIG. 2, nanocluster layer 24 (eg, made of silicon, aluminum, gold, germanium, silicon and germanium alloys or other types of conductive materials or doped or undoped semiconductor materials) may be used. It is formed on oxide layer 22 by, for example, self-assembly techniques such as chemical vapor deposition techniques, aerosol deposition techniques, spin on coating techniques, or annealing a thin film to form nanoclusters. In one embodiment, nanoclusters 24 are silicon nanocrystals. In one embodiment where nanoclusters are used in nonvolatile memory, the nanoclusters have a planar density of 1 × 10 ¹² cm ^{2 with} a size of 5 to 7 nm. In some embodiments, nanoclusters are 10-100 angstroms in size. However, in other embodiments nanoclusters may be of different sizes and / or of different densities. In one embodiment, nanoclusters 24 are generally spaced apart by an average distance equal to the average size of the clusters. In one such embodiment the average distance is greater than 4 nm. Although nanoclusters 24 are shown as having a uniform size and distribution, nanoclusters 24 will have a non-uniform size and non-uniform distribution in practical realization. Nanoclusters 24 may be used to implement charge storage locations in transistors (see FIG. 16) of a nonvolatile memory of semiconductor device 10.

After the nanoclusters 24 are deposited, a layer of dielectric material (eg, silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, lanthanum oxide, and lanthanum silicate) is deposited on the nanocrystals 24. To form the control dielectric layer 26 (for example, by chemical vapor deposition). In one embodiment, a silicon dioxide layer is deposited on the nanoclusters. Alternatively, other dielectrics may be used for layer 26, such as silicon oxynitride, hafnium oxide, aluminum oxide, lanthanum oxide, or lanthanum silicate. In another embodiment, an oxide-nitride-oxide (ONO) stack of silicon dioxide, silicon nitride, and silicon dioxide may be used for layer 26. In one embodiment, dielectric layer 26 is approximately 5-15 nm thick but in other embodiments may be other thickness.

In some embodiments, the bottom dielectric 22, nanoclusters 24, and control dielectric 26 may be a layer of dielectric material (not shown in the dielectric material layer following ion implantation (eg, silicon or germanium)). It can be formed by annealing ions to form nanocrystals In other embodiments, the bottom dielectric 22, nanoclusters 24 and control dielectric 26 are two dielectric materials to form nanoclusters. It can be formed by recrystallization of a silicon rich oxide layer between layers In other embodiments, nanoclusters can be implemented in a plurality of layers overlying the underlying dielectric. It is formed by depositing an amorphous nanocluster material layer (eg, 1-5 nm) where the resulting structure is annealed in a subsequent annealing process.

Referring to FIG. 3, a doped polysilicon layer 28 is formed on the dielectric layer 26. Part of the polysilicon layer 28 will be used as the gate electrode of the NVM bit cell. The polysilicon layer may be doped in situ (during deposition) or doped by implantation (after deposition). Other gate electrode materials such as metals may be used. After the gate electrode 28 is deposited, an antireflective coating (ARC) is deposited. In the illustrated embodiment, the silicon nitride layer 30 provides an antireflective coating.

Referring to FIG. 4, a masking layer 32 (eg, photoresist) is formed on the nitride layer 30. Masking layer 32 protects the gate stack on NVM well 18 and exposes portions of layers 30, 28, 26, 24, 22 from other regions of semiconductor device 10. The nitride layer 30, polysilicon layer 28, dielectric layer 26 and nanocluster layer 24 are then removed. Subsequently, part of the layer 22 is removed. In one embodiment, reactive ion etching is used to remove layers 30, 28, 26, 24, 22.

Referring to FIG. 5, masking layer 32 was removed to expose the nitride layer, and exposed portions of tunnel dielectric layer 22 were removed to expose the substrate. In embodiments where tunnel dielectric layer 22 is silicon dioxide, removal may be performed through wet etching with dilute hydrofluoric acid.

Referring to FIG. 6, a high voltage device oxide layer 34 is formed. For example, HV oxide layer 34 may be grown by oxidation in oxygen or steam. One typical oxide layer 34 is 5 to 15 nm thick silicon dioxide. The oxide layer 35 is typically grown on the nitride layer 30 at a small thickness. During this aggressive oxidation step, nitride layer 30 acts as a diffusion barrier to protect underlying nanoclusters 24, polysilicon layer 28, and tunnel dielectric 22 from harmful oxidation. This oxidation—if done—can adversely affect NVM device performance because programming and erasing of the nanoclusters is very sensitive to the thickness of the dielectric layer 22 and the nanocluster size.

Subsequently, low voltage device wells 37 for a general logic circuit are formed by implantation into the substrate 12. A typical implantation process involves opening the low voltage regions following the masking step. HV oxide layer 34 is used as a sacrificial oxide for low voltage well implantation. Logic wells are typically activated by a rapid thermal annealing process.

After formation of logic well 37, masking layer 36 (eg, photoresist) is HV oxide to protect portions of the HV oxide layer on HV device well 14 and expose other portions of the HV oxide layer. Formed on layer 34.

Referring to FIG. 7, exposed portions of the HV oxide layer 34 are removed through wet etching with dilute hydrofluoric acid. Oxide layer 35 is removed along with the exposed portions of layer 34. After the exposed portions of the HV oxide layers 34, 35 are removed, the masking layer 36 is also removed.

Referring to FIG. 8, an I / O device oxide layer 38 is formed. Although other methods may be used, oxide layer 38 is typically grown by oxidation in oxygen. Other oxygen compounds, such as N ₂ O, may also be used. One typical oxide layer 38 is silicon dioxide. I / O oxide layer 38 is generally 4-8 nm thick, slightly thinner than HV oxide layer 34. The thin oxide layer 39 is grown with the nitride layer 30. HV oxide layer 34 becomes naturally thick during the growth of I / O oxide layer 38. During this oxidation step, nitride layer 30 again acts as a diffusion barrier to protect underlying nanoclusters 24 and tunnel dielectric 22 from harmful oxidation. This oxidation—if done—can adversely affect NVM device performance because programming and erasing of the nanoclusters is very sensitive to the thickness of the dielectric layer 22 and the nanocluster size.

9, the portions of the HV and I / O oxide layers 34, 38 are protected on the respective HV and I / O device wells 14, 20, and the other portions of the I / O oxide layer are protected. Masking layer 30 (eg, photoresist) is formed on I / O oxide layer 38 to expose it. Next, exposed portions of I / O oxide layer 38 are removed using, for example, wet etching of dilute hydrofluoric acid. In addition, the thin oxide layer 39 on the nitride layer 30 is also removed.

Referring to FIG. 10, photoresist layer 40 is removed from HV oxide layer 34 and I / O oxide layer 38. Low voltage (LV) oxide 42 is formed. Although other methods may be used, oxide layer 42 is typically grown by oxidation in oxygen, N ₂ O or NO. One typical oxide layer 42 is silicon dioxide. I / O oxide layer 42 is generally 1.5 to 3 nm thick, slightly thinner than HV oxide layer 34 and I / O oxide layer 38. Very thin oxide layer 43 may be grown with nitride layer 30. HV oxide layer 34 and I / O oxide layer 38 become naturally thick during the growth of LV oxide layer 42. During this oxidation step, nitride layer 30 again acts as a diffusion barrier to protect underlying nanoclusters 24 and tunnel dielectric 22 from harmful oxidation.

Referring to FIG. 11, a doped polysilicon layer 44 is formed on the substrate 12. In the illustrated embodiment, polysilicon layer 44 is deposited on LV oxide layer 42, HV oxide layer 34, I / O oxide layer 38, and incidental oxide layer 43. Portions of the polysilicon layer 44 will act as gate electrodes of HV, LV and I / O devices. When polysilicon is used as the gate electrode for peripheral and NVM array devices, typically, the two layers are approximately the same thickness. In other embodiments, different materials of suitable thicknesses may be used for the peripheral and NVM array gate electrodes. The polysilicon layer 44 may be doped in situ (during deposition) or may be doped by implantation (after deposition). Other gate electrode materials such as metals may be used. After the gate electrode 44 is deposited, an antireflective coating (ARC) is deposited. In the illustrated embodiment, silicon nitride layer 46 provides an antireflective coating.

12, a masking layer 48 (eg, photoresist) is formed on nitride layer 46 on peripheral devices and used to pattern gates for these devices, followed by layers 44, The exposed portions of 46) are removed using, for example, anisotropic plasma etching. During this gate patterning step, the gate electrodes (eg, portions of layer 44) of LV, HV, and I / O devices remain on the polysilicon layer 44 and the nitride layer overlying the NVM regions. (46) Parts are removed. By using reactive ion etching selective to the layers 43 and 30, substantially the gutter electrode material layer 44 and the ARC layer 46 are completely removed from the NVM array region and the I / O, HV, and LV devices Gate electrodes are patterned at the same time.

Referring to FIG. 13, the masking layer 48 is removed. Masking layer 50 (eg, photoresist) is formed on peripheral device regions and other regions corresponding to HV well 14, I / O well 20, and LV well 38. . The masking layer serves to pattern gate electrodes for NVM array devices and to protect peripheral portions of the semiconductor device 10.

Referring to FIG. 14, various portions of the layers exposed by the masking layer 50 are removed (eg, via non-selective, anisotropic, timed, plasma etching). For example, the exposed portions of thin oxide layer 43, nitrided ARC layer 30, gate electrode layer 28, control dielectric 26 and nanocluster layer 24 are removed. Portions of the tunnel dielectric layer 22 are also removed.

Referring to FIG. 15, the masking layer 50 is removed. Any remaining exposed portions of low voltage oxide layer 42, high voltage oxide layer 34, NVM tunnel dielectric 22, and I / O oxide layer 38 are removed by wet etching processes. Very thin oxides 43 on the NVM ARC layer 30 are also removed. In the embodiment where all oxide layers 34, 38, 42 are silicon dioxide, dilute hydrofluoric acid wet clean may be employed for this purpose.

Referring to FIG. 16, NVM cells and peripheral devices are completed. Following the formation of all gate electrodes as described in FIG. 15, standard CMOS processing techniques are used to form source / drain extensions, sidewall spacers and source / drain regions. As shown, 60 and 62 represent source / drain regions and extensions of the HV device, 64 and 66 represent source / drain regions and extensions of the HV device, and 64 and 66 represent source / drain regions and Extensions of the NVM cell are shown, 68 and 70 represent source / drain regions and I / O device extensions, and 72 and 74 represent extension of the source / drain regions and LV device. Sidewall spacers 52 correspond to HV devices, sidewall spacers 54 correspond to NVM cell devices, sidewall spacers 56 correspond to I / O devices, and sidewall spacers 58 are LV Corresponds to the device.

In another embodiment, after the LV oxide 42 is formed as shown in FIG. 10, a doped polysilicon layer 44 can be formed on the substrate 12 as shown in FIG. 17. In the illustrated embodiment, polysilicon layer 44 is deposited on LV oxide layer 42, HV oxide layer 34, I / O oxide layer 38, and incidental oxide layer 43. Portions of the polysilicon layer 44 will act as gate electrodes of HV, LV and I / O devices. In this embodiment no antireflective coating (ARC) is required at this stage since the subsequent etching is for a large area and not a critical dimension.

Referring to FIG. 18, a masking layer 80 (eg, photoresist) is formed and patterned on the HV, I / O and LV regions to expose the NVM EL region. In FIG. 19, polysilicon layer 44, thin oxide layer 43, and nitride layer 30 are etched on the NVM region using, for example, dry etching, wet etching, or a combination thereof. In one embodiment, the etch stops when a chemical change in the materials being etched is detected. In FIG. 20, masking layer 80 is removed (eg, through a plasma ash process or a pyrana resist strip), and ARC layer 82 is deposited uniformly on polysilicon layers 44, 28. . In the illustrated embodiment, silicon nitride is used to provide the antireflective coating. In FIG. 21, a masking layer 84 is formed on the HV, I / O, LV and NVM regions. In FIG. 22, dry etching is performed to remove the ARC layer 82 and underlying polysilicon layers 44, 28, thereby exposing the dielectric layers 26, 34, 38, 42. In FIG. 23, masking layer 84 is removed (eg, as discussed above with respect to masking layer 80), and dielectric layers 26, 34, 38, 42 and exposed portions of layer 24. Formation of the gate electrodes continues by removing them (eg etching). After removal of the ARC layer 82, processing continues in a manner similar to that described above with respect to FIG. This alternative embodiment provides the advantage that only one of the two masks has critical dimensions, which provides cost and manufacturing advantages.

What has been described above is intended to describe at least one embodiment of the invention. What is described above is not intended to define the scope of the invention. Rather, the scope of the invention is defined in the claims. Accordingly, other embodiments of the present invention include other variations, modifications, additions, and / or improvements to what has been described above.

In one embodiment, a method of forming a nanocluster charge storage device is provided. A substrate is provided. The substrate has a first dopant well associated with the nanocluster charge storage device and a second dopant well associated with a semiconductor device having no nanoclusters. A first gate stack is formed having a first conductive gate material layer overlying the first dopant well and forming a gate electrode in the first gate stack. The first conductive gate material layer overlies the plurality of nanoclusters embedded in the first gate dielectric layer. The first conductive gate material layer is placed under a portion of the first conductive gate material layer. The second gate stack is formed overlying the second dopant well using a portion of the second conductive gate material layer overlying the second dopant well as the gate electrode in the second gate stack. The portion of the second conductive gate material layer overlying the first conductive gate material layer is removed.

In another form, the portion of the second conductive gate material layer overlying the first conductive gate material layer is removed by masking all regions away from the first dopant well and selectively etching the second conductive gate material layer. In yet another embodiment, the first conductive gate material layer and the second conductive gate material layer are formed using doped polysilicon, metal or metal alloy. In yet another embodiment, the first conductive gate material layer is implemented of a different material than the second conductive gate material layer.

In another embodiment, the first gate dielectric layer is formed by forming a first oxide layer and a second gate oxide layer over and surrounding the nanocluster layer. A first gate dielectric and a first conductive gate material layer are formed overlying both the first dopant well and the second dopant well. Selective etching of the first conductive gate material layer, the first gate dielectric layer, and the nanocluster layer from the regions overlying the second dopant well is performed using a combination of wet and dry etching.

In another embodiment, the second gate stack is formed by forming a second gate dielectric layer and a second conductive gate material layer overlying a portion of the second dopant well. The second conductive gate material layer overlies the second gate dielectric layer. In yet another embodiment, the second gate dielectric layer is formed of silicon dioxide or silicon oxynitride.

In another embodiment, a nitride layer is formed in the first gate stack and overlies the first conductive gate material and is between the first conductive gate material and the second conductive gate material portion. An oxide layer is formed overlying the nitride layer and in physical contact therewith. The nitride layer and the oxide layer function as an etch stop layer when removing the second conductive gate material. The nitride layer also functions as an antireflective coating when forming a gate electrode in the first gate stack.

In yet another embodiment, the first gate dielectric layer is formed of oxynitride of an oxide or a compound containing at least one of hafnium, lanthanum, aluminum, and silicon.

In yet another embodiment, the plurality of nanoclusters embedded in the first gate dielectric layer overlying the first and second dopant wells are doped or undoped semiconductor nanocrystals, metal nanocrystals, two or more doped or It is formed by forming a layer of nanocrystals, or metal alloy nanocrystals, of undoped semiconductors.

In yet another embodiment, the first source and the first drain are formed around the first gate stack and in the first dopant well to form a charge storage device as a nonvolatile memory (NVM) transistor. The second source and the second drain are formed around the second gate stack and in the second dopant well to form a peripheral transistor.

In yet another embodiment, the semiconductor device is formed from a second gate stack. Semiconductor devices enable charging and discharging of nanocluster charge storage devices.

In yet another embodiment, a method includes providing a substrate; Forming a first dopant well and a second dopant well in the substrate; Forming a nanocluster layer embedded in a first gate dielectric overlying the first and second dopant wells; Forming a first conductive gate material layer overlying the nanocluster layer; Forming a nitride layer overlying the first conductive gate material layer; Patterning the nitride layer, first conductive gate material layer, and nanocluster layer to remove them from regions other than the region overlying the first dopant well to form a storage stack overlying the first dopant well; Forming a second gate dielectric overlying the second dopant well and free of nanoclusters; Forming a second conductive gate material layer overlying the second gate dielectric and the storage stack; Forming an antireflective coating layer overlying the second conductive gate material layer; Patterning the second conductive gate material layer to form a first gate stack having the second conductive gate material layer as the gate electrode while removing the second conductive gate material layer from the storage stack; Forming a second gate stack overlying the first dopant well using a first conductive gate material layer as the gate electrode of the charge storage device with nanoclusters by removing a portion of the storage stack.

In yet another embodiment, a method includes forming a transistor by forming a first source and a first drain around a first gate stack and in a second dopant well; And forming a second source and a second drain around the second gate stack and in the first dopant well to complete the formation of the charge storage device.

In yet another embodiment, the method further includes forming a first conductive gate material layer of doped polysilicon, metal, or metal alloy.

In yet another embodiment, the method further includes forming a second conductive gate material layer 44 of doped polysilicon, metal, or metal alloy.

In another embodiment, the method comprises a nanocluster layer embedded in a first gate dielectric overlying a first dopant well and a second dopant well, doped or undoped semiconductor nanocrystals, metal nanocrystals, two or more. And forming by forming a layer of doped or undoped semiconductors, or metal alloy nanocrystals.

In yet another embodiment, the method further includes forming a first gate dielectric of oxynitride of an oxide or a compound containing at least one of hafnium, lanthanum, aluminum, and silicon.

In yet another embodiment, the method further includes forming a second gate dielectric of silicon dioxide or silicon oxynitride.

In yet another embodiment, a method of forming a nanocluster charge storage device includes providing a substrate having a memory dopant well associated with the nanocluster charge storage device and a peripheral dopant well associated with a semiconductor device having no nanoclusters; Forming a nanocluster layer embedded in a first gate dielectric overlying the memory dopant well; Forming a first gate material layer overlying the nanocluster layer; Patterning the nanocluster layer and the first gate material layer overlying the memory dopant well; Forming a second gate material layer overlying the peripheral dopant well after formation of the first gate material layer and overlying the nanocluster layer and the first gate material layer; Forming a peripheral device gate stack by removing the second gate material layer from regions other than any peripheral region overlying the peripheral dopant well; And subsequently patterning the nanocluster charge storage device gate stack by patterning the nanocluster layer and the first gate material layer overlying the memory dopant well, wherein the charge storage device gate stack is formed before the second gate material layer. Although formed, it is formed after the formation of the peripheral device gate stack.

In yet another embodiment, the method further includes forming an etch stop layer overlying the first gate material layer for endpoint detection during removal of the second gate material layer overlying the first gate material layer.

In yet another embodiment, a method of forming a nanocluster charge storage device includes providing a substrate having a memory dopant well associated with the nanocluster charge storage device and a peripheral dopant well associated with a semiconductor device having no nanoclusters; Forming a nanocluster layer embedded in a first gate dielectric overlying the memory dopant well; Forming a first gate material layer overlying the nanocluster layer; Patterning the nanocluster layer and the first gate material layer overlying the memory dopant well; Forming a second gate material layer overlying the peripheral dopant well after formation of the first gate material layer and overlying the nanocluster layer and the first gate material layer; Removing the second gate material layer from regions other than a predetermined peripheral region overlying the peripheral dopant well; And forming peripheral device gate stacks and nanocluster charge storage gates substantially simultaneously using a mask.

Many of the devices described herein can be conceptualized as having control terminals that control the flow of current between the first current handling terminal and the second current handling terminal. One example of such a device is a transistor. Under conditions suitable for the control terminal of the transistor, current flows to / from the first current handling terminal and to / from the second current handling terminal. In addition, although field effect transistors (FETs) are often treated as having drains, gates, and sources, the drain is interchangeable with the source for most such devices. This is because the layout of the transistors and the semiconductor processing are frequently symmetrical.

The detailed description above is exemplary and, when “one embodiment” is described, is an exemplary embodiment. Thus, the use of the word "one" in this context does not indicate that only one embodiment may have the features described. Rather, many other embodiments may and may not have the described features of an example “one embodiment”. Thus, as used above, when the invention is described in the context of one embodiment, this one embodiment is one of many possible embodiments of the invention.

Notwithstanding this patent application relating to the use of the term "one embodiment" in the description, those of ordinary skill in the art will expressly cite in the claims, even though a number of elements of a number of introduced claims are intended in the claims below. It will be appreciated that in the absence of such a citation this limitation is either not intended or intended. For example, in the following claims, when a claim component is described as having a "one" feature, it is intended that this component is limited to only one and only one of the described features. Moreover, when a component of the claim is described as including a "single" feature in the claims below, it is not intended that the component be limited to only one and only one of the described features. Rather, for example, a claim that includes a "single" feature is understood to be an apparatus or method that includes one or more of the features. That is, since the device or method includes features, the claims understand the device or method regardless of whether the device or method includes such another similar feature. The use of the singular expression non-limiting to the features of the claims is the same as the interpretation adopted by many courts in the past, in spite of the unusual or precedent legal cases which may be found unusual or unprecedented below. Are adopted here by the guys. Similarly, when a constituent element of a claim is described in the following claims as including the recited feature (e.g., recited feature), the constituent element may be described by one or only of It is not limited.

Furthermore, the use of preliminary phrases such as "at least one" and "one or more" in the claims is true even if the same claim includes "one or more" or "at least one" and a single component as preliminary phrases. The introduction of a single component in this specification should not be construed as limiting any particular claim having a component of this introduced claim to inventions having only one such component. The same is true when using quoted phrases.

Based on the teachings herein, those skilled in the art will readily implement the steps necessary to provide the structures and methods disclosed herein and modifications within which the process parameters, materials, dimensions, and series of steps are given by way of example only and are within the scope of the invention. It will be appreciated that not only the examples can be varied to achieve the desired structure. Variations and modifications of the embodiments disclosed herein may be made based on the description disclosed herein, within the spirit and scope of the invention as set forth in the following claims.

While particular embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that, based on what is taught herein, various modifications, alternative configurations, and equivalents may be used within the invention claimed herein. In the end, the appended claims are intended to embrace within their scope all such changes, modifications, etc. that fall within the true spirit and scope of the invention. It will also be appreciated that the invention is defined only by the appended claims. The above description is not intended to provide an exhaustive listing of embodiments of the invention. Unless expressly stated, each example presented herein is a non-limiting or non-exclusive example, regardless of whether non-limiting, non-exclusive or similar terms are represented with each example. Although attempts have been made to outline certain example embodiments and example variations thereof, other embodiments and / or variations are within the scope of the invention as defined in the claims below.

Claims (12)

In a method of forming a nanocluster charge storage device, Providing a substrate having a first dopant well associated with the nanocluster charge storage device and a second dopant well associated with the semiconductor device having no nanoclusters; Forming the first gate stack overlying the first dopant well, the first gate stack having a first conductive gate material layer forming a gate electrode in the first gate stack, wherein the first conductive gate material layer is a first gate dielectric layer. Forming a first gate stack overlying a plurality of nanoclusters embedded in the first conductive gate material layer, wherein the first conductive gate material layer lies below a portion of the second conductive gate material layer; And Forming the second gate stack overlying the second dopant well using a portion of the second conductive gate material layer overlying the second dopant well as a gate electrode in a second gate stack, wherein the first conductive gate And forming the second gate stack wherein the portion of the second conductive gate material layer overlying the material layer is removed. The method of claim 1, Removing a portion of the second conductive gate material layer overlying the first conductive gate material layer by masking all regions away from the first dopant well and selectively etching the second conductive gate material layer. A method of forming a nanocluster charge storage device. The method of claim 1, Forming the first conductive gate material layer and the second conductive gate material layer using doped polysilicon, metal, or metal alloy. The method of claim 3, wherein And implementing the first conductive gate material layer with a material different from the second conductive gate material layer. The method of claim 1, Forming the first gate dielectric layer comprising forming a gate oxide layer and a second gate oxide layer over and surrounding the nanocluster layer, wherein the first gate dielectric and the first conductive gate material layer Forming the first gate dielectric layer overlying and formed on both the first dopant well and the second dopant well; And Selectively etching the first conductive gate material layer, the first gate dielectric layer, and the nanocluster layer using a combination of wet etching and dry etching from regions overlying the second dopant well. Method of forming a charge storage device. The method of claim 1, Forming the second gate stack by forming a second gate dielectric layer overlying a portion of the second dopant well and the second conductive gate material layer, wherein the second conductive gate material layer overlies the second gate dielectric layer. Further comprising the step of forming a nanocluster charge storage device. The method of claim 6, And forming said second gate dielectric layer of silicon dioxide or silicon oxynitride. The method of claim 1, Forming a nitride layer on the first gate stack and overlying the first conductive gate material and lying between the first conductive gate material and the second conductive gate material portion; Forming an oxide layer overlying the nitride layer and in physical contact therewith, the nitride layer and oxide layer functioning as an etch stop layer when removing the second conductive gate material and the nitride layer also forming the first gate stack. And forming the oxide layer that functions as an antireflective coating when forming the gate electrode. The method of claim 1, Forming said first gate dielectric layer of oxide or of an oxynitride of a compound containing at least one of hafnium, lanthanum, aluminum, and silicon. The method of claim 1, Forming the layer of doped or undoped semiconductor nanocrystals, metal nanocrystals, nanocrystals of two or more doped or undoped semiconductors, or metal alloy nanocrystals to form the first dopant layer well and the Forming a plurality of nanoclusters embedded in the first gate dielectric layer overlying a second dopant well. The method of claim 1, Forming a first source and a first drain around the first gate stack and in the first dopant well to form the charge storage device as a nonvolatile memory (NVM) transistor; And Forming a second source and a second drain around the second gate stack and in the second dopant well to form a peripheral transistor. The method of claim 1, Forming a semiconductor device from the second gate stack, wherein the semiconductor device enables charging and discharging of the nanocluster charge storage device.

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