KR20070023012A - Apparatus and method for controlling flow in ethernet - Google Patents

Abstract

An apparatus and method for controlling the flow of an Ethernet frame received using a common public radio interface (CPRI) link, comprising: a buffer for storing the Ethernet frame received from a partner station; and a storage amount of the Ethernet frame stored in the buffer. Including a buffer control unit for controlling the flow of the received Ethernet frame by measuring the advantage of preventing the loss of the Ethernet frame.

Common Public Radio Interface (CPRI), Ethernet, FIFO, Stop Message, Transmission Request Message

Description

{APPARATUS AND METHOD FOR CONTROLLING FLOW IN ETHERNET}

1 is a diagram illustrating a base station structure according to the CPRI standard according to the present invention;

2 is a diagram illustrating a procedure for preventing an error due to a line bit rate provided by an Ethernet standard and a CPRI link according to an embodiment of the present invention; and

3 is a diagram illustrating a control message structure for flow control according to an embodiment of the present invention.

The present invention relates to a flow control apparatus and method for transmitting an Ethernet frame, and more particularly, to an apparatus and method for preventing an error due to a difference between a line bit rate provided by an Ethernet standard and a common public radio interface (CPRI) link. It is about.

Recently, wireless communication is changing from voice center to data center. The data-oriented communication requires a high transmission rate and high reliability, and thus requires a complicated and expensive base station. Accordingly, in order to reduce the cost of the base station and to efficiently transmit and receive a base station, standardization for an interface between base stations in a 3rd generation mobile communication network is in progress.

Representative standardization organizations for the 3G base station interface include the OBSAI (The Open Base Station Architecture Initiative) and CPRI (Common Public Radio Interface). First, the OBSAI was formed by alliance of Nokia, Samsung Electronics, LG Electronics and Hyundai Syscom. The OBSAI is composed of a transport module, a processing module, a radio module, and a control module. Each base station can be manufactured to meet different requirements.

Next, the CPRI was formed by a combination of Ericsson, Huawei, Siemens, Nortel, and the like. The CPRI defines a standard for the main internal interface of a radio base station. That is, the base station is divided into a REC (Radio Equipment Control) and a RE (Radio Equipment) for flexibility of the system structure to define an interface between the REC and the RE.

The CPRI link according to the CPRI standard is synchronized with I / Q (In-phase / Quadreture) data, control and management (hereinafter referred to as C & M) data and data, which are data transmitted and received through an actual antenna. Three data such as (Sync) data transmit a time domain multiplexed signal.

Line bit rates of the CPRI link are defined as 614.4 Mbps, 1228.8 Mbps, and 2457.6 Mbps, respectively, and a high level data link control (HDLC) format for a slow C & M channel. It supports the Ethernet format for fast C & M channels.

Only 20 to 63 subchannels are used to transmit the Ethernet frame among the 64 subchannels constituting the CPRI. That is, when the Ethernet frame is transmitted, all the subchannels 20 through 63 are used for maximum transmission, and only one subchannel is used for the minimum transmission.

The bit rate of the Ethernet frame transmitted through the CPRI link is calculated using Equation 1 below.

Here, B _L represents the line bit rate of the CPRI link, and 16 is used because only one word is used for control among 16 words of the basic frame. X represents the number of subchannels used for transmitting Ethernet frames, 64 represents the total number of subchannels, and 4/5 represents the code rate.

)~21.12(

)Mbps, B_L이 1228.8Mbps일 경우 0.96(

)~42.2(

)Mbps, B_L이 2457.6Mbps일 경우 1.92(

)~84.4(

)Mbps의 이더넷 프레임의 전송 비트율을 갖는다.Computing Equation 1 above, when B _L is 614.4 Mbps, 0.48 (

) ~ 21.12 (

Mbps, 0.96 for B _L of 1228.8 Mbps

) ~ 42.2 (

Mbps, 1.92 (when B _L is 2457.6 Mbps)

) ~ 84.4 (

) Has a transmission bit rate of Ethernet frames of Mbps.

The actual Ethernet frame used uses 10M standard Ethernet or 100M standard Ethernet. If the system uses 10M standard Ethernet, the downlink supports up to 21.12 Mbps Ethernet frame transmission over the CPRI link in 614.4 Mbps mode, but no problem occurs. When the Ethernet frame is transmitted, the buffer becomes saturated because the speed of the Ethernet frame stored in the buffer is faster than the speed transmitted from the buffer to the Ethernet MAC.

Accordingly, an object of the present invention is to provide an apparatus and method for preventing an error due to a difference in line bit rates provided by an Ethernet standard and a CPRI link when using the Ethernet frame transmission function of the CPRI standard.

Another object of the present invention is to provide an apparatus and method for preventing a FIFO full error caused by a difference in the line bit rate provided by the Ethernet standard and the CPRI link when using the Ethernet frame transmission function of the CPRI standard.

A first aspect of the present invention for achieving the above object, the apparatus for controlling the flow of the Ethernet frame received using a Common Public Radio Interface (CPRI) link, and a buffer for storing the Ethernet frame received from the other station; And a buffer controller for controlling the flow of the received Ethernet frame by measuring a storage amount of the Ethernet frame stored in the buffer.

According to a second aspect of the present invention, a method for controlling the flow of an Ethernet frame received using a common public radio interface (CPRI) link includes: comparing a first reference value by measuring a storage amount of the Ethernet frame stored in a buffer; And transmitting the transmission stop message to the counter station when the storage amount is larger than the first reference value.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, the present invention describes a technique for preventing an error due to a difference between a line bit rate provided by an Ethernet standard and a common public radio interface (CPRI) link.

1 illustrates a base station structure according to the CPRI standard according to the present invention.

As shown in FIG. 1, the base station includes a downlink Ethernet MAC 101, an uplink Ethernet MAC 102, a first input first output (FIFO) buffer 103, a FIFO control unit 105, and an I / Q (In). Phase / Quadreture Data Channels (107, 119), Sync Data Channels (109, 117), Control & Management (C & M) Data Channels (111, 115), Multiplexer (113) and Demultiplexer (De) A multiplexer (121).

First, the downlink Ethernet MAC 101 generates a MAC message by receiving data to be transmitted from an upper end. The FIFO buffer 103 temporarily stores data provided from the downlink Ethernet MAC 101 or data received from another base station under the control of the FIFO controller 105. In addition, the FIFO buffer 103 transmits data provided from the downlink Ethernet MAC 101 for each channel (I / Q data channel 107, synchronous data channel 109, C & M data channel 111). Therefore, the data is separated for each channel and provided to the I / Q data channel 107, the synchronization data channel 109, and the C & M data channel 111.

The FIFO controller 105 checks the amount of data stored in the FIFO buffer 103 and adjusts the amount of data provided to the FIFO buffer 103 so that no overflow occurs in the FIFO buffer 103. .

For example, we use 10 Mbps of standard Ethernet and assume a line bit rate of CPRI link of 614.4 Mbps. In addition, the CPRI link transmits at the maximum speed of the Ethernet frame (21.12 Mbps).

If the speed (21.12 Mbps) of the received Ethernet frame stored in the FIFO buffer 103 is faster than the speed (10 Mbps) transmitted from the FIFO buffer 103 to the uplink Ethernet MAC 102, the FIFO control unit 105 When the amount of data stored in the FIFO buffer 103 is checked and the value exceeds the first reference value, the transmission stop message is transmitted to the counterpart station transmitting the Ethernet frame to prevent the overflow of the FIFO buffer 103.

In addition, when the received Ethernet frame is interrupted and the data storage amount of the FIFO buffer 103 is less than or equal to the second reference value, the transmission request message is transmitted to the counterpart station. Here, the transmission stop message and the transmission request message are transmitted through the first C & M data channel 111.

The first I / Q data channel 107 transmits I / Q data, which is transmission data provided from the FIFO buffer 103, and the first synchronous data channel 109 is provided from the FIFO buffer 103. The synchronization data for synchronizing the synchronization and timing of each received base station is transmitted. The first C & M data channel transmits a control and management signal provided from the FIFO buffer 103. Furthermore, according to the present invention, the transmission stop message and the transmission request message transmitted from the FIFO control unit 105 are transmitted.

The multiplexer 113 time-domain the I / Q data, the synchronization data, and the C & M data provided from the first I / Q data channel 107, the first synchronization data channel 109, and the first C & M data channel 111. Multiplexing the data to the destination station.

The demultiplexer 121 demultiplexes I / Q data, synchronous data, and C & M data of the Ethernet frame received from the counterpart station to demultiplex the second I / Q data channel 115, the second synchronous data channel 117, and the second C & M. Transmit to data channel 119.

The second I / Q data channel 115 transmits I / Q data, which is received data provided from the demultiplexer 121, to the FIFO buffer 103, and the second synchronous data channel 117 is the demultiplexer. Synchronization data for synchronizing synchronization and timing of each base station received from 121 is transmitted to the FIFO buffer 103. The second C & M data channel transmits the control and management signals provided from the demultiplexer 121 to the FIFO buffer 103.

The uplink Ethernet MAC 102 transmits the received data provided from the FIFO buffer 103 to the upper end.

2 illustrates a procedure for preventing an error due to a line bit rate provided by an Ethernet standard and a CPRI link according to an exemplary embodiment of the present invention. The following description assumes receiving Ethernet frames transmitted at the maximum rate (21.12 Mbps) in a CPRI link having a line bit rate of 614.4 Mbps in the up-link direction.

Referring to FIG. 2, first, when a base station receives an Ethernet frame through a CPRI link from another base station in step 201, the received Ethernet frame includes a second I / Q data channel 115 and a second synchronous data channel 117. ) And the second C & M data channel 119 in the FIFO buffer 103.

In step 203, the base station checks the data storage amount (= P) of the FIFO buffer 103. After checking the data storage amount of the FIFO buffer 103, the base station proceeds to step 205 to compare the P and the first reference value. That is, the FIFO buffer 103 checks whether an overflow occurs. If P is less than or equal to a first reference value (P ≦ first reference value), the base station returns to step 201 to continue receiving the Ethernet frame.

If P is greater than the first reference value (P> first reference value), the base station proceeds to step 207 and anticipates that an overflow occurs in the FIFO buffer 103 and transmits a transmission stop message to the counterpart station.

In step 209, the base station reconfirms the data storage amount P ₁ of the FIFO buffer 103. After confirming the data storage amount of the FIFO buffer 103, the base station proceeds to step 211 to compare the P ₁ and the second reference value. That is, since transmission of the Ethernet frame is stopped from the counterpart station, it is checked whether the data storage amount of the FIFO buffer 103 is reduced to receive the Ethernet frame again.

If P ₁ is greater than the second reference value (P ₁ > second reference value), the base station returns to step 209 to check the data storage amount of the FIFO buffer 103 again. If P ₁ is less than or equal to the second reference value (P ₁ ≤ second reference value), the base station proceeds to step 213 and transmits a transmission request message requesting to transmit the Ethernet frame again to the counterpart station. The base station then terminates this algorithm.

Here, the transmission stop message and the transmission request message use one byte as shown in FIG. 3 among the subchannels 3 to 15 that are reserved in the subchannels of the CPRI hyper frame. That is, if 1 byte 301 of FIG. 3 is 1, transmission of the Ethernet frame is stopped, and if 0, transmission of the Ethernet frame is requested.

In addition, since one hyper frame in the CPRI link is 66.67 μs, the state of the FIFO buffer 103 may be informed to the counterpart station every 66.67 μs.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, when the Ethernet frame transmission function is used in the CPRI link, the data storage amount of the buffer is checked to prevent an error caused by the difference between the CPRI standard and the line bit rate provided by the CPRI link. By controlling the flow compared to the preset reference value, there is an advantage that can prevent the loss of the Ethernet frame.

Claims (11)

An apparatus for controlling the flow of an Ethernet frame received using a common public radio interface (CPRI) link, A buffer for storing the Ethernet frame received from the other station; And a buffer controller for controlling the flow of the received Ethernet frame by measuring a storage amount of the Ethernet frame stored in the buffer. The method of claim 1, The buffer control unit, And measuring a storage amount of the Ethernet frame stored in the buffer and transmitting a transmission stop message to the counterpart station when the storage amount is greater than or equal to a first reference value. The method of claim 2, The transmission stop message is, And transmitting one byte of a reserved subcarrer included in the CPRI hyper frame as one. The method of claim 2, The buffer control unit, And after transmitting the transmission stop message, when the Ethernet frame storage amount of the buffer is less than or equal to a second reference value, transmitting the transmission request message. The method of claim 4, wherein The transmission request message, And transmitting one byte of a reserved sub-channel included in the CPRI hyper frame as 0. The method of claim 1, The buffer is characterized in that the fast input fast output (FIFO) buffer. In the method for controlling the flow of Ethernet frames received using a common public radio interface (CPRI) link, Comparing a first reference value by measuring a storage amount of the Ethernet frame stored in a buffer; And transmitting the transmission stop message to a counter station when the storage amount is larger than the first reference value. The method of claim 7, wherein The buffer is a fast input fast output (FIFO) buffer. The method of claim 7, wherein The transmission stop message is, And transmitting one byte of a reserved sub-channel included in the CPRI hyper frame as one. The method of claim 7, wherein After transmitting the transmission stop message, comparing the Ethernet frame storage amount of the buffer with a second reference value; If the amount of Ethernet frame storage is less than or equal to a second reference value, transmitting the transmission request message to the counterpart station. The method of claim 11, The transmission request message, And transmitting one byte of a reserved sub-channel included in the CPRI hyper frame as 0.

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