KR20070022196A - Display device driving circuit - Google Patents

Abstract

The present invention provides a driving circuit capable of reducing power consumption in an amplifier for outputting a target voltage. A drive circuit for driving a capacitive load of the display device Ccol, comprising: drive signal supply means 10 for supplying a drive signal Vin having a target voltage to be applied; An amplifying step 20 for receiving the drive signal Vin and optionally outputting the drive signal Vin to the capacitive load Ccol; And a pair of current sources Icpp, Ipcn for selectively supplying positive and negative currents to the capacitive load Ccol, respectively during their on-state. The drive circuit has a pre-operation and amplification step 20 in which any one of the current sources Icpp, Ipcn is switched on according to the drive signal Vin and then switched off after the pre-operation of the drive signal Vin. The repetitive operation is repeated, including post-operation switching to a state for output to the capacitive load Ccol.

Description

Display device drive circuit {DISPLAY DEVICE DRIVING CIRCUIT}

 The present invention relates generally to a driving circuit of a display device. Specifically, the present invention relates to a driving circuit for supplying a target voltage signal to a capacitive load in a display device, and more particularly, to apply a voltage corresponding to a pixel information signal to a column electrode of a display device such as a liquid crystal display panel. It relates to a display drive circuit for.

Patent document 1 describes this type of drive circuit. This drive circuit switches on the pre-charged switching element previously in the buffer amplitude section when the common voltage is inverted in horizontal period units to pre-charge the output terminal to a supply potential or ground potential. The potential difference is reduced or increased to an intermediate potential by operating the select switching element. In this way, since the output voltage is moved to the intermediate potential after being pre-charged to the power supply potential or the ground potential, it is possible to apply the desired voltage to the liquid crystal capacitance faster when the target voltage is close to the intermediate potential.

However, in the driving circuit of document 1, since the output terminal connected to the load is once stabilized at the target voltage after being moved to the intermediate potential, the output voltage can change from the intermediate potential to the target voltage level, which is the target voltage level. Not exactly equal to, may cause a loss in driving the load. Therefore, the amplifier for outputting the target voltage can consume unnecessary power. This consumption is particularly important in devices that can use target voltage levels that differ significantly from the intermediate potentials, ie systems operating over a wider operating range.

[Patent Document 1]

Laid-open Japanese Patent Application No. 122733/96 (see in particular paragraphs [0054] to [0057], [0065], [0066] and [0074])

(purpose)

In view of the foregoing, it is an object of the present invention to provide a driving circuit capable of reducing the power consumption of an amplifier for outputting a target voltage.

Another object of the present invention is to provide a driving circuit that can contribute to power saving.

(Configuration)

To achieve the above object, a drive circuit according to the first aspect of the present invention is a drive circuit for driving a capacitive load of a display device: drive signal supply means for supplying a drive signal having a target voltage to be applied. and; An amplifying step for receiving the drive signal and optionally outputting the drive signal to a capacitive load; And a pair of current sources for selectively supplying a positive current and a negative current to the capacitive load, respectively during the on-state, wherein the driving circuit is switched on according to the drive signal after any one of the current sources is switched on. The pre-operation and amplification steps that are switched off repeat an iterative operation that includes a post-operation that switches to a state for outputting the drive signal to the capacitive load after the pre-operation.

In this way, since the capacitive load is charged and discharged by the current source, the output voltage gradually changes to the target voltage, thereby suppressing drive loss to the load.

In this aspect, the duration length of the ON period of the associated current source and / or the current supply rate of the associated current source during pre-operation may vary depending on the value of the drive signal in the repetition period of the repetitive operation. It is thus possible to make the target voltage and the output substantially equal on the basis of a predetermined reference voltage after the pre-operation is completed, and the amplification step should therefore only operate to output the subsequent stable voltage, thus unnecessary The power consumption can be suppressed to the maximum possible.

In addition, the duration length of the ON period of the relevant current source and / or the current supply ratio of the relevant current source during pre-operation may be determined by the value of the drive signal in the repetition period of the repetitive operation and the value of the drive signal in another repetition period before the repetition period. It can be changed according to the value. In this way, the output can be made substantially equal to the target voltage after the pre-operation is completed without using the reference voltage.

Alternatively, a drive circuit according to another aspect of the present invention is a drive circuit for driving a capacitive load of a display device, comprising: drive signal supply means for supplying a drive signal having a target voltage to be applied; An amplifying step for receiving a drive signal and optionally outputting the drive signal to a capacitive load; A pair of power sources for selectively performing charging and discharging to the capacitive load, respectively; And comparison means having one input for receiving a voltage value of a drive signal and another input for receiving a voltage value on an output line connected to the capacitive load, wherein the drive circuit is configured to charge and discharge any power source. The pair of pre-operation and amplification steps performed by one then repeats the repetitive operation including a post-operation that switches to a state for outputting a drive signal to the capacitive load after the pre-operation, the pair The charging and discharging operations performed by the power supply of are controlled based on the comparison output of the comparing means during the pre-operation.

By doing so, whenever the value of the drive signal is updated, it is possible to achieve appropriate charge / discharge control adapted to the value of the drive signal in pre-operation.

This aspect may take the following method: discharge operation is performed when the comparison output indicates that the voltage value on the output line is greater than the voltage value of the drive signal, and the comparison output indicates that the voltage value on the output line is less than the voltage value of the drive signal. If indicated, a charging operation is performed; In addition, one of the charging and discharging operations is that the comparison output is continued until the voltage value on the output line reaches the voltage value of the drive signal.

In the foregoing aspects and their embodied forms, the target voltage can be a grayscale voltage, the capacitive load can be a liquid crystal cell and / or the drive signal supply means can comprise analog-to-digital conversion means. Thus, it is possible to take full advantage of the foregoing advantages in the display device.

The present invention also provides a display device utilizing the features of the above-described drive circuit.

It should be noted that the amplifying step should only take the form of selectively outputting the drive signal, and therefore it should be understood that this step includes a form without an amplifier, as described below.

1 is a block diagram showing a schematic configuration of a drive circuit according to a first embodiment according to the present invention;

FIG. 2 is a time diagram illustrating operation in a drive circuit as shown in FIG. 1. FIG.

3 is a block diagram showing a schematic configuration of a driving circuit according to a second embodiment of the present invention.

4 is a time diagram illustrating the operation of a drive circuit as shown in FIG.

Fig. 5 is a block diagram showing a schematic configuration of a drive circuit of a modification according to the present invention.

FIG. 6 is a block diagram showing a configuration upstream from a drive signal, including a control signal generation circuit used in each embodiment. FIG.

Fig. 7 is a table showing a data storage state in a look-up table memory in the control signal generation circuit.

8 is a conceptual diagram illustrating a relationship between a gray scale level and a driving voltage level.

9 is a block diagram showing a schematic configuration of a drive circuit according to a third embodiment (3) of the present invention.

FIG. 10 is a time diagram illustrating operation in a drive circuit as shown in FIG. 9; FIG.

11 is a block diagram showing a schematic configuration of a drive circuit according to a modification of the present invention.

12 is a time chart showing operation in a drive circuit as shown in FIG.

Fig. 13 is a block diagram showing a schematic configuration of a drive circuit according to another modification of the present invention.

Best mode

Embodiments of the present invention embodied will now be described more specifically by examples with reference to the accompanying drawings.

1 shows a schematic configuration of a driving circuit according to a first embodiment of the present invention.

The drive circuit is for driving a capacitive load of the display device, and in this embodiment, it is a drive circuit for supplying pixel information signals to each column electrode of a passive or active matrix type liquid crystal display panel.

The drive circuit includes a gray-scale voltage generation circuit 10 in a first step, which serves as a drive signal supply terminal for supplying a target voltage to be applied to the drive signal, and the generation circuit 10 Has the function of digital-to-analog switching. The gray-scale voltage generation circuit 10 includes a voltage division circuit formed of a plurality of resistance elements connected in series with each other. As shown in FIG. 1, the voltage dividing circuit 10 is connected to a positive power supply voltage Vdd at one end while to a negative power supply voltage Vss at the other end. The voltage dividing circuit 10 divides the voltage between Vdd and Vss, and generates a plurality of gray-scale voltages having stepwise increase or decrease gradients. Common connection points of the resistive elements are each connected to one end of the switching element. The other ends of the switching elements are all connected in common and are led as the output end of the gray-scale voltage generation circuit 10. The switching elements can be individually controlled and any one of the switching elements is switched on in accordance with the input pixel information signal Vdata. In this way, only the switched-on switching element relays the gray-scale voltage corresponding to the gray-scale level indicated by the pixel information signal Vdata among the various gray-scale voltages made in the division circuit, and is replaced. The drive signal Vin with the gray-scale voltage is output.

The drive circuit further has an amplification step 20 for receiving a drive signal Vin. The amplification step 20 comprises a pair of switching elements (SW-) connected to each of the signal input and output terminals and the amplifier 21 having positive and negative power terminals, and the signal output terminals of the positive power terminal and the amplifier 21, respectively. A ₀ and SW-A ₁ ). One of the switching elements SW-A _{0 is} connected at one end to the positive power supply terminal of the amplifier 21, while at the other end to the positive power voltage Vdd. The other of the switching elements SW-A _{1 is} connected at one end to the signal output terminal of the amplifier 21, while at the other end to the output line 40. The pair of switches SW-A ₀ and SW-A ₁ are synchronized with each other in ON / OFF operation, and are simultaneously turned on or off in response to a common control signal C _A. When the pair of switches SW-A ₀ and SW-A ₁ are ON, the drive signal Vin from the gray-scale voltage generation circuit 10 is output via the activated amplifier 21 to the output line 40. Is output. When the pair of switches SW-A ₀ and SW-A ₁ are OFF, the amplifier 21 is not powered by the power source and the output line 40 so that the amplifier 21 does not involve power consumption. Is separated from. The embodiment is a means for controlling the drive signal Vin whether or not to relay to the output line 40, the configuration based on a pair of switches, that is, two switches, SW-A ₀ and SW-A ₁ It is intended to be used. However, such means can be arranged for using a configuration with only one switch SW-A ₀ , which controls the power supply to the amplifier 21.

The drive circuit further has an output stage 30 coming down from the amplifying stage 20. The output stage 30 is, as a basic structural element, a current source Icpp (preferably stabilized) which is connected with a positive supply voltage Vdd and generates a positive current (current flowing into the output line 40) and It is provided with a current source Ipcn (preferably stabilized) which is connected to the negative supply voltage Vss and generates a negative current (flowing from the output line 40). The output stage 30 further comprises switches SW-B and SW-C connected respectively between the current source Icpp and the output line 40 and between the current source Ipcn and the output line 40. The switches SW-B and SW-C control the conduction / non-conductivity between the current sources Icpp, Ipcn and the output line 40, and are individually individually switched ON or OFF according to the control signals C _B and C _C. Can be controlled. When the switch SW-B is ON, the current of the positive pole from the current source Icpp is supplied to the output line 40 through the switch SW-B. When the switch SW-C is ON, the current of the cathode from the current source Ipcn is supplied to the output line 40 through the switch SW-C. It is noted that in this embodiment only one of the switches SW-B and SW-C is allowed to be switched on, and control for switching them simultaneously is not allowed.

In this embodiment, the output line 40 is connected to a column electrode extending in the longitudinal direction in the liquid crystal display panel. The column electrode designates one potential for determining the optical state of the pixel of the liquid crystal medium in the liquid crystal display panel, and partially applies a voltage to the liquid crystal medium in cooperation with, for example, the so-called common electrode 50 which specifies the other potential. . In this case, the column electrode and the liquid crystal medium can be regarded as the equivalent capacitance Ccol inserted between the output line 40 and the common electrode 50. The drive circuit supplies the drive signal to the equivalent capacitance Ccol as a capacitive load. This embodiment may encompass a configuration in which an active element such as a TFT (thin film transistor) is provided to each pixel and one potential is given to the pixel according to a driving signal supplied to the column electrode through the active element, and the common electrode 50 It is noted that may encompass a configuration that extends in the longitudinal direction and is replaced by row electrodes that intersect the column electrodes.

The operation of the drive circuit will be described below with reference to the time diagram of FIG.

In the horizontal scanning period 1H, which is the update period of the drive signal Vin carrying the gray-scale voltage, the drive circuit is pre-operated and the amplification step 20 in the output step 30 based on the current source is ultimately pre-set. Perform a basic operation including a post-operation that stabilizes the output line 40 at the potential of the drive signal Vin after operation.

More specifically, in the horizontal scanning period, only the switch SW-B is first switched on in the output step 30 (t1). The output current of the current source Icpp thus flows into the output line 40, the equivalent capacitance Ccol is charged with the current and the voltage between the opposite ends gradually increases (see t1-t2 in Vout (1)).

After the predetermined time period T ₀ has elapsed (t2), the switch SW-B is switched off, and the switches SW-A ₀ and SW-A ₁ are switched on. Thus, charging of the equivalent capacitance Ccol due to the current source Icpp is stopped while the output of the amplifier 21 is supplied to the output line 40. Therefore, in the horizontal scanning period, the amplifier 21 relays the drive signal Vin having the target gray-scale voltage specified by the pixel information signal Vdata to the output line 40, and the output line 40 is driven. Converge to the signal level (see t2-t3 in Vout (1)).

Also in the next horizontal scanning period, a series of operations are performed including the operation of the switch in the output stage 30 and the operation of the amplification stage 20. However, after driving with the anode is performed as in the period from t1 to t3, the driving is performed at the cathode. Therefore, in this horizontal scanning period, only the switch SW-C is switched ON (t3), the current is moved from the output line 40 to the current source Ipcn, and the equivalent capacitance Ccol is the current. Discharged together, and the voltage between the opposite ends gradually decreases (see t3-t4 in Vout (1)). Then, if the predetermined time period T ₀ likewise elapses (t4), the switch SW-C is switched off and the switches SW-A ₀ and SW-A ₁ are switched on. Thus, the discharge of the equivalent capacitance Ccol due to the current source Ipcn is stopped while the output of the amplifier 21 is supplied to the output line 40. Therefore, in the horizontal scanning period, the amplifier 21 relays the drive signal Vin having the target gray-scale voltage specified by the pixel information signal Vdata to the output line 40, and the output line 40 drives. Converge to signal level (see t4- in Vout (1)).

Thus, the drive circuit is a pre-operation in which only one of the current sources Icpp and Ipcn is switched on and then switched off in accordance with the drive signal Vin while the drive polarity is changed every horizontal scanning period, Repeat the repetitive operation, including a post-operation in which the amplification step 20 is switched to a state for outputting the drive signal Vin with an equivalent capacitance Ccol such as a capacitive load after the operation is performed. .

According to the driving circuit having the configuration and operation as described above, it is possible to provide the advantageous effects specified in the present invention. In other words, since the equivalent capacitance Ccol is charged and discharged using the current sources Icpp and Ipcn in the output stage 30, the voltage of the output line 40 gradually approaches the target voltage, and the change of the voltage is thus It is more flexible than in the case of using a voltage source, so that it is possible to suppress the driving loss of the equivalent capacitance.

The beneficial effect is by setting the length of the ON period (pre-charge period) for operating the current sources Icpp and Ipcn in the output step 30 to vary (T ₀ ) inconsistently, and the input signal Vdata or drive It can be made more remarkable by changing the length of the period in accordance with the signal Vin. 2 shows an example of this case at 'Vout (2)'. At the output voltage Vout (2), the pre-charge period of the current sources Icpp and Ipcn is the time period according to the drive signal Vin in the horizontal scanning period (ie, the time period required to charge / discharge to the target voltage). (T ₁ and T ₂ ), the switches SW-A ₀ , SW-A ₁ , SW-B and SW-C are controlled in correspondence to the periods T ₁ and T ₂ , whereby the voltage is The periods change without useless conversion as compared to the case where the periods are set to constant time periods T ₀ . In this way, the equivalent capacitance can be suppressed as much as possible in driving and limits the power consumption in the amplifier 21 to the minimum level required.

Even if the embodiment adopts a so-called change-current driving system in which the target voltage having a positive pole and the target voltage having a negative pole are outputted in units of a horizontal scan period with respect to a reference potential applied to the common electrode 50, the present invention is carried out. The invention is not limited to this change-current drive form. When the target voltage represented by the drive signal Vin in the current horizontal scanning period is higher than the target voltage represented by the drive signal Vin in the previous horizontal scanning period, the switch SW-B is a current source Icpp that enables charging. It can be switched on in the current horizontal scanning period to use. On the other hand, when the former is lower than the latter, the switch SW-C can be switched on in the current horizontal scanning period to use the current source Ipcn to enable the discharge. In this modified form, it is possible to properly output the target voltage with the same polarity for successive horizontal scanning periods. The same modifications can be made in the embodiments described below.

Although the embodiment described above is based on the control of the length of the pre-charge time period of the current sources Icpp and Ipcn, it is possible to control the current supply performance of the current sources Icpp and Ipcn, i.e., the pre-charge ratio or the next current supply ratio. There may be cases.

3 shows a variable current supply ratio type driving circuit, where instead of a constant ratio type of current sources Icpp and Ipcn, a variable ratio type of power supply Ipcpv and Ipcnv is employed, and control signals CI _B and CI _C ) is input to the current sources Ipcpv and Ipcnv to specify the appropriate angular ratio for the current source.

4 shows the operation in a variable current ratio type drive circuit, wherein the pre-charge period is maintained for a constant time period T ₀ , and the current supply ratio of the current sources Ipcpv and Ipcnv is driven by the drive signal Vin. It is set to a value required for the output line 40 to reach the target voltage within a certain time period T ₀ according to the value of. Thus, as evident in the case of setting the current supply ratio to a fixed value as shown in broken lines in 'Vout' of Figure 4, the pre-even if the fixed-charge period, a constant time period (T ₀₎ has passed a Afterwards, control can be performed so that the output voltage nearly reaches the target voltage.

The configuration of FIG. 3 is applicable when making both the length and the ratio of the period of pre-filling variable. In other words, the control signals C _B and C _C and the ratio control signals CI _B and CI _C for the switches SW-B and SW-C are pre-set to appropriate values depending on the value of the drive signal Vin. It can be determined to set the filling period length and ratio.

Furthermore, according to the form for controlling at least one of the pre-charge period length and the ratio according to the value of the drive signal Vin, since the output voltage has already reached the drive voltage after the charge / discharge operation is completed by the current source, Unlike the conventional case, the need for the amplifier to ultimately set the output line at the target voltage is dramatically reduced. Therefore, as shown in FIG. 5, if the applied device or system allows removal of the amplifier 21, it may do so. In this way, the power to be consumed in the amplifier 21 is completely eliminated, thus making a significant contribution to power savings in the overall drive circuit.

The following describes how to specifically set the pre-charge period length and ratio. Fig. 6 shows the configuration above from the drive circuit, which includes a circuit for generating the control signals C _A , C _B and C _C.

The digital image signal (D _V) supplied from a not shown, the signal system, while the one stored in the memory 110 of the two circuits, the output of the read from the memory 110 is sent to the decoder 120. The memory 110 may store image data corresponding to two horizontal scanning periods. For example, the stored image data represents the absolute value of the gray-scale level of each pixel in the form of 6 bits per pixel, and further represents the pole of the gray-scale level of each pixel using an additional 1 bit.

When the data stored in the memory 110 is transmitted to the decoder 120 as current data which is data corresponding to the horizontal scanning period which is about to be currently displayed, the decoder 120 is connected to a certain switching element in the gray-scale voltage generation circuit 10. Decodes the transmitted data to determine whether is to be turned on, and generates a pixel information signal (Vdata) according to the decoding result. As described above, the gray-scale voltage generation circuit 10 switches on a switch corresponding to the gray-scale level according to the pixel information signal Vdata, thus supplying a corresponding drive signal Vin to a later stage of the circuit. do.

The output of the memory 110 is also sent to the control signal generation circuit 130. The control signal generation circuit 130 includes a LUT memory 131, which receives not only the current data but also the previous data, that is, it also receives the data of the horizontal scanning period immediately before the horizontal scanning period to be currently displayed, And control signals C _B and C _C based on the last data.

7 conceptually illustrates data stored in LUT memory 131. In the table of FIG. 7, the previous pixel data types are displayed in rows, the current pixel data types are displayed in columns, with the high / low and black / white levels of the driving voltage levels, and the respective rows and columns intersect each other. The part represents the value currently set for the control signals C _B and C _C. For example, when the previous pixel data represents the value of '2' of the cathode and the current pixel data represents the value of '1' of the anode, the interval of 'N2P1' determines how to set the control signals C _B and C _C. Store the data that is displayed. When the current pixel data is the same as the previous pixel data, the values of the control signals C _B and C _C are not changed, and the interval in this case represents '0'.

The section of '0' forms a diagonal line from the upper left corner of the table to the lower right corner. The section above the diagonal corresponds to selecting the switch SW-B in the horizontal scanning period, while the section below the diagonal corresponds to selecting the switch SW-C in the horizontal scanning period.

Data representing the duration length of the pre-charged period, such as data representing the settings for the control signals C _B and C _{C to be} stored, are used in embodiments for changing the pre-charge period, or the pre-charge rate The data representing is used in the examples to change the pre-fill rate. Furthermore, in the case of control based on the charging ratio, in the configuration of FIG. 6, the LUT memory 131 outputs control signals CI _B and CI _C.

For example, the duration length or charge rate of the period shown in the section of 'N0N2' is greater than that shown in the section of 'N0N1'. This means that when the voltage level is changed by one step (N0N1) from the highest black level of the cathode to the black level close to white, as shown in FIG. This is because the change must be made larger when changing by 2 steps (N0N2).

Furthermore, assuming the value of the duration length of the pre-charge period in the intervals N0N1, N0N2, ..., which will be denoted as tN0N1, tN0N2, respectively, the following relationship is for example gamma to the display image. Allow the property to be provided and adjust the difference value in each period.

(tP0N0-tP0N1)> (tP0N1-tP0N2)> (tP0N2-tP0N3)> ...

Similarly, assuming the values of the pre-charge ratios in the intervals N0N1, N0N2, ..., which will be denoted by IpN0N1, IpN0N2, ..., respectively, the above relationship can be replaced by the following relationship.

(IpP0N0-IpP0N1)> (IpP0N1-IpP0N2)> (IpP0N2-IpP0N3)> ...

Thus, by defining control signals C _B and C _C (or CI _B and CI _C ) to indicate the determined duration length and / or the determined pre-charge ratio of the pre-charged period, the appropriate pre- It is possible to control charging.

A configuration such as that shown in FIG. 9 can be used as an example to simplify the control of pre-charging.

In the configuration of FIG. 9, an additional pair of switches is further provided in the downward direction at the output stage 30 in the configuration shown in FIG. 3. The pair of switches is a switch (SW-D) for connecting the positive power supply voltage (Vdd) and the output line 40, and a switch (SW-) for connecting the negative power supply voltage (Vss) and the output line (40). E).

In this configuration, as shown in FIG. 10, in the pre-charge time periods TP ₀ and TP ₁ , the switch SW-D is driven according to the drive signal when the drive signal Vin is induced with positive drive. It is ON first for a predetermined time period T ₀ ′ or the switch SW-E is preferentially ON for a predetermined time period T ₀ ′ according to the drive signal when the drive signal Vin is induced with negative driving. Thus, the output voltage is once raised to the maximum level (Vdd) or to the minimum level (Vss) of the power supply voltage, respectively. Then, the switch SW-B or SW-C is controlled to be ON according to the drive signal Vin in the horizontal scanning period. As can be seen in FIG. 10, when the switch SW-C is selected, the discharge is performed by the current source Ipcnv, and the voltage is reduced to the target voltage. On the other hand, when the switch SW-B is selected, charging is performed by the current source Ipcpv, and the voltage is increased to the target voltage.

In this configuration, the control of the pre-charge to the target voltage is based on the duration length of the pre-charge period using the control signals C _B and C _{C or} by using the control signals CI _B and CI _C. It can be based on pre-fill rate.

In this way, the value of the duration length of the pre-charge or the value of the ratio can be determined using only the current data with reference to fixed values (Vdd and Vss), so that the previous data as described above to determine the length or ratio There is no need to refer to, thus simplifying the configuration.

9 and 10 are intended to compare the reference value and the current value of the drive signal Vin to define the duration length or ratio of the pre-charge, wherein the positive and negative maximum Possible values are set as reference values. If the former is larger than the latter, pre-charging is performed such that the output voltage Vout is increased as in the period Tp ₁ . If the former is smaller than the latter, the pre-charge reduces the output Vout as in the period Tp ₀ . Thus, such a comparison of the present values can lead to a limitation of the charging mode.

The following is another variant for defining the charging mode based on the comparison.

11 shows a general configuration of a drive circuit according to the modification.

In Fig. 11, comparators 61 and 62 are provided, which receive a drive signal Vin at each first input and receive an output voltage Vout at each of the second inputs. The comparison output of the comparator 61 becomes a control signal for the switch SW-B, and the comparison output of the comparator 62 becomes a control signal for the switch SW-C.

The comparator 61 compares the voltage value of the drive signal Vin with the value of the output value Vout, and outputs a high level to turn on the switch SW-B only when the voltage value of the drive signal Vin is greater than this. Create The comparator 62 compares the voltage value of the drive signal Vin with the value of the output value Vout, and the high level to turn on the switch SW-C only when the voltage value of the drive signal Vin is smaller than this. Generate output

Fig. 12 is a time diagram showing the operation of such a drive circuit, in which the drive signal Vin changes the voltage of v ₀ , v ₁ , v ₂ whenever the horizontal scan period is changed as an example.

First, for the horizontal scanning period from time t1 to time t3, the comparator 61 compares the drive signal Vin with the output voltage Vout, in which the comparison output is the previous period T _00. It is maintained at a low level because the driving signal Vin as well as the output voltage Vout remains at the voltage value v ₀ . During the subsequent period T ₀₁ , however, the comparator 61 produces a high level of comparison output since the drive signal Vin is switched to a voltage value v ₁ higher than the voltage value v ₀ . to be. Accordingly, the high level output of the comparator 61 causes the switch SW-B to be turned on, so that current from the current source Ipcp is provided to the output line 40 through the switch SW-B. Therefore, the value of the output voltage Vout gradually increases as shown in the figure, but when the voltage value v ₁ of the drive signal Vin is not determined to be greater than or equal to the value of the output voltage Vout, the output voltage When the value of Vout is equal to or greater than the value of the drive signal Vin (time t2), the comparator 61 can no longer make a high level comparison output to change the comparison output to a low level. In response, the switch SW-B is turned off and the switches SW-A ₀ , SW-A ₁ are turned on. Therefore, the output voltage Vout no longer increases and the output voltage Vout is driven on the output line 40 based on the operation of the amplifier 21 until the drive signal Vin is updated in the next horizontal scanning period. It is held at the voltage value v1 of the signal Vin.

From the time t3 to the horizontal scanning period, the comparator 62 compares the drive signal Vin with the output voltage Vout and keeps the comparison output at a low level for the previous period T ₁₀ , because This is because the driving signal Vin as well as the output voltage Vout still have the voltage value v ₁ . During the subsequent period T ₁₁ , however, the comparator 62 produces a high level of comparison output because the drive signal Vin is switched to a voltage value v ₂ lower than the voltage value v ₁ . Because. Accordingly, the high level output of comparator 62 causes switch SW-C to be turned on, so that negative current from current source Ipcn is provided through switch SW-C at output line 40. . Thus, the value of the output voltage Vout gradually decreases as shown in the figure, but when the voltage value v ₂ of the drive signal Vin is not determined smaller than the value of the output voltage Vout, that is, the output When the value of the voltage Vout is equal to or smaller than the value of the drive signal Vin (time t4), the comparator 61 can no longer make a high level comparison output to change the comparison output to a low level. . In response, the switch SW-C is turned off and the switches SW-A ₀ , SW-A ₁ are turned on. Therefore, the output voltage Vout is no longer reduced and the output voltage Vout is on the output line 40 based on the operation of the amplifier 21 until the drive signal Vin is updated in the next horizontal scanning period. The voltage value v2 of the driving signal Vin is maintained.

In this way, a comparison of the present value Vin and the previous value Vout of the drive signal is performed, where the former is larger than the latter, on the one hand, the pre-charge output voltage Vout is the period T ₀₁ . Is increased to, or on the other hand, when the former is smaller than the latter, the pre-charge is done so that the output voltage Vout is reduced as in the period T ₁₁ . By doing so, it is possible to define the charging mode such that the pre-duration period does not depend on the same means as the memory 131 described above and the output voltage Vout is necessarily present. This variant also has the advantage that the length of the charge / discharge periods T ₀₁ , T ₁₁ can be automatically obtained each time by comparison of the current and previous values.

Although the variant of FIG. 11 is intended to limit the pre-charge mode of the current source based on the comparison result between the present value and the previous value, the pre-charge mode of the alternative voltage source may be defined based on the comparison result.

FIG. 13 shows a configuration that allows a pair of voltage sources to pre-charge the output line 40. The difference from FIG. 11 is that the switch SW-B switches the connection between the positive constant voltage Vdd and the output line 40 and the switch SW-C has a negative constant voltage Vss and the output line 40. Is to switch the connection between.

Also accordingly, the comparators 61 and 62 perform the charging / discharging operation necessary for the output line 40 for the length of the required duration so that the output value Vout of the drive signal reaches the present value Vin. Turn on the switches (SW-B, SW-C). However, since this charge / discharge operation depends on the constant voltage source, as a result, the time constant of the charge / discharge circuit in which the change of the output voltage Vout shown in the period corresponding to the periods T ₀₁ and T _{11 of} FIG. It follows the curve mainly determined by.

As can be seen from the foregoing, the on-timing of the switches SW-A ₀ and SW-A ₁ is a control signal in response to the off-operation of the switches SW-B and SW-C. It can be implemented by circuitry that causes (C _A ) to work. On the other hand, off-timing of the switches SW-A ₀ and SW-A ₁ may be defined based on, for example, a horizontal synchronization signal of the driving signal Vin.

The above description is based on the assumption that the liquid crystal display panel to be used is arbitrarily selected, and therefore, of course, the present invention provides a so-called low temperature poly-silicon (LTPS) in which the display driving circuit is formed on the same glass substrate as the liquid crystal support substrate. It can be applied to the liquid crystal display panel of the silicon) form.

Although the above-described embodiments are limited to the form for supplying the gray-scale voltage to the liquid crystal display device as the target voltage, it should be noted that the present invention is not necessarily limited to this form.

While some representative embodiments of the invention have been described above, those skilled in the art can modify these embodiments in various modifications as desired without departing from the spirit of the invention as defined in the claims.

The present invention is applicable to a drive circuit for supplying a target voltage to a capacitive load and to an apparatus using such a drive circuit.

Claims (10)

A driving circuit for driving a capacitive load of a display device, Drive signal supply means for supplying a drive signal having a target voltage to be applied; An amplifying step for receiving the drive signal and selectively outputting the drive signal to the capacitive load; And A pair of current sources, comprising, during each of these on-states, a pair of current sources for selectively supplying positive and negative currents to the capacitive load, wherein the drive circuitry is driven by any one of the current sources. A display device in which the pre-operation and amplification stages switched on and then switched off in accordance with the signal repeat a repetitive operation comprising a post-operation switched to a state for outputting a drive signal to the capacitive load after the pre-operation. A driving circuit for driving a capacitive load of. The display device of claim 1, wherein the duration length of the on-period of the associated current source and / or the current supply rate of the associated current source during pre-operation is made to vary according to the value of the drive signal within the repetition period of the repetitive operation. Drive circuitry for driving capacitive loads. The method of claim 1, wherein the duration length of the on-period of the associated current source and / or the current supply rate of the associated current source during pre-operation is determined in the repetition period of the repetitive operation and in the other repetition period before the repetition period. A drive circuit for driving a capacitive load of a display device, the drive circuit being made to be changeable in accordance with the value of the drive signal. A driving circuit for driving a capacitive load of a display device, Drive signal supply means for supplying a drive signal having a target voltage to be applied; An amplifying step for receiving the drive signal and selectively outputting the drive signal to a capacitive load; A pair of power sources for selectively performing charging and discharging to the capacitive load, respectively; And Comparing means having one input for receiving a voltage value of a drive signal and the other input for receiving a voltage value on an output line connected to the capacitive load, The drive circuit performs a post-operation in which a pre-operation and amplification step in which charging or discharging is performed by any one of the power sources and then interrupted is switched to a state for outputting the driving signal to a capacitive load after the pre-operation. Repeat the repetitive actions that you include, The charging and discharging operation performed by the pair of power sources is controlled based on the comparison output of the comparing means during the pre-operation, the driving circuit for driving the capacitive load of the display device. The charging operation according to claim 4, wherein the discharge operation is performed when the comparison output indicates that the voltage value on the output line is greater than the voltage value of the drive signal, and when the comparison output indicates that the voltage value on the output line is smaller than the voltage value of the drive signal. A drive circuit for driving a capacitive load of the display device, in which operation is performed. 6. The drive circuit according to claim 5, wherein one of the charging and discharging operations is continued until the comparative output indicates that the voltage value on the output line reaches the voltage value of the drive signal. 7. The driving circuit according to any one of claims 1 to 6, wherein the target voltage is a gray-scale voltage. The drive circuit according to any one of claims 1 to 7, wherein the capacitive load is a liquid crystal cell. 9. The drive circuit according to any one of claims 1 to 8, wherein said drive signal supply means comprises analog-to-digital conversion means. Display device using the drive signal according to any one of the preceding claims.

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