KR20070022090A - Interrupt scheme for bus controller - Google Patents

Abstract

The host controller, under the control of the processor, transmits data in separate transactions via the bus communication system. Processor interrupt requests are generated upon transaction completion. The host controller is configured to send an interrupt request to a processor when a processor interrupt request is generated upon completion of a transaction from a first group of individual transactions, while a processor interrupt request is generated upon completion of a transaction from a second group of individual transactions. It includes logic to prevent interrupt requests from being sent to the processor. The host controller also sends an interrupt request to the processor only when an interrupt request is generated upon transaction completion, if a processor interrupt request is generated upon completion of a transaction from the third group of individual transactions.

Description

Interrupt technique for bus controllers {INTERRUPT SCHEME FOR BUS CONTROLLER}

The present invention relates to a bus controller, and more particularly, to a device included in an electronic device for controlling data transfer to / from another electronic device by using an external bus.

It is common for an electronic device to provide an interface that enables data transfer using a universal serial bus (USB).

When items of an electronic device are interconnected using a USB system, one item of the device is designated as the USB host, while the other item is designated as the USB device. It is the USB host that initiates and schedules communication via USB. For example, the USB host may be a personal computer (PC) and may be connected to various USB devices such as printers, digital cameras, and personal digital assistants (PDAs).

However, it is also possible to use a USB connection, for example, to connect the camera directly to a printer without requiring a connection via a PC. In order to be able to function as a USB host, in this example, the functionality required for an item of the device, which may be a camera, must be provided, and the present invention is particularly integrated that can be included in an item of the device to provide such functionality. It relates to a device in the form of a circuit. However, it will be understood that an item of device has other functionality, and its USB interconnectivity is only part of that functionality. It is also desirable to be able to include a device in an item of the device to provide the item with the ability to operate as a USB host without requiring items of the device to have a particularly powerful processor.

Thus, it is desirable for the device to be able to operate with minimal possible dependence on the central processing unit (CPU) of the item of apparatus that can be employed. For example, the device preferably operates as a slave to the bus system of the item of the device, while the CPU remains as the bus master. It is also desirable for the device to place the least possible processing burden on the CPU, and in particular, to minimize the number of interrupt requests to the CPU. Furthermore, the device does not depend on the CPU using any particular operating system, so the device can be employed in the widest possible range of items of the device.

According to the present invention, a host controller is provided in which an interrupt request, for example generated as a result of a transaction completion, can be sent to the system CPU in a controlled manner. For example, different interrupt requests may be given at different priorities, or interrupt requests may be sent together to the CPU to reduce confusion to the CPU.

1 is a schematic block diagram of an electronic device item employing a host controller in accordance with the present invention.

2 is a schematic block diagram of a host controller according to the present invention;

3 illustrates the structure of software in the host controller of FIG.

4 illustrates a logic circuit that can be used to control how an interrupt request is sent to the CPU of an electronic device item.

1 is a schematic block diagram of a relevant portion of an electronic device item 10 operating as a USB host. The present invention is particularly applicable to devices in which the functional limitations of microprocessors and system memory, such as cameras, set-top boxes, mobile phones, or PDAs, are more relevant than personal computers (PCs). However, the present invention is applicable to any device that can operate as a USB host.

It is apparent that device 10 will have many features, and many of these features are not shown in FIG. 1 because they are not relevant to the understanding of the present invention.

Device 10 has a host microprocessor (CPU) 20 that includes a processor core. The CPU 20 is connected to the system memory 30 by the peripheral bus 32.

The host controller 40 is also connected to the host microprocessor 20 and the system memory 30 by a peripheral bus or memory bus 32. The host controller 40 has an interface for the USB bus 42 that can be connected to a number of USB devices. In the illustrated embodiment, the host controller 40 is a USB controller and the features of the host controller are not described herein because they are described in detail in the USB 2.0 specification.

As is conventional, the host controller 40 is adapted to retrieve the data provided by the processor 20 in an appropriate format and to transmit the data over the bus interface. In USB communication, there are two categories of data transfer: asynchronous transfer and periodic transfer. Control and bulk data are transmitted using asynchronous transmissions, while isochronous and interrupt data are transmitted via periodic transmissions. The qTD (Queue Transaction Descriptor) data structure is used for asynchronous transmission and the iTD (Isochronous Transaction Descriptor) data structure is used for periodic transmission.

The processor 20 prepares data in an appropriate structure, stores it in the system memory 30, and then the host controller 40 needs to retrieve data from the system memory 30.

2 shows a more detailed structure of the embedded USB host controller 40.

As mentioned above, the host controller 40 has a connection to a memory bus 32 connected to an interface 44 that includes a memory management unit, a slave DMA controller, an interrupt control unit, and a hardware configuration register. The interface 44 also has a connection 46 for control and interrupt signals and a register 48 that supports the operational registers and RAM structures of the host controller 40.

The interface 44 is connected to the on-chip RAM 50 of the host controller, which is a dual port RAM that allows data to be simultaneously written / read to / from memory in the preferred embodiment. The memory 50 is connected to a host controller logic unit 52 that also includes an interface for the USB bus 42. The control signal may be sent from the register 48 to the logic unit 52 on the internal bus 54.

3 is a schematic diagram showing a part of the software operating on the host controller 40 to explain a method of operating the device according to the present invention.

The host controller 40 executes the USB driver software 80 and the USB Enhanced Host Controller Interface (EHCI) software 82, all of which have generally existed in the past.

The host controller 40 also executes the USB EHCI interface software 84, which provides a transfer-based transfer descriptor for every endpoint to which data is to be transferred.

The EHCI interface software 84 is written to use parameters generated by the EHCI host stack 82 for existing periodic and synchronous headers, all of which are entirely different types of USB transfers, particularly high speed isochronous, bulk, interrupt and control and Can be used for high speed USB transfers such as start / stop split transactions.

The host microprocessor 20 transfers through the peripheral bus 32 to the RAM 50 of the host controller 40 via the peripheral bus 32 without requiring the host controller 40 to master the bus 32. Record it. In other words, the host controller 40 only acts as a slave. The transfer-based transfer descriptor may then be memory mapped to the RAM 50 of the host controller 40.

Advantageously, the built-in memory of the host controller 940 is mapped to the host microprocessor 20 while facilitating the transaction being scheduled from the host microprocessor 20.

The use of dual port RAM 50 means that the transfer-based transfer descriptor is executed by the host controller 40 and the host microprocessor 20 can write data to another block space.

As conventional, data transactions can include isochronous transfers, interrupt transfers, and bulk and control transfers. As is still another conventional case, as defined by the packet transfer descriptor, when the transfer is complete, the host controller generates an interrupt request for transfer to the CPU 20. However, the CPU does not know when each transaction will complete and when many devices are connected to the system and there will be many interrupt requests.

The present invention allows the CPU to, for example, prioritize the transfer descriptor for a particular endpoint so that those interrupt requests are handled immediately. In other cases, the CPU can handle other interrupt requests from the group of transfer descriptors only when they are all completed. The transfer descriptor and payload can be updated on-the-fly without stopping any other USB transactions or corrupting RAM data. It is also mentioned that interrupt requests can occur due to timeouts, especially in the case of bulk and isochronous transactions.

4 illustrates a logical structure applied to an interrupt request generated when a transaction is completed. This logical structure can be made by logic gates in hardware or by software.

A packet transfer descriptor (PTD) Done map has 32 bits. That is, in this example, the logic can handle interrupt requests arriving up to 32 PTDs to indicate that the corresponding transaction is complete. When the transaction completes, the relevant bit of the PTD Done map is set high. The bits of the PTD Done map are applied to the series of 32 first AND gates 210 and the series of 32 second AND gates 220, and inverted to the series of 32 third AND gates 230.

OR masks also have 32 bits and are commonly used to prioritize specific packet transmission descriptors. To give a particular priority to a particular packet transmission descriptor, the corresponding bit of the OR mask is set high. The bits of the OR mask are applied to the second input of the series of 32 first AND gates 210.

In addition, the AND mask also has 32 bits and is applied to introduce a relationship between specific packet transmission descriptors. The bits of the AND mask are applied to the second input of the series of 32 second AND gates 220 and to the second input of the series of 32 third AND gates 230.

Thus, when an interrupt request is generated from a packet transfer descriptor and the corresponding bit of the OR mask is set high, the corresponding AND gate 210 generates a logic "1" as an output, and the OR gates 215, 240 are OR A logic "1" appears at the output of the gate 240, and an interrupt request is sent to the CPU 20.

When an interrupt request is generated from the packet forwarding descriptor and the corresponding bit of the OR mask is set low, the AND mask becomes relevant. The output of AND gate 220 is applied to each input of OR gate 225. The output of AND gate 230 is applied to each input of OR gate 235. The output of the OR gate 225 is applied to the first input of the AND gate 245, and the output of the OR gate 235 is applied inverted to the second input of the AND gate 245. The output of AND gate 245 is applied to OR gate 240.

The effect of this logic is that an interrupt request is sent to the CPU 20 only when logic " 1 " appears at the output of the OR gate 240 and an interrupt request is generated from all packet transfer descriptors, for which The bit is set high. For example, if bits 2, 4, and 10 are set in the AND mask register, an interrupt request is sent to the CPU only if bits 2, 4, and 10 of the PTD Done map are set high. If only one of bits 2, 4, or 10 of the PTD Done map is set high, it will not send an interrupt to the CPU.

The system software determines which transfer descriptors are given priority regarding the ability to send interrupt requests to the CPU, which waits for other transactions to complete, and ORs to send the interrupt requests together to the CPU. The mask bit and the AND mask bit can be changed as required.

In practice, this allows the CPU 20 to change the frequency at which to receive the interrupt request.

Claims (7)

Under the control of a processor, a host controller transmitting data via a bus communication system, the data being transmitted in a plurality of individual transactions and upon completion of the transaction a processor interrupt request is generated; The host controller causes an interrupt request to be sent to the processor when a processor interrupt request is generated upon completion of a transaction from the first group of the plurality of individual transactions, while the transaction from the second group of the plurality of individual transactions is Includes logic to prevent an interrupt request from being sent to the processor when the processor interrupt request is generated upon completion Host controller. The method of claim 1, The host controller is only configured when an interrupt request is generated upon completion of a transaction from all of the third group of the plurality of individual transactions, if a processor interrupt request is generated upon completion of a transaction from the third group of the plurality of individual transactions. And logic to cause an interrupt request to be sent to the processor. The method according to claim 1 or 2, A first interface for connection to a memory bus interconnecting the processor and system memory, and And a second interface for connecting to the bus communication system. As a bus communication device, Processor, System memory, A host controller, and A memory bus interconnecting said processor, said system memory and said host controller, The host controller is configured to transmit data through a bus communication system under control of the processor, the data is transmitted in a plurality of individual transactions, a processor interrupt request is generated upon completion of the transaction, The host controller is further configured to transmit a interrupt from the second group of the plurality of individual transactions, while an interrupt request is sent to the processor when a processor interrupt request is generated upon completion of the transaction from the first group of the plurality of individual transactions. And logic to prevent an interrupt request from being sent to the processor when a processor interrupt request is generated upon completion of the transaction. Bus communication device. The method of claim 4, wherein The host controller is only configured when an interrupt request is generated upon completion of a transaction from all of the third group of the plurality of individual transactions, if a processor interrupt request is generated upon completion of a transaction from the third group of the plurality of individual transactions. And logic further including logic to cause an interrupt request to be sent to the processor. A method of operation of a host controller that transmits data through a bus communication system, under the control of a processor, the data being transmitted in a plurality of individual transactions, upon completion of the transaction a processor interrupt request is generated; The method includes sending an interrupt request to a processor when a processor interrupt request is generated upon completion of a transaction from the first group of the plurality of individual transactions, In contrast, the method includes not sending an interrupt request to the processor when a processor interrupt request is generated upon completion of a transaction from the second group of the plurality of individual transactions. The method of claim 6, The method further comprises: when a processor interrupt request is generated upon completion of a transaction from a third group of the plurality of individual transactions, only when the interrupt request is generated upon completion of a transaction from all of the third group of the plurality of individual transactions. Sending an interrupt request to the processor.

Images