JP2011198314A - Data receiver and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data receiving apparatus including a control device that recognizes reception of packet data without polling.SOLUTION: A target device 30 includes a plurality of buffers 321, 322, 323 for storing packet data transmitted from a host device 10 through a data communication channel. The data receiving apparatus includes: a USB target controller 33 for receiving packet data transmitted from the host device 10; the buffer 321 which stores packet data first among the plurality of buffers when transmission of packet data from the host device 10 is started, in which the maximum size of packet data transferred from the host device 10 is an effective memory size to store the packet data; and a control part 36 for informing a CPU 31 for controlling the target device 30 about reception of the packet data when the packet data is stored in the buffer 321 and the effective memory size of the buffer 321 is satisfied.

Description

  The present invention relates to a data receiving apparatus and a program.

  Communication between apparatuses is generally performed based on some standard. For example, in serial communication, IEEE (Institute of Electrical and Electronic Engineers) 1394 and USB (Universal Serial Bus) are widely used. IEEE 1394 is a standard in which transfer rates of 100 Mbps, 200 Mbps, and 400 Mbps are defined. In addition, USB is defined by FS (full speed mode) having a transfer speed of up to 12 Mbps adopted in USB 1.1, HS (high speed) mode having a transfer speed of up to 480 Mbps added by USB 2.0, and the like. Standard.

  Patent Document 1 is a data transfer method of an image forming apparatus, in which a first monitoring stage for monitoring whether a packet is stored in a memory every first monitoring time, and as a result of monitoring, a packet is stored in a memory. If this is the case, a second monitoring stage for monitoring the storage of the packet in the memory every second monitoring time shorter than the first monitoring time is provided.

Japanese Patent Publication No. 3857598

  An object of the present invention is to provide a data receiving apparatus and a program that allow a control apparatus to recognize reception of packet data without using polling.

  In order to achieve such an object, the invention described in claim 1 is a data receiving device comprising a plurality of memories for storing packet data transmitted from an external device via a data communication path, wherein the data communication path is provided via the data communication path. Receiving means for receiving packet data transmitted from the external device, and the maximum transfer size of the packet data transferred from the external device is an effective memory size capable of storing packet data, and the packet data from the external device When the transmission of the first memory, the first memory for storing the packet data first in the plurality of memories, and when the packet data is stored in the first memory and the effective memory size of the first memory is satisfied, Notification means for notifying reception of packet data to a control device that controls the data receiving device.

  According to a second aspect of the invention, in the first aspect of the invention, the plurality of memories follow the first memory and packet data stored in the first memory, which is sequentially transmitted from the external device. A plurality of subsequent memories that sequentially store packet data and have an effective memory size capable of storing packet data that is an integer multiple of the maximum transfer size, and storage of packet data is started in any of the plurality of subsequent memories Wait time setting means for setting a wait time until packet data satisfying the effective memory size of the memory is stored, and the notification means is stored in any one of the plurality of subsequent memories. Packet data that satisfies the effective memory size of the memory even after the waiting time has elapsed since the start of packet data storage is stored in the memory. If not stored, the control device may notify the reception completion of the packet data from the external device.

  The invention according to claim 3 is the invention according to claim 1, wherein the subsequent memory includes a second memory and a third memory, and an effective memory size capable of storing packet data of the second memory is the first memory. A memory size obtained by subtracting the effective memory size of the first memory from the effective memory size of 3 memories may be provided.

  The invention according to claim 4 is the invention according to claim 3, further comprising effective memory size changing means for changing an effective memory size of the first memory and the second memory, wherein the effective memory size changing means is Packet data satisfying the effective memory size of each memory is stored in each of the first memory and the second memory, and after the stored packet data is transferred to the processing unit on the subsequent stage by the control device, The effective memory size of the first memory and the second memory is changed to the effective memory size of the third memory, and packet data satisfying the effective memory size of the third memory is stored in the third memory. Later, subsequent packet data may be sequentially stored in the first memory and the second memory.

  The invention according to claim 5 is a data reception program of a data reception device including a plurality of memories for storing packet data transmitted from an external device via a data communication path, and the computer receives the data communication path via the data communication path. Receiving the packet data transmitted from the external device by the receiving means, and when transmission of the packet data from the external device is started, the maximum transfer size of the packet data transferred from the external device is set to the packet A step of first storing packet data in the plurality of memories in a first memory having an effective memory size capable of storing data; the packet data being stored in the first memory; and an effective memory size of the first memory being When the condition is satisfied, the packet data reception is transmitted to the control device that controls the data reception device. It is characterized by and a step of.

  According to the first aspect of the present invention, it is possible to make the control device recognize the reception of packet data without using polling.

  According to the second aspect of the present invention, it is possible to determine completion of reception of packet data and notify the control device of completion of reception of packet data.

  According to the third aspect of the present invention, the data size of the packet data sent to the processing unit on the subsequent stage can be matched with the effective memory size of the third memory.

  According to the fourth aspect of the present invention, after the packet data is once stored in the first memory and the second memory, the effective memory sizes of the first memory and the second memory are matched with the effective memory size of the third memory. be able to.

  According to the fifth aspect of the present invention, it is possible to make the control device recognize the reception of the packet data without using polling.

It is a figure which shows the hardware structural example of a USB communication system. It is a figure which shows the hierarchy of the software and hardware of a USB communication system. It is a figure for demonstrating the packet transmitted / received in bulk-out transfer. It is a figure for demonstrating the packet transmitted / received in bulk-out transfer. It is a figure for demonstrating the data transfer inside a target device. It is a figure which shows the flow of the process regarding the buffer of a kernel area | region. It is a figure which shows the structure of IO request structure. It is a figure for demonstrating an IO request and IO request waiting queue. It is a figure for demonstrating an IO request and an IO request completion queue. It is a flowchart which shows the buffer setting process of a kernel area | region.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

  First, the configuration of an embodiment in which the present invention is applied to a USB communication system will be described with reference to FIG. The USB communication system has a configuration in which a USB host device (for example, a personal computer) 10 and a target device (for example, an image forming apparatus) 30 are connected by a USB cable 20.

  The host device 10 is a general-purpose computer. For example, a notebook PC carried by the owner can be cited as an example. A CPU (central processing unit) 11, a memory 12, and a USB host controller 13 are connected to the host device 10 via a bus as an internal communication path.

  The CPU 11 is a device that executes computation and control according to a program (software) stored in the memory 12, and controls the operation of each device and controls communication between devices or externally through a bus. . The memory 12 is a storage device and stores an OS (operation system), a device driver, an application program, various data, and the like. In the memory 12, a kernel area 12A used by the OS and device driver and a user area 12B used by the application program are constructed.

  The USB host controller 13 is a communication control device that controls USB communication and enables transmission and reception of data with the target device 30 through the USB cable 20. The USB host controller 13 includes a buffer memory 14, a USB interface (hereinafter abbreviated as USB I / F) 15, and a control unit 16.

  The buffer memory 14 is a first-in first-out storage device configured using a semiconductor memory, and temporarily stores data to be input or output. The USB I / F 15 is an interface for connecting the USB cable 20. The control unit 16 is a device that has an arithmetic processing function and controls the USB host controller 13. The control unit 16 controls the buffer memory 14 and the USB I / F 15 under the instruction of the CPU 14. This control unit 16 is provided with a DMA (Direct Memory Access) 17. The DMA 17 is a device that controls data communication between the buffer memory 14 and the memory 12, and can directly control communication between the buffer memory 14 and the memory 12 without the CPU 11.

  The target device 30 has a configuration in which a CPU 31, a memory 32, a USB target controller 33, and the like are connected to an internal bus. The CPU 31 and the memory 32 are configured in substantially the same manner as the PC 20, and the same is true in that the memory 32 is provided with a kernel area 32A and a user area 32B.

  The USB target controller 33 is configured in substantially the same manner as the USB host controller 13, but differs in that it is used as a target device in USB communication. That is, in the USB target controller 33, the USB I / F 35, the control unit 36, and the like are constructed as receiving means.

  Next, USB communication will be described with reference to FIG. FIG. 2 is a diagram illustrating functional units of the host device 10 and the target device 30 that are involved in communication in USB communication, divided into software and hardware. In FIG. 2, the configurations of the host device 10 and the target device 30 are divided into three layers of an application level, a device driver level, and a hardware level.

  In the host device 10, the application level is configured by the application 101 program. The device driver level includes a class driver 102 as a general-purpose host driver, an API (Application Program Interface) 103, and a host control / bus driver 104. The API 103 is software that connects the class driver 102 and the host control / bus driver 104. The host control driver is a driver that abstracts the USB host controller 13, and the bus driver is a driver that implements a USB-specific protocol. The hardware level is configured by the USB host controller 13 described in FIG.

The target device 30 is configured by a program of the application 108 at the application level. The device driver level includes an H / W (hardware) independent unit 107, an API 106, and an H / W dependent unit 105. The hardware level is configured by the USB target controller 33 described with reference to FIG.
Note that the reason why the H / W-independent part 107 and the H / W-dependent part 105 are separated at the device driver level is because the influence when the USB target controller 33 is replaced with another is reduced. Of course, it is also possible to integrate the two. The API 106 is software that connects the H / W-independent unit 107 and the H / W-dependent unit 105.

  In USB, in addition to default type control transfer, bulk transfer for transferring large-capacity data, interrupt transfer for transferring small-capacity data periodically, isochronous transfer with compensated transfer data amount within a certain time Is stipulated. Hereinafter, an example in which bulk-out transfer in which bulk transfer is performed from the host to the target is performed in the HS mode will be described.

  When the application 101 of the host apparatus 10 performs bulk-out transmission of data to be communicated to the application 108 of the target device 30, first, the data is transferred from the application 101 to the class driver (printer class or the like) 102. Subsequently, the class driver 102 transfers data to the host control / bus driver 104 via the API 103. Then, the host control / bus driver 104 divides the data into 512-byte packets (this is a data element as a data transfer unit) based on the USB 2.0 standard, and uses the USB host controller 13 to output OUT. Send as a transaction.

  Each packet data to be transmitted reaches the USB target controller 33 of the target device 30 via the USB cable 20. The USB target controller 33 receives the packet data and temporarily stores it in the buffer memory 34. Specifically, the buffer memory 34 is configured by a FIFO (a first-in first-out storage unit) capable of storing one packet data (maximum 512 bytes in USB 2.0), and the packet data is stored therein. A plurality of logical communication paths (pipes) can be set between one target device 30 and the host apparatus 10. The end of each pipe on the target device side is called an end point, and usually a FIFO capable of physically storing one packet data is provided. The number of FIFOs may be fixed or changeable. In general, the larger the number of FIFOs, the higher the room for speeding up data transfer.

  Here, FIG. 3 shows a format of a packet exchanged between the USB host controller 13 and the USB target controller 33 in the bulk-out transfer transaction. The USB host controller 13 first transmits an OUT token packet 120 to notify the start of bulk-out transfer. As a result, the USB target controller 33 recognizes that the transfer to be performed from now on is bulk-out transfer, and prepares a FIFO for storing packet data at the bulk-out endpoint. Subsequently, the USB host controller 13 transmits packet data 121 called DATA0. The USB target controller 33 receives the DATA0 packet data and stores it in the FIFO provided at the end point of this pipe. At this point, the other of the two FIFOs is usable. Therefore, the USB target controller 33 transmits an ACK handshake 124 indicating that the next packet data 121 can be received to the USB host controller 13. When the USB host controller 13 receives the ACK handshake 124, it continuously transmits the OUT token packet 120 and the packet data 121 of DATA1. Then, the USB target controller 33 receives this packet data 121 and stores it in the other FIFO.

  At this stage, if the FIFO that previously stored the DATA0 packet data 121 is empty, that is, if data transfer has already been performed in the subsequent apparatus and a new packet data path can be stored. The USB target controller 33 transmits an ACK handshake 124 indicating that the next packet data 121 can be received. On the other hand, if the FIFO storing the packet data 121 of DATA0 is in use, that is, if no data transfer is performed to the subsequent apparatus, the USB target controller 33 cannot receive the next packet data. Is transmitted to the USB host controller 13.

  FIG. 4 is a diagram showing packet exchange when the USB host controller 13 receives the NYET handshake 123. In this case, the USB host controller 13 issues a PING token packet 127 instead of the OUT token packet 120. Then, the USB target controller 33 transmits the NAK handshake 125 to the USB host controller 13 when the FIFO holding the DATA0 packet data 121 is not usable, and the ACK handshake 124 when it is usable. When receiving the ACK handshake 124, the USB host controller 13 issues the OUT token packet 120 shown in FIG. 3 in order to resume the OUT transaction. On the other hand, when the USB host controller 13 receives the NAK handshake 125, it issues the PING token packet 127 again. The issuing of the PING token packet 127 is continued until the ACK handshake 124 is received from the USB target controller 33. The USB target controller 33 returns a STALL handshake 126 when it is in an inoperable state. Each handshake described here is a packet for performing connection-type communication (communication interactively) between the target device and the host.

  Next, the flow of packet data in the target device 30 after receiving the packet data will be described with reference to FIG. FIG. 5 is a diagram showing a flow of processing of packet data in the target device 30 when data transfer is performed from the host apparatus 10 to the target device 30 by bulk-out transfer in HS mode (packet data is 512 bytes). It is.

  The packet data received by the USB I / F 35 of the USB target controller 33 is temporarily stored in one of the FIFOs 341 and 342 set as the end point for each packet data. The FIFOs 341 and 342 are areas secured in the buffer memory 34 in the USB target controller 33.

  The packet data stored in the FIFOs 341 and 342 is transferred to the kernel area 32A in the memory 32 by the DMA 37 in the USB target controller 33. In the kernel area 32A, three buffers 321, 322, and 323 are secured for temporarily storing packet data transferred from the FIFOs 341 and 342.

  Buffers 321, 322, and 323 are prepared in the kernel area 32 </ b> A in response to a request from the application 108. Among these, the buffers 321 and 322 can change the size of an available effective area that can store a packet (hereinafter referred to as an effective memory size). For example, if the size of the buffer 321 prepared in the kernel area 32A (hereinafter referred to as the original size) is 4 Kbytes, the buffer 321 uses 512 bytes of the effective memory size. The effective memory size of 512 bytes of the buffer 321 is assumed to be USB 2.0 in the present embodiment, and is therefore equal to the maximum size of one packet data to be transferred. The effective memory size of the buffer 321 is changed according to the maximum size of one packet data to be transferred.

The effective memory size of the buffer 322 is an integral multiple of the maximum size of one packet data (that is, 512 bytes × integer). In this embodiment, the size of the effective area of the buffer 322 is about 3.5 Kbytes obtained by subtracting 512 bytes, which is the effective memory size of the buffer 321 (or the maximum size of one packet data), from the original size of 4 Kbytes.
The effective memory size of the buffer 323 is 4 Kbytes of the original size prepared in the kernel area 32A.

  The packet data stored in the kernel area 32A is transferred to the buffer 325 secured in the user area 32B. The buffer 325 has a size capable of storing the entire data transmitted from the host device 10, and the packet data is integrated here. The restored data is managed and used by the application 108. The packet data is transferred from the kernel area 32A to the user area 32B by the CPU 31.

  FIG. 5 shows an example in which three buffers 321, 322, and 323 are provided in the kernel area 32A. However, the number and size (original size and effective memory size) of buffers provided in the kernel area 32A can be dynamically changed.

FIG. 6 is a diagram for explaining the flow of internal processing in the target device 30 in association with the software and hardware structures shown in FIG.
The H / W-independent unit 107 manages routines for general system calls such as ioctl () and read (). When these routines are called from the application 108, the H / W-independent unit 107 transmits the H / W through the API 106. Commands the W-dependent unit 105 for the corresponding processing. Here, ioctl () is a routine that supports a function for setting the number and size of buffers provided in the kernel area 32 </ b> A, and read () is a routine for reading data.

  First, the application 108 sets a function value and an attribute value of the function value in an argument of ioctl (), and sets a timeout time, the number of buffers and the size (original size and effective memory size). Then, ioctl () generates the same number of IO request structures (hereinafter sometimes simply referred to as IO requests) as the number of set buffers (IO requests a, b, and c shown in FIG. 6). . It is assumed that a buffer 321 having an effective memory size of 512 bytes is set in the kernel area 32A shown in FIG. 5 by the IO request a shown in FIG. Similarly, it is assumed that a buffer 322 having an effective memory size of about 3.5 Kbytes is set in the kernel area 32A shown in FIG. 5 by the IO request b, and the kernel area 32A shown in FIG. Assume that a buffer 323 having an effective memory size of 4 Kbytes is set. The timeout time will be described later.

  FIG. 7 is a diagram for explaining the IO request structure 210. The IO request structure 210 is a structure set for each buffer secured in the kernel area 32A, and includes a pointer 212 to the buffer, an original size 214 of the buffer, an effective size 216 of the buffer, and a pointer 218 to the callback routine. , Data size 220 and list pointer 222 fields. The pointer 212 to the buffer represents the address of the buffer 321 (322, 323) secured in the kernel area 32A by the IO request structure 210. The buffer original size 214 represents the original size of the buffer 321 (322, 323) secured in the kernel area 32A by the IO request structure 210. The original sizes of the buffers 321, 322, and 323 are all set to 4 Kbytes. The buffer effective size 216 represents the effective memory size that is actually used (packet data is stored) among the original sizes of the buffers 321 (322, 323) prepared in the kernel area 32A. Further, the pointer 218 to the callback routine is an address set for receiving a notification from the H / W dependency unit 105 that the IO request has been completed. The data size 220 represents the size of data actually stored in the buffer, and the list pointer 222 is set to control the arrangement of the plurality of IO request structures 210.

  In the H / W-independent unit 107, ioctl () sets a value in each field of the IO request structure 210. At this time, the list pointer 222 is initialized with NULL, and the data size 220 is initialized with 0. Further, based on an instruction from ioctl (), the request waiting queue managed by the H / W dependent unit 105 is initialized with NULL.

  When receiving data from the host device 10, the application 108 calls read () provided by the H / W independent unit 107 as shown in FIG. 6. Then, the H / W independent unit 107 sequentially issues IO requests for the number of buffers to the H / W dependent unit 105 through the API 106. The H / W dependency unit 105 manages the IO request waiting queue in order to sequentially process the issued IO requests, and sequentially connects the IO request structures 210 corresponding to the issued IO requests to the IO request waiting queue. Process. FIG. 8 is a diagram for explaining this state. Three issued IO requests 240, 242, and 244 (the IO request 240 corresponds to the IO request a shown in FIG. 6 and the IO request 242 is shown in FIG. The IO request b corresponds to the IO request b, and the IO request 244 corresponds to the IO request c shown in FIG. 6).

  The DMA 37 transfers the packet data stored in the FIFO 341 or the FIFO 342 provided in the buffer memory 34 to the buffer 321 prepared in the kernel area 32A by the first IO request in the IO request waiting queue 246. When the transfer to the buffer 321 is completed, an interrupt is notified from the control unit 36 of the USB target controller 33 to the CPU 31, and the CPU 31 determines the interrupt handler (H / W dependent unit) of the H / W dependent unit 105 from the contents of the interrupt. (Routine included in 105) notifies that the packet data has been stored. When the H / W dependency unit 105 is an interrupt handler and receives a notification from the control unit 36, the H / W dependency unit 105 connects the top IO request of the IO request waiting queue 246 to the end of the IO request completion queue 250. The H / W dependency unit 105 processes the IO requests connected to the IO request completion queue 250 in the order of connection to the IO request completion queue 250. The H / W dependent unit 105 calls the callback routine of the H / W non-dependent unit 107 in accordance with the pointer 218 to the callback routine set in the IO request structure connected to the IO request completion queue 250.

  Subsequently, the callback routine of the called H / W non-dependent unit 107 checks the IO request completion queue 250 shown in FIG. Then, the head IO request of the IO request completion queue 250 is removed from the queue, and the buffer set in the pointer 212 to the buffer of the head IO request (for example, the buffer 321 if the IO request a, if the IO request b) If the buffer 322 is an IO request c, the packet data of the size set in the data size 220 of the IO request is copied from the buffer 323) to the buffer 325 of the user area 32B. The callback routine of the H / W independent unit 107 checks whether the size of the copied packet data is equal to the effective memory size of the buffer 321 (322, 323). First, when the effective memory size of the copy source buffer 321 (322, 323) does not match the size of the packet data copied to the buffer 325 of the user area 32B (that is, the size of the copied packet data). If it is not an integer multiple of 512 bytes (hereinafter, this case is referred to as a short packet), the callback routine of the H / W independent unit 107 determines that there is no longer packet data transmitted from the host device 10, and The IO request is canceled and the unnecessary IO request connected to the IO request waiting queue 246 is removed, and even when the packet data received from the host device 10 is a null packet, the callback routine Packet data sent from the host device 10 already exists It is determined that there is no, do the cancellation processing of the IO request, remove the unnecessary IO requests that are connected to the IO request queue 246.

  On the other hand, if the size of the copied packet data is equal to the effective memory size of the buffer 321 (322, 323), the callback routine determines that the packet data from the host device 10 still exists and the used IO The request is used to reissue the IO request and check the IO request completion queue 250 before entering the wait state again. Thereafter, similar processing is repeated.

Here, the timeout time will be described with reference to FIG.
The timeout time is the time from when the H / W independent unit 107 issues an IO request until the callback routine of the H / W independent unit 107 is called. However, the timing for starting the timing of the timeout time does not include the timing for issuing the IO requests a, b, and c. That is, the issuing timing of the IO requests d, e, f,... Following the IO requests a, b, c is the timing start timing of the timeout time. The reason why the IO request a is not targeted is that the timeout period of the IO request a issued first is set to infinite time. The time-out time of the IO request a is set to infinite time because the target device 30 does not know when the host device 10 starts transmitting packet data. This is because the IO requests b and c are issued together with the IO request a and are connected to the IO request waiting queue 246 together with the IO request a. Note that the IO request a is not included in the end of the time-out time measurement because the IO request a sets the timeout time to an infinite time.
The timeout time will be described in more detail with reference to the IO request shown in FIG. When packet data corresponding to the effective memory size of the buffer 321 is stored in the buffer 321, the IO request a is connected to the IO request completion queue 250, and the next IO request b, which is the IO request structure, is stored in the IO request waiting queue 246. Connected to the top. When the callback routine of the H / W non-dependent unit 107 is called by the H / W dependent unit 105, the H / W non-dependent unit 107 uses the IO request structure that has been used. Reissue the request. In order to distinguish this IO request from the IO request a, it is called an IO request d for convenience. The H / W non-dependent unit 107 starts measuring the timeout time when the IO request d is issued. The buffer 322 stores packet data corresponding to the effective memory size of the buffer 322, the IO request b is connected to the IO request completion queue 250, and the H / W dependent unit 105 calls back the H / W independent unit 107 callback. The time until the routine is called (see FIG. 6) is the timeout time. When the timeout time is exceeded, the H / W dependent unit 105 does not call the callback routine even if the timeout time elapses, so the H / W independent unit 107 is transmitted from the host device 10. It is determined that the packet data no longer exists, the IO request is canceled, and unnecessary IO requests connected to the IO request waiting queue 246 are removed.
Note that the timeout time can be said to be the time it takes for the buffers 322, 323, and 321 to store packet data of the effective memory size of each buffer. For example, storage of packet data in the buffer 323 is completed and the callback routine is called, but storage of packet data in the buffer 321 that is the next buffer is not completed and the callback routine is not called. In this case, the H / W independent unit 107 determines that there is no more packet data transmitted from the host device 10.

Next, the effective memory size of the buffers 321 and 322 will be described.
In the initial state, the effective memory size of the buffer 321 of the kernel area 32A that initially stores packet data transmitted from the host apparatus 10 is set to 512 bytes. For example, if the effective memory size of the buffer that initially stores packet data is 4 Kbytes, a packet that is smaller than 4 Kbytes and that is an integer multiple of 512 bytes, which is the maximum transfer size, is received and stored in the buffer 321. Unless the packet data is received or the null packet is received, the target device 30 waits for reception of the packet data indefinitely. However, by setting the effective memory size of the buffer 321 to 512 bytes which is the maximum transfer size of USB 2.0, the target device 30 receives the packet data, and the received packet data is stored in the buffer 321. Then, the notification is sent to the H / W dependent unit 105 via the CPU 31, and the reception of the packet data can be recognized. Even if the CPU 31 does not monitor the reception state of the packet data by polling every predetermined time, when the 512-byte packet data is stored in the buffer 321, there is a notification from the control unit 36 of the USB target controller 33. Reception of packet data from the host device 10 can be recognized.

The effective memory size of the buffer 322 that stores packet data next to the buffer 321 is about 3.5 Kbytes obtained by subtracting 512 bytes from 4 Kbytes that is the original size of the buffer 321 (322, 323). For this reason, the data size of the packet data stored in the buffer 321 and the buffer 322 is 4 Kbytes in total. The effective memory size of the buffer 323 that stores the packet data next to the buffer 322 is also 4 Kbytes of the original size. Furthermore, the buffer 321 and the buffer 322 once store the packet data of the effective memory size, and the packet data After being read out to the user area 32B, the effective memory sizes of the buffer 321 and the buffer 322 are set to 4 Kbytes of the original size, respectively.
The size of the buffer 325 in the user area 32B is set to an integer multiple of the original size of the buffers 321, 322, and 323. The sum of the packet data stored in the buffer 321 and the buffer 322 is 4 Kbytes only at the start of reception of the packet data, and thereafter, the size of the packet data sent from the buffers 321, 322, and 323 to the buffer 325 is set to 4 Kbytes. Keep it in place. By processing in this way, when packet data is transferred from any of the buffers 321, 322, and 323 to the buffer 325, the packet data is left in the transferring buffer 321 (322 and 323). In this state, the buffer 325 does not become full.

The procedure of the buffer setting process for the kernel area 32A will be described with reference to FIG. 6 along the flowchart shown in FIG.
First, the application 108 calls ioctl () provided by the H / W-independent unit 107 of the device driver, and sets a timeout time in ioctl () (step S1). In the timeout period, packet data corresponding to the effective memory size is stored in the second and subsequent buffers in which packet data is stored (that is, buffer 322, buffer 323, buffer 321, buffer 322,...). It takes time to complete. More specifically, the time-out time is determined by the H / W-independent unit 107 after the IO requests d, e, f,... Are issued, and the IO requests b, c, d,. 250 is a time until the callback routine of the H / W independent unit 107 is called (see FIG. 6). Note that the buffer 321 that stores packet data first waits indefinitely for reception of packet data from the host device 10 without a timeout time.

  Next, the application 108 calls Read () provided by the H / W independent unit 107 of the device driver. When Read () is called by the application 108, the H / W non-dependent unit 107 issues the IO requests a, b, and c shown in FIG. 6 to the H / W dependent unit 105 of the device driver (step S2). ). When the I / O requests a, b, and c are issued to the H / W dependency unit 105, the H / W dependency unit 105 prepares buffers 321, 322, and 323 in the kernel area 32A. That is, the buffer 321 is prepared in the kernel area 32A by the IO request a, the buffer 322 is prepared in the kernel area 32A by the IO request b, and the buffer 323 is prepared in the kernel area 32A by the IO request c. IO requests a, b, and c are registered in the IO request waiting queue 246, respectively. Since the packet data sent from the host device 10 is stored in the order of the buffer 321, the buffer 322, and the buffer 323, the IO request waiting queue 246 is also in the order of the IO request a, the IO request b, and the IO request c. be registered. The buffer 321 that first stores the packet data waits indefinitely for reception of packet data from the host device 10 without a timeout time (step S3).

  When the host device 10 starts the bulk-out transfer and the first packet data is stored in the buffer 321, the packet data is transferred from the control unit 36 of the USB target controller 33 to the interrupt handler of the H / W dependent unit 105 via the CPU 31. The storage is notified. When receiving the notification from the control unit 36 by the interrupt handler, the H / W dependency unit 105 moves the IO request a from the IO request waiting queue 246 to the IO request completion queue 250. Further, the H / W dependent unit 105 calls the callback routine of the H / W independent unit 107 set by the “pointer to the callback routine” 218 of the IO request structure shown in FIG. When the H / W dependent unit 105 calls the callback routine, the CPU 31 reads out the packet data stored in the buffer 321 and stores it in the buffer 325 of the user area 32B (step S4).

  Next, the H / W independent unit 107 determines whether or not the packet data stored in the buffer 325 of the user area 32B is a short packet (step S5). When the data size of the packet data is a short packet that is not an integral multiple of 512 bytes that is the maximum packet transfer size (step S5 / YES), the H / W independent unit 107 determines that the unused IO request b, Canceling c and completing Read () are performed (step S6), and the bulk-out transfer is terminated. Further, even when the packet data is a null packet, the H / W independent unit 107 cancels unused IO requests b and c and completes Read () (step S6), and performs bulk-out. End the transfer.

  If the data size of the packet data newly stored in the buffer 325 of the user area 32B is a data size that is an integral multiple of 512 bytes, which is the maximum packet transfer size (step S5 / NO), it is H / W independent. The unit 107 determines whether or not the effective memory size of the buffer 321 is the original size (4 Kbytes) (step S7). First, since the effective memory size of the buffer 321 is set to 512 bytes (step S7 / NO), the H / W independent unit 107 changes the effective memory size of the buffer 321 from 512 bytes to the original size of 4 Kbytes (step S7 / NO). S8) The issued IO request d (see FIG. 6) is issued to the H / W dependency unit 105 of the device driver (step S9). When the IO request d is issued to the H / W dependency unit 105, the H / W dependency unit 105 causes the kernel area 32A to prepare the buffer 321 with 4 Kbytes. That is, the buffer 321 in which the packet data has been stored is newly prepared in the kernel area 32A of the memory 32 with a new effective memory size and the like when the transfer of the stored packet data to the user area 32B is completed. The

After that, the subsequent packet data is stored in the buffer 322, and when the effective memory size of the buffer 322 is satisfied, as in the case of the buffer 321, the control unit 36 of the USB target controller 33 passes through the CPU 31 and the H / W dependent unit 105 The interrupt handler is notified that the packet data has been stored. The H / W dependency unit 105 receives the notification from the control unit 36 via the CPU 31 as an interrupt handler, and moves the IO request b from the IO request waiting queue to the IO request completion queue. Further, the H / W dependent unit 105 calls the callback routine of the H / W independent unit 107 set in the “pointer field to the callback routine” of the IO request structure shown in FIG. S10). When the H / W dependent unit 105 calls the callback routine, the CPU 31 reads out the packet data stored in the buffer 321 and stores it in the buffer 325 of the user area 32B (step S4). Thereafter, similarly, the H / W independent unit 107 determines whether or not the packet data newly stored in the buffer 325 of the user area 32B is a short packet (step S5). When the data size of the packet data newly stored in the buffer 325 of the user area 32B is a data size that is an integral multiple of 512 bytes, which is the maximum packet transfer size (step S5 / NO), the H / W independent unit 107 Determines whether the size of the buffer 322 is the maximum size (step S7). Initially, the size of the buffer 322 is set to about 3.5 Kbytes obtained by subtracting 512 bytes from the maximum size of 4 Kbytes, not the maximum size of 4 Kbytes (step S7 / NO). Therefore, the H / W independent unit 107 issues an IO request e (see FIG. 6) in which the effective memory size of the buffer 321 is changed to the original size of 4 Kbytes (step S8) to the H / W dependent unit 105 of the device driver. (Step S9). By issuing the IO request e to the H / W dependency unit 105, the H / W dependency unit 105 causes the kernel area 32A to prepare the buffer 322 in 4 Kbytes.
Thereafter, the effective memory size of the buffers 321, 322, and 323 becomes 4 Kbytes. Every time 4 Kbytes of packet data is stored in the buffers 321, 322, and 323, the H / W dependent unit 105 and the H / W independent unit 4 Kbytes of packet data is transferred to the user area 32 </ b> B of the application 108 via 107.

  In step S10, if the callback routine of the H / W independent unit 107 is not called even after the time-out period has elapsed since the IO request (for example, the IO request g shown in FIG. 6) is issued (step S11). / YES), cancellation of unused IO requests, and completion of Read () are performed (step S6), and the bulk-out transfer is terminated.

  The embodiment described above is a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.

10 Host device 11 CPU
12 Memory 13 USB Host Controller 30 Target Device 31 CPU (Control Device)
32 Memory 33 USB target controller 36 Control unit (notification means)
101, 108 Application 102 Class driver 103, 106 API
104 Host control / bus driver 105 H / W dependent unit 107 H / W independent unit 321 Buffer (first memory)
322 buffer (second memory)
323 buffer (third memory)
325 buffer

Claims (5)

A data receiving device comprising a plurality of memories for storing packet data transmitted from an external device via a data communication path,
Receiving means for receiving packet data transmitted from the external device via the data communication path;
When the maximum transfer size of the packet data transferred from the external device is set to an effective memory size capable of storing the packet data, and transmission of the packet data from the external device is started, the packet data is first transmitted in the plurality of memories. A first memory for storing
A notification means for notifying the control device that controls the data reception device of reception of packet data when packet data is stored in the first memory and the effective memory size of the first memory is satisfied;
A data receiving apparatus comprising: The plurality of memories sequentially store packet data subsequent to packet data stored in the first memory and sequentially transmitted from the first device and the external device. A plurality of subsequent memories having an effective memory size capable of storing data,
Wait time setting means for setting a wait time from the start of storing packet data to any of the plurality of subsequent memories until the packet data satisfying the effective memory size of the memory is stored;
The notifying means stores packet data that satisfies the effective memory size of the memory in the memory even after the waiting time has elapsed since the start of storing packet data in any one of the plurality of subsequent memories. 2. The data receiving apparatus according to claim 1, wherein when the data is not stored, the control apparatus is notified of completion of reception of packet data from the external apparatus. The subsequent memory includes a second memory and a third memory,
The effective memory size capable of storing the packet data of the second memory includes a memory size obtained by subtracting an effective memory size of the first memory from an effective memory size of the third memory. Data receiving device. Effective memory size changing means for changing the effective memory size of the first memory and the second memory;
The effective memory size changing means stores packet data satisfying the effective memory size of each memory in each of the first memory and the second memory, and the control device stores the packet data stored on the rear stage side. After being transferred to the processing unit, the effective memory size of the first memory and the second memory is changed to the effective memory size of the third memory, and the effective memory of the third memory is changed to the third memory. 4. The data receiving apparatus according to claim 3, wherein after the packet data satisfying the size is stored, the subsequent packet data is sequentially stored in the first memory and the second memory. A data receiving program of a data receiving device comprising a plurality of memories for storing packet data transmitted from an external device via a data communication path,
On the computer,
Receiving packet data transmitted from the external device via the data communication path by a receiving unit;
When transmission of packet data from the external device is started, the plurality of memories are used as a first memory in which the maximum transfer size of the packet data transferred from the external device is an effective memory size capable of storing packet data. First storing packet data in
When packet data is stored in the first memory and the effective memory size of the first memory is satisfied, a step of notifying reception of packet data to a control device that controls the data receiving device is executed. A featured program.

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