KR20070018981A - Complex logarithmic alu - Google Patents

Abstract

The present invention relates to a method and apparatus for performing log operations with real and / or complex numbers expressed in log format. In one exemplary embodiment, the ALU implements a log operation on complex numbers represented in logpolar format. According to this embodiment, the memory in the ALU stores a lookup table used to determine complex logs, while the processor in the ALU uses the stored lookup table to generate an output log based on a complex input operand expressed in logpolar format. Create In another exemplary embodiment, the ALU performs log operations on real and complex numbers expressed in log format. In this embodiment, the memory stores two lookup tables, one for determining the logs of the real number and the other for determining the logs of the complex number, while the processor uses the real or complex lookup table respectively. Generate an output log based on real or complex input operands expressed in log format.

ALU, Lookup Table, Accumulator, Memory, Butterfly Circuit

Description

Complex log ADL {COMPLEX LOGARITHMIC ALU}

FIELD OF THE INVENTION The present invention generally relates to computing and digital signal processing, and more particularly to pipeline logarithmic arithmetic of arithmetic logic units (ALUs).

ALUs have typically been used to implement various arithmetic functions such as addition, subtraction, multiplication, division, etc. for real and / or complex numbers. Conventional systems use either fixed-point or floating-point ALUs. ALUs that use finite accuracy real logs are also known. See, for example, "Digital filtering using logarithmic arithmetic" (NG Kingsbury and PJW Rayner, Electron. Lett. (January 28, 1971), Vol. 7, No. 2, pp. 56. -58). "Arithmetic on the European Logarithmic Microprocessor" (JN Coleman, EI Chester, CI Softley and J. Kadlec, July 2000) IEEE Trans. Comput., Vol. 49, No. 7 pp. 702-715 provide another example of a high accuracy (32 bit) log unit for real numbers.

Fixed-point programming places a mental burden on the programmer to track the position of the decimal point, especially after multiplication or division. For example, if the FIR filter is -0.607, 1.035, -0.607. Suppose we include a weighted addition of signal samples using the weighting factors of, which should be specified with an accuracy of one part in 1000. In fixed-point arithmetic, it is necessary to represent 1.035 × 1035, for example. As a result, multiplication of the signal samples by this number extends the resulting word length by 10 bits. To store the result in the same memory word length, we need to discard 10 bits; Which of each MSB (most significant bit) or LSB (least significant bit), or some, is discarded depends on the signal data spectrum and must be determined by simulation using real data. This makes it difficult to verify correct programming.

Floating point processors have been introduced to avoid the mental inconvenience of tracking a decimal point by automatically tracking the decimal point with the help of an "exponent" portion associated with each stored number of "mastissa" portions. The IEEE standard floating point format is as follows:

SEEEEEEEE.MMMMMMMMMMMMMMMMMMMMMMM,

Where S is the sign of the value (0 = +; 1 =-), EEEEEEEE is an 8-bit exponent, and MMM ... MM is a 23-bit mantissa. By the IEEE standard floating point format, the 24th most significant bit of the mantissa is always 1 (except for true), so it is omitted. Thus, in IEEE format, the actual value of the mantissa is:

1.MMMMMMMMMMMMMMMMMMMMMMM.

For example, the base 2 log numbers -1.40625 × 10 ^-2 = -1.8 × 2 ^-7 can be represented in the IEEE standard format as follows:

1 01111000.11001100110011001100110.

Also, since the zero index is 01111111, the number +1.0 can be written as:

0 01111111.00000000000000000000000.

Representing true zero would require a negative infinite exponent, which is not practical, resulting in artificial zero by interpreting all zero bit patterns as true zero instead of 2 ^-127 .

To multiply two floating point numbers, the mantissa with the suppressed MSB 1 replaced is multiplied using a fixed point 24x24 bit multiplier, which is a reasonably high complexity and delay logic, while the exponents are added to offsets of 127. One of them is subtracted. The 48-bit result of the multiplication must then be truncated to 24 bits, with the top 1 deleted after left alignment. Thus, multiplication is much more complicated than fixed point in the case of floating point.

To add two floating point numbers, the exponents must first be subtracted to see if the decimal points are aligned. If the decimal points are not aligned, a smaller number is selected to right shift by the binary space equal to the exponential difference to sort the decimal points before adding the mantissas, and the assumed one is replaced. In order to perform shifting quickly, a barrel shifter can be used, which is similar in structure and complexity to a fixed point multiplier. After addition and more specifically subtraction, the leading zeros must be left shifted from the mantissa while incrementing the exponent. Thus, addition and subtraction in floating point operations are also complex operations.

In the simple linear format, addition and subtraction of fixed point is simple, but multiplication, division, square and square root are more complicated. Multipliers are inherently configured as a sequence of "shift and conditional addition" circuits with a majority of logic delays. High speed processors may use pipelining to overcome this delay, but this typically complicates programming. Thus, attention has been drawn to minimizing the pipelining delay of high speed processors.

Note that floating point representation is a hybrid between logarithmic and linear representations. The exponent is the integer part of the logarithm to the base 2 of the number, and the mantissa is a linear fractional part. Since multiplication is complex for linear representations and addition is complex for logarithmic representations, this explains why multiplication and addition are complex for hybrid floating point representations. To overcome this, some known systems as described above have used pure log representation. This solves the problem of tracking decimal points and simplifies multiplication, but only adds complexity. Log addition was performed in the prior art using a lookup table. However, the size limit of the table limits the solution to limited word lengths, for example in the range 0-24 bits. In Coleman's references mentioned above, 32-bit accuracy has been achieved with reasonably sized lookup tables using interpolation techniques that require multipliers. As such, the Coleman process still includes the complexity associated with multiplication.

Although the prior art describes various methods and apparatuses for implementing real logarithm operations, the prior art does not provide a lookup table solution for complex arithmetic useful in wireless signal processing. Also, the prior art does not provide an ALU with shared real and complex processing capabilities. Since wireless signal processing often requires complex and real processing capabilities, a single ALU that implements real and complex logarithms is useful in wireless communication devices regarding size and / or power.

Summary of the Invention

The present invention relates to an arithmetic logic unit (ALU) for performing arithmetic calculations with real and / or complex numbers expressed in log format. Using log number representation simplifies multiplication and division operations, but addition and subtraction make it more difficult. However, the log of the sum or difference of the two input operands can be simplified using known algorithms as described herein. In the following description, assume that a> b and c = a + b. It can be expressed as

C = log _q (c) = log _q (a + b) = A + log _q (1 + q ^-r )

Where q is the base of the log, r = AB, A = log _q (a), and B = log _q (b). The operation represented by Equation 1, referred to herein as logadd, causes the log of the sum of a and b to be calculated using only addition and subtraction operations, wherein the value of log _q (1 + q ^-r ) is Determined using a lookup table.

In one exemplary embodiment, the present invention provides an ALU for performing a log operation on complex input operands expressed in logpolar format. For example, A = log _q (a) = (R ₁ , θ ₁ ) and B = log _q (b) = (R ₂ , θ ₂ ). Here, R and θ represent log size and phase angle, respectively, as described further below. According to this embodiment, the ALU includes a memory and a processor. The memory stores a lookup table used to determine the logs of complex numbers in logpolar format, while the processor uses the stored lookup table to generate an output log of complex input operands expressed in logpolar format.

In another exemplary embodiment, the present invention provides an ALU for performing log operations on both real and complex numbers expressed in log format. An exemplary ALU according to this embodiment also includes a memory and a processor. The memory stores two lookup tables, one for determining real logs, and the other for determining complex logs. The processor includes a shared processor that generates an output log based on input operands expressed in log format using a real lookup table for a real input operand and a complex lookup table for a complex input operand.

In any case, according to one exemplary embodiment of the present invention, the processor may include a butterfly circuit configured to simultaneously generate output logs for both logad and logsub operations. According to another exemplary embodiment, the processor may include a lookup controller and an output accumulator, the lookup controller calculating one or more partial outputs based on the lookup tables. The partial outputs may be determined during one or more iterations, or may be determined among one or more stages of the pipeline. The output accumulator generates an output log based on the partial outputs.

1 illustrates a coordinate comparison between the IEEE floating point format and the true log format for real numbers.

2 shows a chart comparison between the IEEE floating point format and the true log format for real numbers.

3 shows a block diagram of a linear interpolator.

4 shows a coordinate comparison between a true F-function and an exponential approximation.

5A and 5B show quantization regions of logpolar and Cartesian representations, respectively.

6 shows a block diagram of an exemplary ALU for concurrently performing log add and log sub operations.

FIG. 7 illustrates an implementation of a 16-point FFT using the ALU of FIG. 6.

8 shows a block diagram of an example ALU in accordance with the present invention.

9 illustrates a block diagram of an example lookup controller for the ALU of FIG. 8;

10 shows further details of an exemplary ALU in accordance with the present invention.

11A-11C show different assignments of complex numbers for real numbers.

The present invention provides an ALU for performing log operations on complex numbers and / or real numbers in log format. In one embodiment, the ALU performs log operations on complex numbers expressed in logpolar format using one or more lookup tables. In another embodiment, the ALU performs log operations on both complex and real numbers represented in log format using at least one complex lookup table and at least one real lookup table, respectively. In order to better understand the details and advantages of the present invention, the following description first provides details regarding number representation, conventional interpolation, iterative log operation, high accuracy iterative log addition, high accuracy iterative log subtraction and exponential approximation do.

<Example>

Can express

Log operations implemented in the ALU generally require a specific number format. As mentioned above, conventional processors may format real or complex numbers in fixed-point binary format or floating-point format. As mentioned above, the fixed point format is a simple linear format. Thus, addition and subtraction with fixed point are simple, while multiplication is more complicated. Floating point numbers are a hybrid between logarithmic and linear representations. Thus, addition, subtraction, multiplication, and division are all complicated for floating point formats. To somewhat overcome the difficulties associated with these formats, a pure log format can be used with an appropriate algorithm to solve the addition and subtraction problems associated with the log format. The following description provides additional details related to the pure log format that may be applied to the present invention.

Real log format mistakes can be abbreviated as (S 8.23) and can be expressed as:

S xxxxxxxx.xxxxxxxxxxxxxxxxxxxxxxx

These two real numbers can be used as a way to represent complex numbers. However, as described below, logpolar format may be a more useful method for representing complex numbers.

The base used for logging can be easily selected. However, it is advantageous to select one base overlaid with the other base. For example, choosing the base 2 has many advantages. First, as shown in equation (2), the 32 bit pure log format looks substantially the same as the (S8.23) IEEE floating point representation.

Pure log: S xx ... xx.xx ... xx ↔ (-1) ^S × 2 ^{-xx ... xx.xx ... xx}

IEEE: S EE ... EE.MM ... MM ↔ (-1) ^S × (1 + 0.MM ... MM) × 2 ^{-EE ... EE}

Since the integer part of the logarithm to base 2 can be offset by 127 as in the IEEE format, the number 1.0 is expressed in another format as:

0 01111111.00000000000000000000000.

Alternatively, 128 can be used as an offset, in which case 1.0 is expressed as:

0 10000000.00000000000000000000000.

Using 127 or 128 as the preferred offset is a matter of implementation.

All zero patterns can be defined as artificial zeros as in the IEEE floating point format. In fact, if the same exponential offset 127 is used, as shown in Figure 1, the pure log format is for all numbers of powers of two, for example 4, 2, 1, 0.5, and so on. Consistent with the IEEE format, each mantissa is only slightly different from powers of two.

For pure log format, the maximum representation is:

0 11111111.11111111111111111111111.

For base 2, this represents a log of an offset of approximately 256-127, that is, a number of nearly 2 ¹²⁹ or 6.81 × 10 ³⁸ .

The minimum expression value is:

0 00000000.00000000000000000000000

For base 2, this represents the same logarithm as -127 of 5.88 × 10 ⁻³⁹ . If desired, the above all zero format may be reserved to indicate artificial true zero, as in the IEEE case. In this scenario, the minimum representable number is as follows:

0 00000000.00000000000000000000001

This is a base 2 log that is approximately equal to -127, which still corresponds to approximately 5.88 × 10 ⁻³⁹ .

Quantization accuracy IEEE mantissa having a value between 1 and 2 is between ^2-23 accuracy of the LSB value, ^2-23 and ^2-24 (0.6 to 1.2 × 10 ^-7). The accuracy representing the number x of the base 2 log format is a constant 2 ^-23 in the logarithm, which gives dx / x = log _e (2) × 2 ^-23 or 0.83 × 10 ^-7 , which is better than the average of the IEEE quantization accuracy. More preferred between the two.

In other implementations, other base logs, such as base e, can be used. For base e, real numbers can be specified in 32-bit sign + logsize format as follows:

S xxxxxxxx.xxxxxxxxxxxxxxxxxxxxxxx

Or simply as (S7.24). Due to the larger base (e = 2.718), fewer bits to the left of the decimal point are sufficient to provide a suitable dynamic range, while extra bits to the right of the decimal point are needed for the same or better accuracy, which will be described below.

The log size portion may be a coded fixed-point amount, with the leftmost bit being the sign bit and not to be confused with the represented number of sign S. Alternatively, the log size portion may be offset by +64 (or +63) such that the bit pattern is as follows:

0 10000000.00000000000000000000000

The bit pattern represents zero log (number = 1.0). In the latter case, the maximum representable number is the base e log:

0 11111111.11111111111111111111111

This is an offset of 64, i.e., nearly 128 less than e ⁶⁴ or 6.24 × 10 ²⁷ , and the reciprocal represents the minimum representable number. Equation 3 shows the quantization accuracy of the base e logarithm.

2 compares the IEEE floating point format (+127 offset) with the base e format (+64 offset) and the base 2 format (+127 offset).

, 여기서, N은 양 또는 음의 정수)로 선택하는 것은 + 또는 - N 비트 위치들로 소수점을 이동하는 것과 등가이며, 동시에 동일한 성능을 제공한다. 밑으로서 8을 선택하는 것은 로그를 3으로 나누는 것과 같이, 소수점을 정수의 위치들로 이동하는 것과 등가가 아니다. 다시 말해서, 로그 밑을 선택하는 것은 이진 소수점의 우측과 좌측 간의 비트의 분할을 변경하는 것과 수학적으로 등가이며, 이는 정확도 및 동적 범위 간의 절 충(compromise)을 변경한다. 그러나, 소수점은 오직 단으로만 시프트될 수 있으며, 밑은 계속해서 변경될 수 있다. 부호화된 로그크기의 경우, (부호화되지 않은 127-오프셋 로그크기와 반대로), 부호 비트는 로그크기의 부호로서 참조함으로써 수의 부호(S 비트)와 구별된다. 이를 더 명료하게 하기 위해, 밑 10 로그에서, log₁₀(3) = 0.4771이지만, log₁₀(1/3) = -0.4771임을 고려하라. 따라서, +3의 값을 로그로 나타내기 위해, 수 및 로그의 부호가 +이며, ++0.4771로 쓰여질 수 있다. 이하의 표는 이러한 표기법을 설명한다.The bottom choice is actually equivalent to determining the tradeoff between dynamic range and accuracy within a fixed word length, equivalent to shifting the decimal point to one or fewer integer bits. Base 2 or 4 or √2 (typically

, Where N is a positive or negative integer) is equivalent to moving the decimal point to + or-N bit positions, while at the same time providing the same performance. Selecting 8 as the base is not equivalent to moving the decimal point to integer positions, such as dividing the log by three. In other words, selecting logarithmic is mathematically equivalent to changing the division of bits between the right and left sides of the binary decimal point, which changes the compromise between accuracy and dynamic range. However, the decimal point can only be shifted in steps, and the base can be changed continuously. In the case of the encoded log size (as opposed to the unsigned 127-offset log size), the sign bit is distinguished from the sign of the number (S bit) by referring to it as the sign of the log size. To make this clearer, consider that in the base 10 log, log ₁₀ (3) = 0.4771, but log ₁₀ (1/3) = -0.4771. Thus, to log the value of +3, the sign of the number and log is + and can be written as ++ 0.4771. The table below illustrates this notation.

Mark expression ++ 0.4771 log ₁₀ (+3) + -0.4771 log ₁₀ (+1/3) -+ 0.4771 log ₁₀ (-3) --0.4771 log ₁₀ (-1/3)

To ensure that all log representations are positive, an offset representation can be used. For example, if more than the number of logs selected, for example 0.0001, is displayed instead, the representation of 3 is log ₁₀ (3 / 0.0001) = 4.4771, and the representation of 1/3 is log ₁₀ (0.3333 /0.0001) = 3.5229. Due to the offset, both are now positive. An indication of 0.0001 would be log (0.0001 / 0.0001) = 0. This zero bit pattern represents a minimum possible amount of 0.0001.

Typical log tables require storing 10,000 numbers of logs between 0.0000 and 0.9999 to examine the logarithm, and storing similar amounts to obtain logs of the same accuracy. Log equality can be used to reduce the size of the lookup table. For example, log ₁₀ (3) = 0.4771 and log ₁₀ (2) = 0.3010. From this, it can be derived immediately as follows:

log ₁₀ (6) = log ₁₀ (2 × 3) = log ₁₀ (3) + log ₁₀ (2) = 0.4771 + 0.3010 = 0.7781

It can also be derived immediately as follows:

log ₁₀ (1.5) = log ₁₀ (3/2) = log ₁₀ (3)-log ₁₀ (2) = 0.4771-0.3010 = 0.1761

However, by any simple manipulation of the predetermined numbers 0.4771 and 0.3010, it cannot be derived as follows:

log ₁₀ (5) = log ₁₀ (2 + 3) = 0.6990

From the logs of 3 and 2 it is also not clear at all that:

log ₁₀ (1) = log ₁₀ (3-2) = 0

To address this problem, a lookup table based on the logad function F _a can be used. For example, the larger of log ₁₀ (3) and log ₁₀ (2), that is, 0.4771, is given to their difference function F _a [log ₁₀ (3)-log ₁₀ (2)] = F _a (0.1761) By addition, a log of (2 + 3) may be obtained, for base 10, as follows:

F _a (X) = log ₁₀ (1 + 10 ^-X )

Similarly, the logarithm of 3-2 may be obtained by subtracting the function F _S (0.1761) from the larger of log ₁₀ (3) and log ₁₀ (2), where for base 10, F _S (X) is As follows:

F _S (X) = log ₁₀ (1-10 ^-X )

However, the lookup tables of F _a (X) and F _S (X) still require storing at least 10,000 numbers for each function.

Interpolation method

Interpolation may be used to reduce the number of values stored in the lookup table. In order to facilitate the following description, interpolation is described in more detail below. For convenience, the base e is used. However, it will be appreciated that other bases may be used equally.

x _o by using the values given in Table A limited number of the example as a function F _a (x) of a ^{_{= log e (1 + e x}} ) to calculate a function of the point x _o given in Table F (X) Taylor The Taylor / McClaurin description provides:

F (x) = F (x _o ) + (xx _o ) F '(x _o ) + 0.5 (xx _o ) ² F "(x _o ) ...

Where 'denotes the first derivative and "denotes the second derivative. Based on this expansion theory, using the advantages of Taylor McClaurin expansion, log _e (c) = log _e (a + b) can be calculated as log _e (a) + F _a (x), where x = log _e (a)-log _e (b) and the values of x _o are provided in a table.

In order to use simple linear interpolation for the 32-bit sub-e case, the second term containing the second derivative F "must be ignored, for example, to the 24th binary digit less than 2 ^-25 . F _a (x) = The derivative of log _e (1 + e ^x ) yields:

F _a "(x) is peaked at 0.25 when x = 0. Therefore, when (x-x _o ) <2 ^-11 , the quadratic term is less than 2 ^-25 . To satisfy this requirement,

The rest of dx = x-x _o

0.00000000000xxxxxxxxxxxxx

In the form of

The most significant bit is formatted (5.11), i.e.

xxxxx.xxxxxxxxxxx

Is less than 2 ^-11 because it addresses the decimal point x _o in the table. As such, dx is a 13-bit quantity and x _o is a 16-bit quantity.

The degree of linear interpolation term F _a '(x _o ) should be approximately 2 ^-25 . Since F _a '(x _o ) is multiplied by dx less than 2 ^-11 , the accuracy of F _a ' (x _o ) must be 2 ^-14 . Extra LSB couples may be provided as a table for F _a (x _o ) to help reduce rounding errors, which is a lookup table for storing both F and F 'for each x _o value. It is proposed to be 5 bytes (40 bits) wide.

Thus, the values in the table include 2 ¹⁶ = 65,536 values of 26 bit F _a and the same number of corresponding 14 bit F _a 'values. In addition, _a 14x13 bit multiplier is required to form dx · F _a ′. Such multipliers inherently perform 13 shift and add operations. Thus, it includes approximately 13 logic delays. The complexity and delay of the multiplier may be somewhat reduced using Booth's algorithm, but a conventional multiplier can be used as a benchmark.

로 14 비트 F_a'(X_M) 값을 승산한다. 또한, 승산기(40)는 결과가 F_a'(X_M)와

의 27 비트 곱이 되도록 구성된다.3 shows a block diagram of an example of a conventional ALU that implements the linear interpolation described above. The ALU of FIG. 3 uses a subtractor 10, an adder 20, a F _a / F _a 'lookup table 30, a multiplier 40 and a subtractor 50 to determine the value C = log _e (A + B). Estimate. As used in this example, A = log _e (a) and B = log _e (b). As described below, since it may be necessary to perform backward interpolation on subtraction to prevent singularity, FIG. 3 interpolates the value of x ₀ from X _M by one more than the most significant 16 bit portion of x _. Shows that. A look-up table 30 in the F _a is in, with F _a 'values are a F _a calculation from the value of the center of the interval, i.e., X _M + 0.5' because it contains a value of F _a at X _M + 1 Can be a value. Multiplier 40 is a complement of 13 bits 2 of the least significant 13 bits of x,

Multiply the 14-bit F _a '(X _M ) value by. Multiplier 40 also results in F _a '(X _M )

It is configured to be a 27-bit product of.

The LSB of the 27 bit product may be input to the subtractor 50 as a borrow, after the remaining 26 bits are subtracted from the 26 bit F _a '(X _M ) value to yield the interpolation value with 26 bits, then the output adder It is added to the larger of A and B in (20), rounded up the result C to 31 bits of the log size by the carry-in bit of '1'.

The actual 32-bit log adder based on linear interpolation includes a lookup table 30 of approximately 65,536 × 40 = 2.62 megabits and a multiplier 40 of 13 × 14 bits. The components consume significant silicon area and do not have speed advantages in terms of logic delay. However, in order to process subtraction or complex arithmetic operations using interpolation methods, significant adjustments are needed to the word length and multiplier configuration.

For example, to implement subtraction using interpolation, the function values are determined by the following subtraction equation:

F _s (x) = log _e (1-e ^-x )

The Taylor / McCroline expansion of F _s (x) involves a first derivative:

This tends to go to infinity as x goes to zero. To keep the operations away from this singularity, the function uses one table, LSB, which is larger than the actual value of x = log _e (A)-log _e (B) (A> B) by It can be backward interpolated from a value:

F _s (x) = F _s (x _o )-(x _o -x) F _s ' (x _o )

The above equation is the implementation shown for the logad of FIG. Then, when at least the most significant bit of x is zero, x _o is one LSB with a larger value, thus preventing the specificity.

Such as the addition, in the case of the same 16/13 bit division, the minimum value of x _o is ^2-11, the size of the F _s' are the values approximately 2,048. However, the value of F _s 'is 12 bits longer than the logad counterpart, thereby increasing the size of the multiplier for forming dx · F _s ' to 13 × 26 bit devices.

In view of the above, the synergy between actual addition and actual subtraction as well as complex operations is limited in ALU implementation interpolation. Thus, both lookup tables and multiplications are required for interpolation execution, which becomes undesirable to implement in hardware logic.

Repeated Logarithmic Operations

As an alternative to the interpolation process described above, an iterative solution can also be used to reduce storage requirements. The iterative solution uses relatively few two tables to compute log output using an iterative process based on tabulated functions. To illustrate the iterative solution, from log ₁₀ (3) = 0.4771 and log ₁₀ (2) = 0.3010, how log ₁₀ (5) = log ₁₀ (3 + 2) and log ₁₀ (1) = log ₁₀ (3-2 Decimal example is provided to illustrate whether can be derived.

The logad function table, also referred to as F _a -table, is for values of x between 0.0 and 4.9 instead of 0.1 and stores 50 values based on Equation 4 below. Another table, also called a G-table or a correction table, stores 99 values for values of y between 0.001 and 0.099 instead of 0.001 based on Equation 11:

G (y) = -log ₁₀ (1-10 ^-y )

The two-table iteration process for the log (5) = log (3 + 2) example is described below using the two lookup tables. Although the following is described by base 10, those skilled in the art will understand that any base may be used. For embodiments using base 10 and other bases, Equations 4 and 11 define the function and correction table for base 10 calculations, respectively, and Equation 12 is generally a function for any base q and It will be understood that the correction tables are defined.

F _a (x) = log _q (1 + q ^-x )

G (y) = -log _q (1-q ^-y )

For the logad process, the arguments x = AB = log ₁₀ (3)-log ₁₀ (2) = 0.1761 are rounded to the nearest single decimal place 0.2 first. From the F _a -table of the 50 values, we can find that F _a (0.2) = 0.2124. By adding 0.2124 to 0.4771, first approximately log ₁₀ (2 + 3) is 0.6895. The error resulting from rounding x from 0.1761 to 0.2 is 0.0239. The error is never greater than 0.099, so a 99 value correction lookup table G (y) is used. For a correction value y = 0.0239, rounded to 0.024, the G-table gives a correction value of 1.2695. By combining the values from the first lookup table F _a (0.2) = (0.2124) and the eigenvalues of x (0.1761) and G (y) = 1.2695, a new factor of F _a , x '= 1.658 is created. Those skilled in the art will understand that in this case the prime defining x does not represent a derivative.

When rounded to the nearest single decimal, x '= 1.7. F _a (1.7) = 0.0086, which gives a second approximation of 0.6981 when added to the first approximation of log ₁₀ (2 + 3) of 0.6985. The error when rounding 1.658 to 1.7 is 0.042. Looking up y = 0.042 in the G-table gives a 1.035 value, which when added to the previous F _a value of 0.0086 and x '= 1.658, results in a new x value x "= 2.7016. X" to 2.8 after rounds, _a F - using the table, a F _a (2.8) = 0.0007 is caused. When adding 0.0007 to a second approximate value (0.6981), there is provided a final third approximate value of 0.6988, which is only of 0.6990 with an accuracy that is expected when using the G look-up tables of F _a look-up table, and only 100 values of 50 values I think it's close enough to the actual value. If desired, another iteration may be performed for a slight increase in accuracy. However, more than three iterations are generally not necessary for the addition. Alternatively, if the maximum number of iterations is chosen to be 3, the factor of F _a for the final iteration may be rounded to the nearest single decimal place of 2.7. Inde F _a (2.7) = 0.0009, which when added to the second approximate value of log ₁₀ (3 + 2) of 0.6981, the expected result that the _{log 10 (5) = log 10} (3 + 2) = 0.6990 are provided .

The two-table iteration process involves accepting a three-step process instead to avoid 100-fold reduction and multiplication of the lookup table size. In a hardware implementation, the total number of logic delays required for three iterations may actually be less than the number of logic delays through the iterative add / shift structure of the multiplier. In any case, the reduction described above is useful when silicon area and / or accuracy are of primary importance.

Values of log ₁₀ (3-2) can be calculated similarly. The starting approximation is a larger number of logs, that is, 0.4771. The F _s -table for subtraction stores the following values in steps of 0.1;

F _s (x) = log ₁₀ (1-10 ^-x ) (for base 10)

F _s (x) = log _q (1-q ^-x ) (for normal base q)

Here, the G-tables keep the same. The difference between log ₁₀ (3) and log ₁₀ (2) of 0.1761 is rounded to the nearest single decimal place 0.2. A look up of 0.2 in the subtraction table results in F _s (0.2) = -0.4329. Adding -0.4329 to the starting approximation 0.4771 yields a first approximation of log ₁₀ (1), 0.0442.

In the case of addition, the error when rounding 0.1761 to 0.2 is 0.0239. When processing a G-Table previously defined with 0.024, 1.2695 is returned. When added to the look-up table values, new F _s of x '= 1.0127 - - 1.2695 the previous F _s F _s of acquired and before the x -0.4329 = 0.1761 The table acquisition is generated. the x 'nearest decimal digit, rounded to 1.1, and F _s - is when using the back table, F _s (1.1) = -0.0359 is calculated. By adding -0.0359 to the first approximation value (0.0442), a second approximation for log ₁₀ (1) of 0.0083 is provided. The error when rounding 1.0127 to 1.1 was 0.0873. Using the value 0.087 to address the G-table, G (0.087) = 0.7410 is provided. When added to the previously unrounded F _s -table argument of 1.0127 and the F _s -table lookup value of -0.0359, a new F _s -table argument x "= 1.7178 is generated. If x" is rounded to 1.8, F _s (1.8) = -0.0069 is caused, which is added to the second approximation of 0.0083 to obtain a third approximation for log ₁₀ (1) of 0.0014. The error when rounding 1.7178 to 1.8 was 0.0822. When addressing a G-Table with 0.082, the value 0.7643 is returned. Adding this value to the previous F _s -table argument of 1.7178 and the old F _s -table lookup value of -0.0069 produces a new F _s -table argument of x "'= 2.4752. Rounding 2.4752 to 2.5, F _s (2.5) a = -0.0014 function values are generated. When the addition -0.0014 to the third approximate value (0.0014), the _{log 10 (1) = log 10} (3-2) = 0 is provided as expected. F _s The algorithm converges because the factor of increases with each iteration, resulting in smaller and smaller corrections.

The subtraction process described above was the same as for the addition regardless of the use of the subtraction-version of the F-table. However, both addition and subtraction use the same G-table. In addition, subtraction required one more repetition than addition to provide the desired degree; This is because the factor of F _s increases slightly less rapidly at each iteration, especially at the first iteration, because the increase when adding F _s -value is negative for subtraction.

High accuracy logad

In general, the logad problem to be solved for the more common base q log can be provided by the following steps:

A = log_q(a) 및 B = log_q(b)라고 가정함 - 여기서, a 및 b는 양수이고 q는 밑.

Assume that A = log _q (a) and B = log _q (b)-where a and b are positive and q is base.

목표: C = log_q(c)를 찾음 - 여기서, c = a + b.

Goal: find C = log _q (c) where c = a + b.

따라서, C = log_q(a + b) = log_q(q^A + q^B)

Thus, C = log _q (a + b) = log _q (q ^A + q ^B )

A를 A 및 B 중에서 큰 수로 하라.

Let A be the larger of A and B.

이어서, C = log_q(q^A(1 + q^-(A-B)))

Then C = log _q (q ^A (1 + q- ^(AB) ))

= A + log _q (1 + q- ^(AB) )

= A + log _q (1 + q ^-r ), where r = A-B and positive.

Therefore, the problem is reduced by calculating the function log _q (1 + q ^-r ) of the single variable r.

If r has a limited word length, the function value can be obtained by the function lookup table. For example, for a 16-bit r-value, the function lookup table must store 65,536 words. In addition, for base q = e = 2.718, if r> 9, the value of the function is different from 0 less than 2 ^-13 , suggesting that only a 4 bit integer part needs to be considered, with a 12 bit fractional part. . Then, if r> 9, the function value is 0-12 binary places after the decimal point, so the lookup table is only required for values up to 9 r, giving 9 × 4,096 = 36,864 words of memory.

Since the maximum value of the function is log _e (2) = 0.69, when r = 0, only 12 bit fractional parts need to be stored, so the memory requirement is only 36,864 12 bit words, not 65,536 16 bit words. In the case of base 2, the function is from 0 to 12 binary places for r> 13, so again only the 4-bit integer portion of r needs to be considered. If one bit is used for the sign, the log size portion is only 15 bits long, for example 4.11 format or 5.10 format, so that the above-described figures can be adjusted.

However, for example, using word lengths of 32 bits, the direct lookup table for the function is excessively large to obtain degrees much higher than 16 bits. For example, to provide a degree and dynamic range comparable to the IEEE 32-bit floating point standard, A and B must each have a 7-bit integer part, a 24-bit fractional part, and a sign bit for base e. The value of r must now be greater than 25log _e (2) = 17.32 before the function is on the order of 0 to 24 bits, which can be represented by the positive integer part of r's 5 bits. Thus, the tentative 29-bit r-value of format 5.24 should be considered as an argument of the function F _a . A lookup table size of 18 × 2 ²⁴ or 321 million 24-bit words is required for the desired lookup of r for values between 0 and 18. All work on log operations is concerned with reducing the table size, and the ultimate goal is to make the actual word length 64 bits. Several techniques described herein are directed towards this goal.

In order to reduce the size of the lookup table from a single large table, one implementation of the invention requires r to be equal to MS, respectively, as desired for the desired lookup of the logad function F _a using all bits of r as addresses. And dividing into LS (lowermost) portions, r _M and r _L. The MS and LS portions process two much smaller tables, F and G, which are described below. The MS part represents the "rounded" version of the input value, while the LS part represents the difference between the rounded version and the unique total argument value.

As shown in equation (14), let r _{M be} the most significant 14 bits of r <32 and r _{L be} the least significant 15 bits of r.

r _M = xxxxx.xxxxxxxxx

r _L = 00000.000000000xxxxxxxxxxxxxxx

For convenience, the lengths of r _M and r _L may simply be denoted as (5.9) and (15). Other divisions of r into the most significant and least significant bit parts can be used equally by the apparent modification of the method, and some considerations for referring to the specific divisions described below are different word lengths (eg, 16 bits) or complex numbers. It relates to the ability to reuse the same F and G tables for operations.

Let r _M ^{+ be} the maximum possible value of r _L , that is, the value of r _M increased by 00000.000000000111111111111111. It will be appreciated that only the lowest 15 bits are unique r-values set to one. In some implementations, r _M can be increased by 0.000000001. That is:

r _M ⁺ = xxxxx.xxxxxxxxx + 00000.000000001

Suppose the complement of r _L is

_{^{r L - = r M + -}} r

One of the two's complement or 2's complement r _L, r the growth rate of the two alternatives of _{M, ^{i.e., r L - = 00000.000000000111111111111111 - 00000.000000000xxxxxxxxxxxxxxx}} ( number of beam _L r) or ^{_{r L - = 00000.000000001000000000000000 - 00000.000000000xxxxxxxxxxxxxxx (}} r L Depends on which augment is used. This results in the following for e under:

이다. log(1 +

) 를 확장하면 다음과 같은 결과를 낳는다:here,

to be. log (1 +

)) Produces the following output:

이다. 반복하면, 원하는 답이 이하의 함수들의 합을 포함함을 보여준다: here,

to be. Repeating, it shows that the desired answer includes the sum of the following functions:

The functions depend only on the most significant 14 bits of each r-factor, which can then be obtained from a lookup table of only 16,384 words.

)을 가산함으로써 유도되는데, 상기 후자 값은 r_L ^-가 15 비트 값이기 때문에 32,768 워드들을 갖는 정정 룩업 테이블, 즉, G-테이블에 의해 제공된다.In the context of Equations 17-19, the decimal number (s) used to define the indicated r-values does not represent a derivative. Instead, a series of r-values r, r ', r ", etc., accumulate the value just obtained from the logad function lookup table F _a to the preceding value, ie a value that depends on the least significant 15 bits of r. -log _e (1-

), Which is provided by a correction lookup table with 32,768 words, i.e., a G-table since r _L ^- is a 15 bit value.

Even though the stored values are calculated from r _M ⁺ and r _L ⁻ , the function and correction lookup tables can be addressed directly by r _M and r _L , respectively. If the lookup table functions F _a and G are called respectively and the correction values are always very negative, then a positive correction value can be stored in the G-table. The positive correction value is added to the previous r-factor, instead of storing and subtracting the negative value. In addition, the minimum correction value, or at least its integer portion, of the G-table may be subtracted from the stored values to reduce the number of stored bits, and added again each time the value is pulled from the table. For base 2, the value of 8 fits as the minimum correction value and in some implementations does not need to be added again. The repetition is as follows:

1. Initialize the output accumulator value C to the greater of A and B.

2. If A is bigger, initialize r with A-B. If B is larger, initialize r with B-A.

3. Divide r by r _M and r _L.

4. Look up F _a (r _M ⁺ ) and G (r _L ⁻ ), as addressed by r _M and r _L , respectively.

5. Accumulate F _a with C and F _a + G with r.

6. If r <STOP_THRESHOLD, repeat from step 3 (described below).

)의 값은 항상 대략 6.24보다 커서, 반복은 항상 3 사이클 이하로 종료된다. 정정 값들은 밑 2에 대해 비례해서 커져서, r은 항상 많아야 3 사이클들동안 밑 2에 대해 25를 초과한다. 일반적으로, 임의의 밑에 대해 3 사이클들이면 통상 충분하다.Those skilled in the art will appreciate that a few logic gates may have a logic b6.OR. (b5.AND. (B4.OR.b3.OR.b2)) (32-bit setting, or 16-bit setting, 8, 4, or It will be appreciated that it may be used to detect r-values greater than 18 using a setting of one of two bits, where the bit index indicates the bit position to the left of the decimal point. Function ^{_{G (r L -) = log}} e (1 -

) Is always greater than approximately 6.24, so that iteration always ends in less than 3 cycles. The correction values increase proportionally for base 2, so r always exceeds 25 for base 2 for at most 3 cycles. In general, 3 cycles for any bottom are usually sufficient.

High Accuracy 2-Table Log Sub

If the signs S associated with A and B indicate that a and b have the same sign, the above-described log addition algorithm, referred to as "logadd", can be used. Otherwise, a log subtraction algorithm called "logsub" is required. The following table shows when each algorithm is used:

Code (a) Sign (b) Addition subtract b from a + + use logadd (A, B) use logsub (A, B) + - use logsub (A, B) use logadd (A, B) - + use logsub (B, A) use logadd (A, B) - - use logadd (A, B) use logsub (A, B)

The sign of the result is always the sign associated with a larger log size than when the logad algorithm is used.

If the sign associated with the second argument is inverted first, the same holds true for the logsub algorithm. If subtraction is required, inversion of the sign of the second argument can be performed when applying the second argument to the input of the log unit. The "logsub" algorithm is derived as follows: Let A = log (| a |) and B = log (| b |). C = log (c) is required to be found, where c = | a | -| b | to be. Let A be the larger of A and B. For convenience, the absolute value is denoted by (||), assuming both a and b are positive:

C = log _e (ab) = log _e (e ^A -e ^B )

In the case of logad, the base e is used in this example for illustrative purposes only, and is not limited.

Since A is assumed to be greater than B:

C = log _e (e ^A (1-e- ^(AB) ))

= A + log _e (1-e- ^(AB) )

= A + log _e (1-e ^-r )

Where r = A-B and is positive. Thus, the problem is reduced to calculating the function log (1-e ^-r ) of the single variable r. Let r _M , r _L , r _M ⁺ and r _L ⁻ be as defined previously. Then, for base e:

이다. log(1 +

) 를 확장하면 다음과 같은 결과를 낳는다:here,

to be. log (1 +

)) Produces the following output:

이다. 결과를 반복하면, 원하는 답이 이하의 함수들의 합을 포함함을 보여준다: here,

to be. Repeating the results shows that the desired answer includes the sum of the following functions:

The functions depend only on the most significant 14 bits of each total word length r-values, which can then be provided by a lookup table of only 16,384 words.

Even though the stored values are calculated from r _M ⁺ and r _L ⁻ , as in Log Add, the lookup tables for the log sub can be configured to be addressed directly by r _M and r _L. Also, as with logad, the decimal number (s) used to change the indicated r-values does not represent a derivative.

Calling the look-up table of F _s and G (G is the same look-up table and a log add algorithms), respectively, and when the store a positive value of G as before, are generated F _s and G tables required to log the sub-operations. Since 1-e ^-r is always less than 1, F _s is always negative, so a positive magnitude can be stored and subtracted instead of the addition. Another method stores discarded negative values of negative sign bits, which are placed outside the lookup table by appending the most significant '1' when subtraction is in progress. A preferred choice is to cause simplicity of logic and maximum synergy of lookup table values between addition and subtraction, which is described below. In any case, the following steps outline the "logsub" process:

1. Initialize the output accumulator value C to the greater of A and B.

2. If A is bigger, initialize r with A-B. If B is larger, initialize r with B-A.

3. Divide r by r _M and r _L.

4. Look up F _s (r _M ⁺ ) and G (r _L ⁻ ), as addressed by r _M and r _L , respectively.

5. Accumulate F _s with C and F _s + G with r.

6. If r <STOP_THRESHOLD, repeat from step 3 (described below).

For both LOGADD and LOGSUB algorithms, STOP_THRESHOLD is chosen so that any contribution derived from another iteration is less than half of the LSB. This occurs at 17.32 for base e with 18 binary digits after the decimal point or at 24 for base 2 with 23 binary digits after the decimal point. Originally, less than 2 bases that provide a STOP_THRESHOLD of 31 may be found, which uses an F-function defined for the total address space that can be addressed by the selected MSBs of r. Also, a base greater than e that provides a STOP_THRESHOLD of 15 may be found, which has the same attribute. However, the actual benefits of base 2 appear to be greater than any advantage of using the total address space for F-tables. In general, for base 2, STOP_THRESHOLD is simply 1 or 2 greater than the number of binary digits in the log-expression after the decimal point.

As suggested by the decimal examples described above, if the final factor used to address the F-table, for example r _M "' ⁺ is rounded off instead of rounded from r _M "', the degree after a finite number of iterations is improved. do. If the two-table iteration process always executes a fixed number of iterations, or if the process identifies the last iteration, the argument of F is discarded at the last iteration. The final iteration may be identified, for example, by r within a specific range of STOP_THRESHOLD (˜6 for bottom e, or ˜8 for bottom 2), indicating that the next iteration is bound to exceed STOP_THRESHOLD. When the method is used, the address of the F-table can be reduced by one if the leftmost bit of r _L is zero in the last iteration. In the described pipeline implementation, the final F-table content is simply calculated for the round-down factor.

The difference between the LOGSUB and LOGADD algorithms is the use of the F _s lookup table, not only F _a . Since both are 16,384 words in size, they can also be combined into a single function F-table with extra address bits to select the + or-version denoted by F (r _M , opcode), with the extra argument "opcode" being LOGADD Or an extra address bit with a value of 0 or 1 to indicate which of the LOGSUB algorithms to apply. In addition, since the peripheral logic (ie, input and output accumulators and adders / subtractors) are small compared to the iterative lookup tables, it costs little to duplicate the peripheral logic to form independent adders and subtractors. Also, the similarity between the functions F _a and -F _s is described below for explanation.

Exponential approximation

As described above, r _M ⁺ may include r _M increased by the maximum possible value of r _L (0.00000000011111111111111), or may include r _M increased by 0.000000001. The advantage of choosing 0.0000000001111111 .... 1 instead of 0.000000001 as an fragment of r _M is that the G table can be addressed by complement of r _L during the iteration algorithm, or directly obtain the value of F if r _M = 0. Can be addressed by r _L (not complement), so a single iteration is sufficient if it is difficult to subtract two nearly identical values. Since the carry does not need to be delivered, validating both the complement and non-compensation values is simpler and faster than forming a two-complement.

For logad, the values in F _a -table can be defined as follows:

Where d is preferably an increment which is the maximum possible value of X _L , ie the value of all ones. The function can be configured as a lookup table addressed by X _M. For subtraction, the values of F _s can be defined as follows:

For large values of X _M and also for 32-bit operations, F _a (X _M ) = F _s (X _M ), and the argument range between 16 and 24 can be suitably approximated by the following equation:

Here, X _M1 is an integer part (bit to the left of the decimal point) of X _M , and X _M2 is a decimal part, that is, a bit to the right of the decimal point. Functions in parentheses can be stored in small exponential lookup tables. The right shifter can implement an integer part, reducing the table size since only a few bits need to address the exponential function.

4 shows the similarities between the exponential approximation E and the function values F _a , F _s . When the argument ranges from 16 to 24, E is substantially the same as F _a and F _s . 4 is another approximation.

It shows whether the approximate difference between this exponential approximation and the true function values, dF _a = E-F _a and dF _s = F _s -E, is approximated. Thus, for X _M in the range of 8 to 16, an exponential approximation E can be used when corrected by a small correction value E ₂ , which is less than or equal to 8 bits long, as can be seen in FIG. 4. When 24 positions after the binary decimal point are required, the result is 17 bits long.

Since the area under the E curve approximates the silicon area needed to implement an approximate exponential approximation, Figure 4 shows the approximate silicon area needed to implement the function tables for logad and logsub operations. Using the base 2 logarithmic scale as the vertical scale means that the height represents the word length of the binary value. The horizontal scale represents the number of these values. Thus, the area under the curve represents the number of bits of ROM needed to store the curve values. However, the exponential function E is periodic and the values repeat every time 1 increases except for the right shift. Therefore, only one cycle addressed by the fractional part X _M2 needs to be stored, and the result has shifted the number of positions given by X _M1 . Thus, the exponential function E requires very few tables. Also, since the correction values dF or E ₂ obviously have less area under the curve than the intrinsic F _a and F _s functions, using the exponential approximation E, storing correction values dF and E ₂ yields F _a and F _s . It requires smaller silicon area and smaller table size than storing.

Equation 29 provides the G-function for the least significant bit:

Here, (dX _L ) is the same as the complement of X _L when d is all 1. The minimum value of G (X _L ) depends on the division of the 31-bit log size between X _M and X _L. If X _M is 5.8, then X _L is 0.00000000xxxxxxxxxxxxxxx and less than 2 ^-8 . The minimum value of G is 8.5 when X _L = 0. If X _M is form (5.7), the minimum value of G is 7.5; if X _M is form (5.9), the minimum value of G is 9.5. Since the value of X is increased by at least the value of G in each cycle, as long as the G values are larger than 8 on average, X exceeds 24 in 3 cycles. In the following, it is assumed that 32 bit operations are maintained for the purpose of explanation. When the minimum value of G is 8.5, the base value of 8 can be subtracted from the stored values.

Logarithmic Operations for Complex Numbers

The various processes described above generally apply to log operations for mistakes. However, wireless communication signals may use both real and complex representations. For example, typical applications for real and complex signal processing include wireless signal processing. In a wireless system, the signals received at the antenna include radio noise and may be represented by a complex sample sequence. To maximize the range, it is usually desirable to recover the information using the weakest signals possible for noise. Thus, since there is no need to use a degree of quantization better than the expected noise levels, the complex representation of the samples obtained at the antenna does not require high accuracy digitization. After processing the complex noise signal to recover information and correct errors, the noise is removed; The resulting information may now require a higher degree of accuracy. For example, speech may be represented by a real sample sequence, but a higher accuracy digital representation may be required because the processed raw antenna signal raises the fidelity of the signal to the noise ratio of speech.

Signal processors that provide both high precision operations for real numbers and lower accuracy operations for complex numbers are a concern in wireless applications such as cell phones and cell phone systems. Such a processor may include memory for program storage, data memory for storing real and complex data to be processed, real and complex ALUs, and input / output devices that may include an AD converter and a DA converter. The data memory stores words equal to the word length of the designed ALU; It is logical to use the same word length for real and complex numbers so that they can be stored in the same memory. However, the present invention does not require this.

Typically, 16 bit words are sufficient for speech processing. Thus, it is a concern to determine if a 16 bit complex representation provides a dynamic range suitable for representing noise signals received by an antenna. This was applied to European LM Ericsson and US affiliate Ericsson-GE during 1988-1997, using a 15-16-bit logpolar representation containing 8-bit log amplitude and 7-bit phase. In the case of the first digital cell phone manufactured and sold by the company. These products are implemented in combination, and US Pat. No. 5,048,059, which is incorporated herein by reference; Direct digitization of radio signals into complex logpolars was used in accordance with Nos. 5,148,373 and 5,070,303.

For real numbers, any base can be used for the amplitude log. If the base e is used, the log amplitude is expressed as Nepher to represent the simultaneous signal level. As is known in the art, one napper is equivalent to approximately 8.686 decibels (dB), so the 8-bit log amplitude of format xxxx.xxxx varies from 0 to 15, with signal levels varying from 0 to 15 and ~ 139 dB Indicates.

The quantization error is 1/2 of the least significant bit or +/- 1/32 or 0.27 dB of the nefer, which is a percentage error of approximately 3.2%. In theory, the error is evenly distributed between +/- 3.2% and has an RMS value of 1/3 of the peak of approximately 1%. Thus, the quantization noise is one hundredth of the signal level, i.e., 40 dB below the signal level, and may be smaller if over-sampling is used, i. Nyquist) is a sampling larger than the ratio.

The advantage of the logpolar representation is that the degree of quantization remains constant over the full range of signal levels. Quantization noise of -40dB with a total dynamic range of 139dB is considered more suitable for most wireless signal applications.

FIG. 5A illustrates how complex surfaces are segmented into element regions using a logpolar representation as opposed to the Cartesian representation of FIG. 5B. The white "hole" in the center of the logpolar chart is the area where the signal level is less than 0000.0000 nippers, and the outer circle is the highest signal level of 1111.1111 nipper. If the lower limit of 0000.0000 is chosen to be 10 dB below the radio noise level, this ensures that noise excursions are properly represented, and that the statistics of noise are not unfairly modulated by the numerical representation. Thus, the outer circle represents a signal level of 129 dB for noise, which is not exceeded even by the strongest signals.

The finite number of bits used to represent the phase angle results in quantization error and noise. The noise contribution from phase quantization has an RMS value of 1/12 of the minimum phase bit value in radians. If 8 bits are used to represent the phase, the minimum phase bit has a 2π / 256 radian value and the quantization noise is 2π / (12 * 256) = 0.002 or -53.8dB relative to the signal level. This is less than -40dB log amplitude quantization noise.

Bit assignments of one bit more amplitude and one bit less phase cause the log amplitude quantization to be approximately -46 dB and the phase quantization noise to be -47.8 dB. Thus, when a 16 bit word length is used, a logpolar format of xxxx.xxxxx for log amplitude and 0.xxxxxxx (modulo 2π) for phase is proposed.

If the base 2 algorithms are used to represent the log amplitude, the quantization noise in the xxxx.xxxxx format is reduced by log _e (2) or 3.18 dB to -49 dB. The dynamic range is reduced to 16 nefers, or 139 dB to 16 × 6 dB = 96 dB, which is still suitable.

Log polar numbers include log amplitude, i.e. {xxxx.xxxxx; 0.xxxxxxx} = {log (r); [theta]} is stored or first phase, i.e. {0.xxxxxxx; xxxx.xxxxx} = {θ; log (r)} can be stored. In the case of complex numbers, it may be useful to think of the phase as an extension of the sign's real number or one bit "phase" to represent an angle greater than just two angles 0 degrees and 180 degrees, so that the "phase-first" format does this. Provide a logical format to describe. In complex arithmetic, addition and subtraction may be almost indistinguishable, where the number of combinations that discriminate by 0 degrees (ie, addition) or 180 degrees (ie, subtraction) are only two points within the total range of relative phase angles considered. .

Using the logpolar format, it is obtained by the fixed-point addition of the small log amplitude portion of the two complex numbers (note the underflow or overflow) and the fixed-point addition of the phase portions ignoring the overflow, each of which is modulo-2π Is calculated. When the binary phase word quantization levels are evenly placed across the 0 to 2π range, as required for phase calculation, the rollover in binary addition exactly corresponds to the modulo-2π operation. Similarly, the quotient of two logpolar complex numbers is obtained by fixed point subtraction.

Considering using the same ALU for 16-bit logreal and 16-bit logpolar operations, the only difference in addition or subtraction is any carry from the addition or subtraction of the log amplitude portion, for logpolar It can be seen that the barrow is not allowed to be passed to the phase portion of the adder or subtractor, and if the log amplitude-first format is used, the reverse is also not allowed.

To illustrate how log operations can be implemented for complex numbers represented in logpolar format, consider the following: Suppose Equation 30 expresses two Cartesian complex numbers z ₁ and z ₂ in logpolar format, Z ₁ and Z ₂ for base e.

Z ₁ = (R ₁ , θ ₁ ) = log _e (z ₁ )

Z ₂ = (R ₂ , θ ₂ ) = log _e (z ₂ )

To determine Z ₃ = log _e (z ₃ ), one may implement the very similar procedure described above for real numbers, where z ₃ = z ₁ + z ₂ . First, note the following:

Assuming that Z ₁ has a log size (R ₁ ) greater than Z ₂ , applying logic similar to that described above, Z ₃ can be expressed as:

Here, Z = Z ₁ -Z ₂ has a positive real part R ₁ -R ₂ because R ₁ > R ₂ , which ensures the size of e- ^Z <1. Thus, the problem of calculating Z ₃ given Z ₁ and Z ₂ is reduced to calculating the function log _e (1 + e ^-Z ) of the logpolar complex variable Z = (R + jθ), where R = R ₁ -R ₂ , and θ = θ ₁ -θ ₂ . Although the above example uses base e, those skilled in the art will understand that any base may be used.

When R> 6, the addition or subtraction of smaller values does not affect the fifth binary position, and the result is a larger value. Thus, only three bits to the left of the binary decimal point need to be considered for R.

The function log _e (1 + e ^-Z ) can be calculated by a wide variety of means. For example, a single table, single iterative process can be used. It can be applied to low and high precision numbers, and the size of the single lookup table required for high accuracy numbers can be enormously large. The lookup table may have an optimal structure. For example, for 16-bit logpolar operations, where 16,384 x 32-bit ROMs are provided, it may be useful to store pairs of values for addresses distinguished by π in the θ-component, or conjugate conjugate symmetry is used. It may be useful to save it in half. Complex log addition and complex log subtraction of the same pair of input values may be performed simultaneously in one cycle.

Simultaneous addition and subtraction of a pair of values in one cycle is known as a butterfly operation and is typically performed in a butterfly circuit. 6 shows an example ALU that includes a low accuracy complex butterfly circuit 100. The butterfly circuit 100 includes a magnitude accumulator 102, a phase accumulator 104, a selector 106, a lookup table 108, a sum combiner 110 and a difference combiner 112. When R ₁ is greater than R ₂ , the log size accumulator 102 calculates the log size difference represented by R = R ₁ -R ₂ , and the phase accumulator 104 has a phase represented by θ = θ ₁ -θ ₂ . Calculate each difference. Also, when R ₂ is greater than R ₁ , magnitude accumulator 102 calculates the logarithmic size difference expressed as R = R ₂ -R ₁ , and phase accumulator 104 is represented by θ = θ ₂ -θ ₁ . Calculate the phase angle difference. The magnitude accumulator 102 and the phase accumulator 104 output the calculated differences to the lookup table 108.

Lookup table 108 includes logarithms of complex numbers for all angles. The logsize difference and the phase difference address the lookup table 108 to provide two logpolar values F (Z) and F (Z + π). If desired, the table can always divide in size by using positive each argument and conjugating the output F (Z) values when the unique each address is negative.

The magnitude accumulator 102 controls the selector 106 to select Z ₁ or Z ₂ as Z _L based on the larger of R ₁ and R ₂ . The selector 106 provides Z _L to the sum combiner 110 and the difference coupler 112. Combiners 110 and 112 add Z _L to the two lookup table outputs F (Z) and F (Z + π) to produce a difference output log and a sum output log associated with the two input complex numbers, Perform a complex butterfly in one operation.

Butterfly operations are often useful for performing the Fast Fourier Transform (FFT), which is required for various signal processing operations such as Orthogonal Frequency Division Multiplex (OFDM) signal decoding. For base 2 FFT operations, it is common to change the phase angle in multiples of 2π / 2 ^N , where 2 ^N is the magnitude of the FFT. In logpolar format, the phase rotation operations, known as twiddles, are trivial and only include adding multiples of quantities equal to 0.0001000 to the phase portion. Since it is easy to change the phase angle in the butterfly circuit 100, very efficient butterfly and tweets may be implemented by applying complex numbers expressed in logpolar format to the butterfly circuit 100, which is very beneficial to the FFT. . As long as the FFT is base 2 and N is less than or equal to the word length of θ, no rounding takes place. For FFTs other than base 2, a special logpolar format may be devised, where θ is expressed using the same roots as the FFT base. The algorithm described herein can be used in the device by suitably applying lookup tables.

FIG. 7 illustrates an implementation of an example 16-point FFT using the multiple complex butterfly circuit 100 shown in FIG. 6. The butterfly circuit 100 combines eight pairs of values selected in a 16-element array. The selected sum and difference outputs are changed in each part to affect the complex rotation known as the tweens. The angles are changed by modulo-2π addition of the shown bit patterns. As shown, when 7-bit respective parts are used, the modulo-2π addition is simply a modulo-128 addition. The FFT may be implemented using 8 × 4 = 32 copies of the butterfly circuit 100 for the total parallel processing and calculation of the complete FFT per machine cycle. In addition, the FFT may be implemented using eight butterfly circuits 100 in a single row in succession to implement each of the four computation columns. In addition, the single butterfly circuit 100 can be used repeatedly 32 times for FFT execution. The options depend on the desired tradeoff between speed and size or cost.

The advantage of logpolar quantization over the Cartesian representation of complex values can be realized by considering the problem of representing the signal as much as 1% when the signal can appear anywhere in the 60 dB dynamic range. This may occur in receivers for burst-mode transmission providing a receiver without warning about the expected signal level. To represent the Cartesian parts by about 1%, if the minimum signal level is approximately 1, a minimum step of approximately 1/64 is required, which is 6 bits to the right of the binary decimal point. However, in order to represent the signals over 60 dB, it is necessary to represent the signals 1000 times larger than in the case of requiring an additional 10 bits to the left of the binary decimal point. The real part and the imaginary part need to have a format of S10.6, which totals 34 bits. However, as described above, the same degree of quantization and dynamic range are achieved using only 16 bits in logpolar format.

If higher accuracy is required than can be achieved with a single lookup table of suitable size, the two-table iteration method described above for real numbers can be applied for complex numbers. Suitable complex formats within the 32-bit word length of the high accuracy real format are, for example,

(0.xxxxxxxxxxxxxxx; xxxxx.xxxxxxxxxxxx)

Or simply in phase priority format (0.15; 5.12). Selecting two or three more bits of the phase than the number of bits to the right of the binary decimal point of log size results in smaller quantization errors for phase and amplitude. The least significant bit of the 15 bit phase has a value of 2π × 2 ⁻¹⁵ = 6.28 × 2 ⁻¹⁵ . The change in the 12th binary position of R = log (r) results in d (log (r)) = dr / r = 2 ^-12 = ^{8x2 -15} .

Thus, the least significant bit of log (r) is a radial displacement that is slightly larger than the displacement of one least significant bit of tangential direction θ. Using a bottom 2, the log (r) the least significant bit is reduced by a log _e (2) = 0.69 to 5.54 × 2 ^-15 slightly smaller than one least significant bit of the θ. If important, exactly the same emission and tangential quantization can be achieved with a special base between e of 2 and e ^{π / 4} = 2.19328. However, Base 2 has implementation advantages and is desirable. For example, using base 2, the log size of format 5.12 represents signal levels with a 32 × 6 = 192 dB dynamic range, which is twice the range of the 16-bit format. Quantization noise is greater than 80 dB below signal level for all signal levels. This is more than suitable for wireless signal processing in normal applications and is also useful for simulation when it is required to ensure that the quantization effects can be ignored, and interference cancellation with excessive differences between undesired large and small desired signals. It can also be useful for major applications such as:

When two logpolar values are log-added or log-subtracted, the result is a value with a larger log size so that the difference between log sizes is large enough that the least significant bit or θ of log (r) is not affected. Thus, if R ₁ and R ₂ are log sizes of _two logpolar values Z ₁ and Z ₂ , and R is the difference between R ₁ and R ₂ , and is always positive, then when R is greater than 13 log _e (2) = 9.011 , function

Are 0 to 12 binary positions.

Therefore, only the values of the difference of log sizes R of 0 to 9 need to be considered if base e for the 32 bit logpolar format. Similarly, in the base 2 case, only values of log size differences of 0 to 13 need to be considered as arguments of the complex logadd / sub function. Thus, the left 4 bits of the binary decimal point are sufficient to represent R, so that R becomes form 4.12.

Since the complex logadd / logsub function for negative θ is a conjugate of the complex logadd / logsub function for positive θ, θ can be limited to a range of values less than 0 to π, with only 14 variable bits It has the form 0.0xxxxxxxxxxxxxx. During the study leading the invention, it was found that the problem of convergence due to complex iterations was very solved by excluding the special value of π = 0.10000000000 ... for each difference. The value is exactly equal to the actual subtraction of the log sizes, the resulting angle is one of the two input argument angles, and is best executed using the F _s function in the actual operation.

In real numbers, the iterative process for complex numbers involves dividing the difference Z = (θ, R) = Z ₁ -Z ₂ of the two factors Z ₁ and Z ₂ to be combined first into the most significant part and the least significant part. do. As mentioned above, the value of Z actually requires only 30 variable bits. For example, let Z _{M be} the least significant 7 bits of the 14 variable bits of θ and the most significant 8 bits of 16 bits R, ie, Z _M = (0.0xxxxxxx; xxxx.xxxx) in the phase-first notation.

Z _L is the remaining least significant 8 bits of R and the least significant bits of seven θ, with the format Z _L = (0.00000000xxxxxxx; 0000.0000xxxxxxxx). Then define Z _M ⁺ = Z _M + dZ. Here, dZ has a real part of 0.0001 or 0.000011111111 and an imaginary part of 0 or 0.111111111111111, that is, 1 LSB smaller than 2π. After that, Z _L ^- is defined as Z _M ⁺ -Z. In the case of electronic selection for dZ, Z _L ^- is the two's complement of the variable bits of Z _L , and in the case of the latter selection for dZ, the complement of the bits. Since the repair is easier than 2's repair, the latter selection of the real and imaginary parts of dZ is preferred.

)는 R의 8개의 최상위 비트 및 θ의 7개의 최상위 비트에만 좌우되기에, 미리 계산되어 Z_M에 의해 직접 어드레스되는 32,768-워드 테이블에 저장될 수 있다. 따라서, 프로세싱 중에 Z_M ⁺를 형성할 필요가 없다.Function log _e (1-

) Depends only on the eight most significant bits of R and the seven most significant bits of θ and can be stored in a 32,768-word table that is precomputed and directly addressed by Z _M. Thus, there is no need to form Z _M ⁺ during processing.

)는 R의 7개의 최상위 비트 및 θ의 8개의 최상위 비트에만 좌우되고, 미리 계산되어 복소수 연산을 위한 G-함수를 32,768-워드 룩업테이블로서 저장될 수 있다. 후자는 연속 값들 Z', Z", Z'" 등을 계산하는데만 필요하며, 희망 결과는 보다 큰 로그크기, Z₁ 또는 Z₂를 갖는 고유 인수와 인수들, Z_M, Z'_M, Z"_M 등을 갖는 일련의 F-함수 값들의 합이다. 연구에 의해, 수렴을 위해 필요한 복소수 로그애드/로그서브 반복은 최대 6회 반복임이 입증되었고, 최악의 경우는 Z₁ 및 Z₂의 각들이 거의 180도 떨어져 있으며, 그 크기들이 거의 동일한 경우이다. 상술된 바와 같이, 정확히 180도 떨어진 각들의 경우는 연산을 실수 감산으로 처리함으로써 해결된다.Function -log _e (1-

) Depends only on the seven most significant bits of R and the eight most significant bits of θ and can be precomputed to store the G-function for complex arithmetic as a 32,768-word lookup table. The latter is only necessary to calculate the continuous values Z ', Z ", Z'", etc., and the desired result is a unique argument and arguments with a larger log size, Z ₁ or Z ₂ , Z _M , Z ' _M , Z "Is the sum of a series of F-function values with _M, etc. Studies have shown that the complex logad / logsub iterations required for convergence are up to six iterations, with the worst case being each of Z ₁ and Z ₂ . Are nearly 180 degrees apart and their sizes are almost the same, as described above, the case of angles exactly 180 degrees is solved by treating the operation with real subtraction.

In order to accommodate both real and complex operations in the same F-table, two extra address bits may be provided for selecting a table for real addition, a table for real subtraction and a table for complex addition / subtraction. . The function may be denoted by F (r _m , opcode), where r _M is 14 of the 15 bits of the argument in the complex case and the 15th bit is part of the 2-bit opcode. Two bit opcodes are allocated as shown in the following table:

00 Mistake addition 01 Mistake subtraction 1x Complex addition / subtraction, where x is the 15th bit of the main argument

)는 Z_L의 15비트에만 좌우되어서, 미리 계산되어 Z_L ^-에 의해 직접 어드레스되는 룩업 테이블에 저장될 수 있다. 크기 및 함수는 실 수 연산들을 위한 G-테이블과 같게 하고, 절반인 적합한 32,768-워드를 선택하기 위해 실수에 대해서는 0이고 복소수에 대해서는 1인 "opcode" 인수를 도입함으로써 65,536-워드 룩업 테이블에서 실수 G-테이블과 결합될 수 있다. Similarly, the function log _e (1-

) Depends only on the 15 bits of Z _L and can be precomputed and stored in a lookup table addressed directly by Z _L ⁻ . The magnitude and function are the same as the G-table for real operations, and the real in the 65,536-word lookup table by introducing an "opcode" argument of 0 for real and 1 for complex numbers to select a suitable 32,768-word that is half. Can be combined with a G-table.

By dividing the complex input into the top and bottom parts, the same principles as used to perform log operations on real numbers using a two-table iteration process can be applied to complex numbers represented in log format. In addition, by dividing the complex input into the top and bottom portions, the complex numbers described in co-pending US patent application Ser. No. _______ (Delegation Document No. 4015-5287) in logpolar format are represented. Can be applied to The co-pending application is incorporated herein by reference. In the pipeline of a co-pending application, the ALU stores the selected portion of the lookup table of each stage of the pipeline. At least one stage of the pipeline executes selected portions of the lookup table using stage inputs expressed in logpolar format to produce partial output associated with the stage. By combining the partial outputs, the multistage pipeline produces log output.

It can be seen that when θ = π, the operation is equivalent to real subtraction. In this case, the result depends only on R. Special lookup tables can be used in one-shot operations. In addition, an existing lookup table for real subtraction can be used. It uses the 14-bit 0xxxx.xxxxxxxxx of R to address the F _s portion of the F-table, and executes the real subtraction algorithm using the remaining 3 bits of R extended to 12 zeros, the initial value of R _L. Can be achieved. Real iterations are then performed by accumulating only the desired bits of the accuracy of the output register corresponding to the reduced complex accuracy, and using termination criteria faster than R> 18. For example, R> 9 may be sufficient.

Common ALU for Real and Complex Logarithm Operations

Complex numbers and real numbers can be used to represent various signals in a single system. Conventional processors may include separate ALUs-one for implementing complex logarithm operations and the other for implementing real logarithm operations. However, two separate ALUs occupy considerable silicon space. In some instances, ALUs may require incredibly large lookup tables. Thus, it is beneficial to have a single ALU that implements both real and complex logarithm operations with reasonable size lookup tables.

8 illustrates an example ALU 200 for performing both real and complex logarithm operations. The ALU 200 includes an input accumulator 210, a lookup controller 220 and an output accumulator 230. In general, the input accumulator 210 calculates the difference between two real or complex inputs, and the lookup controller 220 and the output accumulator 230 together input using a real lookup table or a complex lookup table depending on the input. An output log is generated based on the real or complex output of the accumulator 210.

Two real or complex numbers A and B, represented in the log format being added or subtracted, are provided in succession to the input accumulator 210. When the strobe pulse first occurs, the ALU 200 loads the first number A into the input accumulator 210 and the output accumulator 230. Thereafter, a second number B having an associated sign changed 180 degrees for each portion θ and subtraction is provided to the input accumulator 210.

When the strobe occurs a second time, the input accumulator 210 subtracts B from A. If there is an underflow indicating that the log size of B is greater than the log size of A, then the input accumulator 210 stores and outputs the value X = B-A, and sends a straight pulse to the output accumulator 230. The right pulse causes the output accumulator 230 to load B, including associated or unchanged associated signs (or angles in the case of complex numbers) and overwriting A. However, if there is no underflow, the input accumulator stores and outputs the value X = A-B. Accordingly, the output accumulator 230 maintains a larger value of A and B, and the input accumulator 210 maintains | A-B |. The amount X is equal to the amount r of the above-described equations for real numbers and equal to the amount Z of the above-described equations for complex numbers.

Based on X, lookup controller 220 determines two outputs, a partial output L and a correction output Y. The lookup controller 220 outputs the partial output L to the output accumulator 230 with the ADD pulse, so that the partial output L is accumulated with the existing content of the output accumulator 230. The lookup controller 220 outputs the corrected output Y to the input accumulator 210 with the ADD pulse, so that Y is accumulated with the existing content of the input accumulator 210, thereby generating a new X value. The cycle is repeated until Y satisfies or exceeds the predetermined value. If Y satisfies or exceeds the predetermined value, the cycle stops, and the lookup controller 220 generates a READY signal from the output accumulator 230 as output C indicating that the desired response is valid, The state is returned to its initial state, waiting for the input values of a new pair of A and B.

9 shows additional details of one example lookup controller 220 for real or complex logarithm operations. The lookup controller 220 includes an F-table 222, a G-table 224, a combiner 226, and a sequencer 228. F-table 222 and G-table 224 include a complex lookup table for determining a complex number of logs and / or a real lookup table for determining a real number log. Although the F-table 222 and G-table 224 shown in FIG. 9 include both complex and real lookup tables, those skilled in the art will appreciate that the F-table 222 and / or G-table ( It will be appreciated that 224 may include only one of a complex lookup table and a real lookup table.

As the first 32 bit log amount A is applied to accumulators 210 and 230, the starting strobe is applied to sequencer 228. Sequencer 228 provides a load 1 pulse to input accumulator 210 and a load 2 pulse to output accumulator 230 to store a 32 bit A-quantity. As the second 32 bit log amount B is applied to the accumulators 210 and 230, a second strobe is applied to the sequencer 228.

Sequencer 228 provides an accumulating pulse to input accumulator 210. When the input accumulator 210 outputs a "barrow" pulse indicating that the log size of B is greater than the log size of A, the sequencer 228 outputs another load 2 pulse to the output accumulator 230 to output the accumulator 230. In B, a B value containing the number B sign or phase is stored, and A is overwritten. For real numbers, the sign of the value with the larger log size becomes the sign of the result C. The input accumulator 210 outputs the value of the difference X between the log sizes, where A is larger, X = A-B, and B is larger, X = B-A. Thus, X is always positive. The uppermost part of X, X _M , is applied to F lookup table 222, and the lowermost part of X, X _L is applied to G lookup table 224.

For real numbers, the sign logic portion of input accumulator 210 XORs the signs of numbers A and B, such that the F _a portion of lookup table 222 is used (the same signs mean addition) or F _s is used. Determines whether different symbols mean subtraction. The XOR of the signs forms an extra address bit in the F-table 222.

If the value X of the input accumulator 210 does not exceed the stop threshold, no stop pulse is provided to the sequencer 228, and the sequencer continues to transmit the accumulate pulse to the input accumulator 210 and the output accumulator 230, The value F + G from the combiner 226 is accumulated in the input accumulator 210, the partial output L is accumulated in the output accumulator 230, and the content and correction output of the input accumulator 210 are accumulated.

This is repeated until the output accumulator 230 indicates whether the content satisfies or exceeds the stop threshold by providing a " stop " pulse to the sequencer 228, when the " stop " pulse is provided. ) Generates a " ready " pulse indicating that the value C of the output accumulator 230 is the final result and returns to the start state.

In the apparatus of FIG. 9, the F _s portion of the lookup table 222 stores suitably accumulated negative values in the accumulators 210 and 230 without separately indicating whether a log addition or log subtraction operation is in progress. Alternatively, to store the sign bits of all F _s , they may be omitted from the lookup table, and the values of the +/− bits provided from the sign logic may be used, where all F _a values are positive and all F _s values are negative. . Storing a negative value F _s that is less than the sign bit is different from negating the value and storing a positive value, which must later be subtracted from output accumulator 230 and combiner 226. When lookup table size compression is considered, it will be appreciated that the latter is beneficial. Lookup table compression is further described in US Patent Application Serial No. _______ (Delegation Document No. 4015-5288), which is incorporated herein by reference.

Other changes that may be considered during implementation cause the output accumulator Y of the combiner 226 to be negative of F + G so that it can be subtracted from the input accumulator 210, thereby allowing the input accumulator 210 to differentiate the add and subtract commands. Don't have to. Since the negative number is complement + 1, this can be achieved using the complement outputs, storing the G-table 224 values all reduced by one least significant bit. However, in order for the G-table 224 to be generally useful for other scenarios, it is desirable that the values of the G-table 224 remain unchanged.

10 illustrates in more detail the complex operation of the ALU 200. For complex values, the input accumulator 210 includes two independent portions, the R-section 210A and the θ-section 210B. If the carry output from the θ-part 210B is prevented from being passed to the R-part 210A, the same input accumulator 210 as used for the real number operation can be used for the complex operation, in the case of θ priority bit order. The reverse is true.

It is important that the bits addressing the complex F-tables 222 come from θ in part and from R in part. If θ occupies the position occupied by the LSB of R in case of a real number, the connections between the input accumulator and the F-table 222 must be changed for complex computation. This is also true for the G-table 224. This can be implemented inconveniently with a selector switch set (not shown) that selects the appropriate bits from the input accumulator 210 to connect to address the inputs of the G-table and F-table independently of real and complex operations. have. Other solutions may be considered: The connections between the input accumulator 210 and the F and G tables may remain the same for real and complex operations, which requires interleaving the allocation of bits to R and θ. . Thus, the most significant bit of θ exchanges positions with the least significant bit of R in the implementation so that if the most significant bit of R and θ is real, it occupies bit positions occupied by the most significant bit of R, and the least significant bit of R and θ is real Occupies bit positions occupied by the least significant bit of R; In order to maintain the R bits connected to form R-adder 226A and the θ bits for forming independent θ-adder 226B, the carry bits of the three adder stages need to be routed again for complex numbers compared to real numbers. There is. When achieved, output accumulator 230 and adder 226 are similarly configured to prevent intersection of connections from real to complex numbers. This ensures that the output bits of the F and G-tables remain connected to the same lines in adder 226 and accumulator 230.

When θ = π, if it is desired to use the real subtraction table F _s for the complex case, the above alternative is less practical. In this case, all bits of R are connected to the address input of F-table 222, and likewise, it is necessary to connect all bits to the R-adder portions of accumulator 230 and adder 226. In this case, it is difficult to prevent the use of rerouting switches again. If the θ = π case is processed without repetition, that is, by a single lookup of the real F _s -table 222, the rerouting of the adder bits is prevented.

Another bit alignment processed using the real subtraction table for the complex θ = π case is one less in number (4 bits) for complex numbers than the real number (5 bits) to the left of the binary decimal point. In addition, real repetition uses, for example, an F-table 222 addressed by the most significant bit of the form 5.9, and a difference value of format 4.12 that requires tables of different sizes to process complex θ = π without repetition. It is necessary to address the F-table 222 with a total of 16 bits of R.

11 illustrates different possible bit allocations of real and complex numbers. 11A shows the linear assignment of bits 1 to 32 starting from the sign bit S of position 1 and leading to the 31-bit log size of format 8.23, and splitting into the most significant portion X _M of format 5.9 and the least significant portion X _L of format 0.14. Illustrated. Shown below is the linear assignment of bits 1 to 32 to the log amplitude of format 5.12 and the phase angle of format 0.15, the division of the log amplitude into the highest part R _M and the least significant 8 bits R _L of format 4.4, with the phase It is divided into 7 bit top and bottom parts, with the bit corresponding to π separately shown. Many misalignments between real and complex numbers are apparent from FIG. 11A. For example, the binary size of the log size is not in the same position, and the bits addressing the F-table 222, X _M for real numbers, R _M and θ _M for complex numbers are not the same bits.

11B shows the bit allocation where the binary decimal points are aligned for real and complex log sizes, respectively. This is only _a concern when attempting to reuse the real F _s -table 222 for a complex case where θ = π and attempting to reuse the real F _a -table 222 for a complex case where θ = 0. The bits addressing the F and G tables are still different for real and complex numbers.

11C shows the bit allocation to achieve the same bits addressing the F-table 222 for both real and complex numbers. The sign bit S and the most significant part X _M are placed contiguously to address the F _a and G tables for real arithmetic, so that the 15 bit addresses are together, and in the case of complex numbers the same 15 bits represent 8 bit R _M and 7 bit θ _M Include.

Similarly, 15 bits consisting of R _L and θ _L overlap the 14 bits of X _L and address the G-table 224 ROM. In case of a mistake, the number of bits 2 is ignored when addressing the real G-table 224, which is half the size of the complex table. 11C shows that the bit order within the top and bottom portions is arbitrary, but may be selected to maximize the number of carry connections from one adder stage to the next, and does not change between real and complex operations. It is important to stay with.

The simple solution does not attempt to combine the complex and real F-tables 222 into one large table that must use the same address bits, but rather a suitable address selected from the input accumulator 210 for real and complex cases differently. You must use separate tables linked to bits. In addition, separate address-decoders can be used for real and complex numbers. Similarly, G-table 224 for real and complex numbers may be different tables or at least different address decoders. The total size remains the same as the combined tables, unlike other considerations, such as when θ = π. The case where θ = π is only a problem when the log amplitudes are nearly equal, i. Therefore, it needs to be treated as a special case only for R values such as 0000.xxxxxxxxxxxx or 0.12, ie only when the most significant 4 bits of the difference R are zero. It only requires a 4096-word table, which needs to avoid the complexity of bit line rerouting so that the real F _s -table 222 can be used. If the lookup tables occupy the largest proportion of the silicon chip area and the chip area occupied by accumulators, adders and other peripheral logic is small, the conclusion is that separate implementations of real and complex algorithms can be logical, and the resulting processor It has the advantage that it is possible to execute real and complex operations simultaneously with increased processing speed.

The invention can of course be implemented in other ways not specifically described herein within the essential features of the invention. The present embodiments are to be considered as illustrative and not restrictive, and all changes that come within the meaning and range of equivalency of the appended claims are embraced within the invention.

Claims (48)

ALU for calculating the output log, A memory for storing a first lookup table for determining a log of real numbers and a second lookup table for determining a log of complex numbers; And A shared processor for generating an output log based on two input operands expressed in log format using the first lookup table for real input operands and the second lookup table for complex input operands ALU comprising a. The method of claim 1, The output log is an ALU representing a log of the sum or difference of the input operands. The method of claim 1, Wherein the ALU comprises a butterfly circuit configured to simultaneously generate a log of the difference between the input operands and a log of the sum of the input operands using the first lookup table or the second lookup table. The method of claim 3, wherein The butterfly circuit, A first combiner for combining the selected input operand with the difference value provided by the first or second lookup tables to produce a log of the difference between the input operands; And A second combiner for combining the selected input operand with the sum value provided by the first or second lookup tables to produce a log of the sum of the input operands; ALU comprising a. The method of claim 1, The shared processor, A lookup controller configured to calculate one or more partial outputs based on the first or second lookup tables; And An output accumulator configured to generate the output log based on the partial outputs ALU comprising a. The method of claim 5, The number of partial outputs used to generate the output log is based on the desired accuracy of the output log. The method of claim 5, Wherein the shared processor executes two or more iterations through the lookup controller to determine the output log, each iteration producing one of the partial outputs. The method of claim 7, wherein And an input accumulator configured to generate a real or complex input for the current iteration based on the partial output generated during a previous iteration. The method of claim 7, wherein And the output accumulator generates the output log based on the partial outputs generated during each iteration and a selected input operand. The method of claim 9, The shared processor further comprises a selection circuit configured to select an input operand having a maximum magnitude. The method of claim 5, The lookup controller comprises a multistage pipeline, each stage of the multistage pipeline producing one of the partial outputs. The method of claim 11, Each stage of the pipeline storing a selected portion of the first and second lookup tables. The method of claim 12, At least one stage of the pipeline executes a selected portion of the first lookup table using a real stage input or a selected portion of the second lookup table using a complex stage input, thereby performing ALU to generate one. The method of claim 1, Wherein each of the complex input operands comprises a magnitude portion and a phase portion. The method of claim 14, Further includes an input accumulator, The input accumulator is A magnitude accumulator for generating a magnitude portion of the complex input based on the magnitude portions of the complex input operands; And And a phase accumulator that generates a phase portion of the complex input based on the phase portions of the complex input operands. A method of calculating the output log in the ALU, Storing a first lookup table for determining a log of mistakes; Storing a second lookup table to determine a complex number of logs; And Generating an output log based on two input operands expressed in log format in a shared processor using the first lookup table for real input operands and the second lookup table for complex input operands Output log calculation method comprising a. The method of claim 16, And generating the output log based on two input operands comprises generating the output log based on the sum or difference of the input operands. The method of claim 16, Generating the output log based on two input operands may include simultaneously generating an output log of the difference between the input operands and an output log of the sum of the input operands using the first or second lookup tables. Including output log calculation method. The method of claim 18, Simultaneously generating the output log, Selecting an input operand based on a comparison between the input operands; Combining the selected input operand with the difference value provided by the first or second lookup tables to produce an output log of the difference between the input operands; And Combining the selected operand with the sum value provided by the first or second lookup tables to produce an output log of the sum of the input operands. The method of claim 16, Generating an output log based on two input operands, Calculating one or more partial outputs based on the first or second lookup tables; And Generating the output log based on the partial outputs. The method of claim 20, Executing at least two iterations to determine the output log, each iteration producing one of the partial outputs. The method of claim 21, Generating an input for a current iteration based on the partial output generated during a previous iteration. The method of claim 20, Generating an output log based on the partial outputs comprises generating the output log based on partial outputs generated at each stage of a multi-stage pipeline. The method of claim 23, wherein Storing the selected portion of the first and second lookup tables at each stage of the multi-stage pipeline. The method of claim 24, Outputting at least one stage of the pipeline, respectively, executing selected portions of the first or second lookup tables based on real or complex stage inputs to produce one of the partial outputs. Calculation method. The method of claim 16, And said complex input operands each comprise a magnitude portion and a phase portion. The method of claim 26, Generating a magnitude portion of the complex input based on the magnitude portions of the complex input operands; And Generating a phase portion of the complex input based on the phase portions of the complex input operands Output log calculation method further comprising. ALU for calculating the complex output log, A memory for storing a lookup table for determining a log of complex numbers; A processor for generating an output log of arithmetic combining of complex input operands expressed in logpolar format using the stored lookup table ALU comprising a. The method of claim 28, The processor includes a butterfly circuit configured to simultaneously generate an output log of the difference between the complex input operands and an output log of the sum of the complex input operands based on the lookup table. The method of claim 29, The butterfly circuit, A first combiner for combining the selected input operand with the difference value provided by the lookup table to produce an output log of the difference between the complex input operands; And A second combiner for combining the selected input operand with the sum value provided by the lookup table to produce an output log of the sum of the complex input operands ALU comprising a. The method of claim 28, The processor, A lookup controller configured to calculate one or more partial outputs based on the lookup table; And An output accumulator configured to generate the output log based on the partial outputs ALU comprising a. The method of claim 31, wherein The processor, An at least two iterations through the lookup controller to generate the output log, each iteration generating one of the partial outputs. 33. The method of claim 32, And an input accumulator configured to generate a complex input for the current iteration based on the partial output generated during a previous iteration. The method of claim 31, wherein The lookup controller comprises a multistage pipeline, wherein each stage of the multistage pipeline generates one of the partial outputs. The method of claim 28, Wherein the complex input operands comprise a magnitude portion and a phase portion. 36. The method of claim 35 wherein Further includes an input accumulator, The input accumulator is A magnitude accumulator for generating a magnitude portion of the complex input based on the magnitude portions of the complex input operands; And And a phase accumulator that generates a phase portion of the complex input based on the phase portions of the complex input operands. 36. The method of claim 35 wherein Wherein the phase portion comprises a most significant portion of the complex input and the magnitude portion comprises a least significant portion of the complex input. The method of claim 37, Wherein the lookup table comprises a magnitude lookup table and a phase lookup table. The method of claim 38, The most significant portion of the complex input addresses the phase lookup table, and the least significant portion of the complex input addresses the magnitude lookup table. As a method of calculating a complex output log, Storing a lookup table for determining a complex number of logs represented in a logpolar format; And Generating an output log based on the complex input operands expressed in log polar format using the stored lookup table Output log calculation method comprising a. The method of claim 40, Generating the output log based on the complex input operands includes simultaneously calculating an output log of the difference between the complex input operands and an output log of the sum of the complex input operands based on the lookup table How to calculate the log. The method of claim 40, Generating the output log, Calculating one or more partial outputs based on the lookup table; And Generating the output log based on the partial outputs Output log calculation method comprising a. The method of claim 42, wherein Generating at least two iterations to generate the output log, wherein each iteration generates one of the partial outputs. The method of claim 43, The generating of the output log includes generating the output log by executing a multi-stage pipeline, wherein each stage of the multi-stage pipeline generates one of the partial outputs. The method of claim 40, Generating a magnitude portion of the complex input based on the magnitude portions of the complex input operands; And Generating a phase portion of the complex input based on the phase portions of the complex input operands Output log calculation method further comprising. The method of claim 45, Wherein the phase portion comprises a most significant portion of the complex input and the magnitude portion comprises a least significant portion of the complex input. 47. The method of claim 46 wherein Wherein the lookup table comprises a magnitude lookup table and a phase lookup table. The method of claim 47, Addressing the phase lookup table using the most significant portion of the complex input, and addressing the magnitude lookup table using the least significant portion of the complex input.

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