KR20070016514A - NAND flash memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND flash memory device, and is a technique for reducing parasitic capacitance between adjacent floating gates by forming an active region or a control gate line in a wave form.

Wave form, control gate line, active area, parasitic capacitance

Description

NAND flash memory device

1 is a plan view of a NAND flash memory device according to the prior art

2 is a plan view of a NAND flash memory device according to an embodiment of the present invention.

3 is a plan view of a NAND flash memory device according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

20 semiconductor substrate 21 active region

22: floating gate 23: control gate line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to NAND flash memory devices, and more particularly to NAND flash memory devices suitable for reducing parasitic capacitance between floating gates.

1 is a plan view of a NAND flash memory device according to the prior art.

In the NAND flash memory device according to the related art, as illustrated in FIG. 1, the semiconductor substrate 10 includes stripe-type active regions 11 aligned in a bit line direction. Striped control gate lines 13 pass through the semiconductor substrate 10 in a word line direction perpendicular to the bit line. The semiconductor substrate 10 except for the active region 11 corresponds to a field region.

The floating gates 12 are positioned on the active regions 11 below the control gate lines 13. In order to improve the coupling ratio, the floating gates 12 may be extended not only above the active region 11 but also above the field region under the control gate lines 13.

Although not shown in the drawings, a tunnel oxide film is positioned between the floating gate 12 and the active region 11, and an oxide having an oxide Nitride Oxide (ONO) structure between the floating gate 12 and the control gate line 13. The film is interposed.

As the degree of integration of the device increases, the distance between the floating gates 12 decreases, thereby increasing the capacitance between neighboring floating gates 12.

As a result, the operation speed of the program using the Increment Step Pulse Program (ISPP) is reduced, the performance of the device is lowered, and the interference effect is increased.

An interference effect is that when a cell immediately adjacent to a cell to be read is programmed, the adjacent cell is adjacent to the cell during a read operation due to a charge change of the floating gate of the cell. This refers to a phenomenon in which a threshold voltage higher than the actual cell threshold is read due to the capacitance action of a programmed cell. The charge itself of the floating gate of the leading cell does not change, but the change in the state of the adjacent cell is immediately changed. As a result, the actual cell state is distorted.

This distortion causes wide cell distribution, which makes it difficult to control the cell state. In particular, the effect is enormous in a multi level cell (MLC) having a small cell distribution margin compared to a single level cell (SLC). Therefore, in order to improve cell uniformity, it is necessary to reduce the interference effect.

Accordingly, an object of the present invention is to provide a NAND flash memory device for reducing parasitic capacitance between adjacent floating gates.

Another object of the present invention is to reduce the cell distribution and improve the operation speed by reducing the interference effect between adjacent floating gates.

Another object of the present invention is to facilitate the manufacture of multi-level cells.

A NAND flash memory device according to an embodiment of the present invention includes a semiconductor substrate, active regions in wave form formed on the semiconductor substrate and aligned in a bit line direction, and aligned in a word line direction perpendicular to the bit line direction. And control gate lines passing over a portion where the wave-shaped active region is bent, and floating gates positioned on the active regions below the control gate lines.

A NAND flash memory device according to another exemplary embodiment of the present invention may include a semiconductor substrate, wave shaped control gate lines formed on the semiconductor substrate and aligned in a word line direction, and formed on the semiconductor substrate and in the word line direction. Active regions aligned in a bit line direction perpendicular to the second line and passing below the bending portion of the control gate lines, and floating gates positioned on the active regions below the control gate lines.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2 is a plan view of a NAND flash memory device according to an embodiment of the present invention.

According to FIG. 2, active regions 21 are formed in a wave shape in the bit line direction on the semiconductor substrate 20, and freezes on the semiconductor substrate 20 in a word line direction perpendicular to the bit line direction. The stripe-patterned control gate lines 23 pass over a portion where the active regions 21 are bent. The semiconductor substrate 20 except for the active region 21 corresponds to a field region.

In addition, the floating gate 22 is positioned on the active region 21 under the control gate lines 23. Since the active region 21 has a wave shape, the floating gates 22 adjacent to each other in the bit line direction are viewed obliquely without facing the front.

In order to improve the coupling ratio, the floating gate 22 may be extended not only above the active region 21 but also above the field region under the control gate line 23.

Although not shown in the drawings, a tunnel oxide film is positioned between the active region 21 and the floating gate 22, and a dielectric film is interposed between the floating gate 22 and the control gate line 23.

If the active regions 21 are configured in a wave form and the floating gate 22 is formed at each of the portions where the active regions 21 in the wave form are bent, the floating gate 22 neighboring in the bit line direction is formed. The interspace increases to d2, while the overlap area between the floating gates 22 is reduced. Therefore, parasitic capacitance between the floating gates 22 is reduced, so that the interference effect is improved.

3 is a plan view of a NAND flash memory device according to another exemplary embodiment of the present invention. The NAND flash memory device illustrated in FIG. 2 has a wave-shaped active region, and the active region is formed in a stripe shape and the control gate line is formed. In the case of a wave form.

According to FIG. 3, wave-shaped control gate lines 23 are formed on the semiconductor substrate 20 in a word line direction, and the semiconductor substrate 20 is aligned in a bit line direction perpendicular to the word line direction. The active regions 21 of the stripe pattern pass under the portion where the control gate lines 23 are bent. The semiconductor substrate 20 except for the active region 21 corresponds to a field region.

The floating gates 22 are positioned on the active region 21 under the control gate lines 23. In order to improve the coupling ratio, the floating gate 22 may be extended not only above the active region 21 but also above the field region under the control gate line 23.

Although not shown in the drawings, a tunnel oxide film is positioned between the active region 21 and the floating gate 22, and a dielectric film is interposed between the floating gate 22 and the control gate line 23.

When the control gate lines 23 are configured in a wave shape as described above, parasitic capacitance between the floating gates 22 adjacent to each other in the word line direction is reduced to reduce the interference effect.

As described above, the present invention has the following effects.

First, since parasitic capacitance between neighboring floating gates can be reduced, interference effects can be improved.

Second, since the interference effect is improved, the program speed of the device can be improved.

Third, the cell distribution can be reduced because the interference effect is improved.

Fourth, the cell distribution can be reduced, making it easier to manufacture multi-level cells.

Claims (6)

A semiconductor substrate, Active regions formed in the semiconductor substrate in a wave form aligned in a bit line direction; Control gate lines aligned in a word line direction perpendicular to the bit line direction and passing over a portion where the wave-shaped active region is bent; NAND flash memory device including floating gates positioned on the active regions below the control gate lines. A semiconductor substrate, Wave-shaped control gate lines formed on the semiconductor substrate and aligned in a word line direction; Active regions formed in the semiconductor substrate and aligned in a bit line direction perpendicular to the word line direction and passing under a portion where the control gate lines are bent; NAND flash memory device including floating gates positioned on the active regions below the control gate lines. The method according to claim 1 or 2, A field region is formed in the semiconductor substrate except for the active region, and the floating gates extend over the field region below the control gate lines as well as the active region to overlap the field region at a predetermined width. Memory elements. The method according to claim 1 or 2, A tunnel oxide layer disposed between the active region and the floating gate; And a dielectric film interposed between the floating gate and the control gate line. The method of claim 1, The NAND flash memory device of claim 1, wherein the control gate lines have a stripe shape. The method of claim 2, And the active regions have a stripe shape.

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