KR20070016088A - Electro-optical device and electronic apparatus - Google Patents

Abstract

Provided is an electro-optical device having a structure capable of satisfactorily protecting an active element from static electricity, and preferably achieving an efficiency of the manufacturing process and an improvement in product ratio. An electro-optical device of the present invention is an electro-optical device having a display area 110 formed by arranging a plurality of pixels 19 in a matrix, and a switching element provided corresponding to each pixel 19. On the board | substrate 10, the 1st shield wiring part 91 which encloses at least 3 sides of the said display area 110, and the 2nd shield wiring part 92 which encloses the said 1st shield wiring part 91 are shown. Characterized in having a.

Description

ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS

1 is a diagram showing an overall configuration of a liquid crystal device according to Embodiment 1;

2 is a diagram showing the schematic and schematic circuit configuration;

3 is a diagram showing the details of the circuit configuration;

4 is a diagram illustrating a pixel configuration of a liquid crystal device;

5 is a view showing a cross-sectional structure along the line 'D-D' of FIG.

6 is a diagram showing an example of the configuration of an electrostatic protection circuit;

7 is a diagram showing another configuration example of an electrostatic protection circuit;

8 is a view showing a schematic circuit configuration of a liquid crystal device according to the second embodiment;

9 is a perspective configuration diagram showing an example of an electronic device.

Explanation of symbols for the main parts of the drawings

100: liquid crystal device (electro-optical device)

10: TFT array substrate (element substrate)

20: opposing substrate 50: liquid crystal

110: display area 9: pixel electrode

16: data line 18a: scan line

19: pixel 33: semiconductor layer

34 source electrode 35 drain electrode

60 TFT (switching element) 71 to 74 blackout protection circuit

71a: first MOS diode 71b: second MOS diode

91, 191 1st shield wiring part 92, 192: 2nd shield wiring part

193: third shield wiring portion

The present invention relates to electro-optical devices and electronic devices.

In an active matrix liquid crystal device (electro-optical device), a switching element is connected to each pixel electrode, and each pixel electrode is switched through the switching element. As the switching element, for example, a thin film transistor (TFT) is used. The structure and operation of the thin film transistor are basically the same as those of the MOS transistor of single crystal silicon. As a structure of a thin film transistor using amorphous silicon (a-Si), some structures are known, but a bottom gate structure (inverted staggered structure) in which the gate electrode is under the amorphous silicon film is generally used. It is used.

In manufacturing thin film transistors, it is important to reduce the number of manufacturing steps and to ensure a high product ratio. In addition, it is also important to effectively protect the thin film transistor from breakdown by static electricity generated during the manufacturing process of the active matrix substrate. Techniques for protecting thin film transistors from electrostatic destruction are described, for example, in Patent Document 1 below.

[Patent Document 1] Japanese Patent No. 2744138

According to the technique of the said patent document 1, it is thought that a thin film transistor can be protected from electrostatic destruction in a manufacturing process. However, static electricity is generated not only in the manufacturing process of the electro-optical device, but also in the process of mounting, conveying, packaging, etc. to the electronic device after manufacture, and may also occur in the use of the electronic device. Therefore, in order to secure the reliability of the electro-optical device, it is necessary to effectively protect from static electricity not only during the manufacturing process but also during its use.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art, and has an structure capable of satisfactorily protecting an active element from static electricity, and preferably has an electro-optical device capable of realizing an increase in production process efficiency and product ratio. It aims to provide.

In order to solve the said subject, the electro-optical device of this invention is an electro-optical device provided with the display area which arrange | positions a some pixel in matrix form, and the switching element provided corresponding to each said pixel, on an element substrate. And a first shield wiring portion surrounding at least three sides of the display area and a second shield wiring portion surrounding the first shield wiring portion.

According to this structure, since the switching element of the said display area is double-protected by the said 1st shield wiring part and the 2nd shield wiring part, the electro-optical device provided with the outstanding electrostatic resistance can be provided.

In the electro-optical device of the present invention, preferably, at least one of the first shield wiring portion and the second shield wiring portion is formed in a rectangular shape surrounding the display area. By arranging the display area in such a manner, the electrostatic resistance can be improved.

In the electro-optical device of the present invention, the first shield wiring portion and the second shield wiring portion can be configured to be electrically connected to a common electrode formed over the plurality of pixels. With such a configuration, an electro-optical device capable of flowing a surge through the common electrode power source can be configured.

In the electro-optical device of the present invention, a common electrode wiring electrically connected to a common electrode formed over the plurality of pixels is provided on the element substrate, and the common electrode wiring surrounds at least three sides of the display area. It can be set as the structure which forms the 3rd shield wiring part.

With such a configuration, since the display area is at least partially tripled, more excellent electrostatic resistance can be obtained.

In the electro-optical device of the present invention, the switching element includes a gate electrode formed on the element substrate, a semiconductor layer facing through the gate electrode and a gate insulating film, and a source / drain electrode electrically connected to the semiconductor layer. It is a thin film transistor provided, and it can also be set as the structure in which any one of the said 1st shield wiring part and the 2nd shield wiring part is formed in the same layer as the said source / drain electrode using the same material. With such a configuration, the shield wiring portion can be formed at the same time as the pixels in the display area, which is advantageous in terms of manufacturing efficiency and manufacturing product ratio.

In the electro-optical device of the present invention, either one of the first shield wiring portion and the second shield wiring portion may be formed in the same layer as the gate electrode using the same material. Also in this case, the shield wiring portion can be formed at the same time as the pixels in the display area, which is advantageous in terms of manufacturing efficiency and manufacturing product ratio.

In the electro-optical device of the present invention, a pixel electrode electrically connected to the switching element via the source / drain electrode is provided, and either one of the first shield wiring portion and the second shield wiring portion is connected to the pixel electrode. It can also be set as the structure formed in the same layer using the same material. Also in this case, the shield wiring portion can be formed at the same time as the pixels in the display area, which is advantageous in terms of manufacturing efficiency and manufacturing product ratio.

In the electro-optical device of the present invention, the first and second electrodes are electrically connected to the switching element via the source / drain electrodes, and the connection member is formed on the same layer as the pixel electrode by using the same material. At least two of the first to third shield wiring sections may be configured to be electrically connected to each other. With such a configuration, even if the shield wiring portion is formed in another wiring layer, it can be easily connected by the wiring member of the same layer as the pixel electrode, so that a path through which the surge flows can be easily formed.

In the electro-optical device of the present invention, a plurality of data lines and a plurality of scanning lines extending to cross each other are formed on the element substrate, and the pixels are provided corresponding to intersections of the data lines and the scanning lines, and the first It is preferable to set it as the structure in which the shield wiring part or the 2nd shield wiring part, and the said scan line or the said data line are electrically connected through at least one electrostatic protection circuit. With such a configuration, the switching element can be protected by an electrostatic protection circuit and the static resistance can be enhanced.

In the electro-optical device of the present invention, the electrostatic protection circuit can be configured to have a MOS diode having a semiconductor layer formed on the same layer as the thin film transistor. The first MOS diode and the second MOS diode formed by shorting the gate electrode and the drain electrode of the thin film transistor may be connected in opposite directions.

With these configurations, the electrostatic protection circuit can be formed at the same time as the pixel, and the electro-optical device excellent in manufacturing efficiency can be obtained.

In the electro-optical device of the present invention, a capacitor in which a source electrode and a gate electrode in the first MOS diode are overlapped in a planar manner, and a capacitor in which the source electrode and the gate electrode in the second MOS diode are partially overlapped in a plane. It is preferable that it is a coupled operation MOS diode. With such a configuration, the protection circuit can be operated at an early stage of the manufacturing process, more effectively preventing breakage of the switching element in the manufacturing process, and the ratio of the manufactured product can be improved.

In the electro-optical device of the present invention, it is preferable that the capacitive coupling operation type MOS diode is electrically connected to the shield wiring portion formed on the same layer as the data line. With such a configuration, the electrostatic protection circuit can be operated immediately after the data line is formed, thereby more effectively preventing damage to the switching element in the manufacturing process, and improving the manufactured product ratio.

The electronic device of the present invention includes the above-mentioned electro-optical device. According to this structure, the shield wiring part can protect a circuit of switching elements etc. from static electricity favorably, and can provide the electronic device provided with the display part excellent in reliability.

(Example 1)

1 is an overall configuration diagram of a liquid crystal device 100 which is an embodiment of the electro-optical device of the present invention, FIG. 1 (a) is a planar configuration, and FIG. 1 (b) is a line H-H 'of FIG. 1 (a). Fig. Is a cross-sectional configuration diagram.

As shown in FIG. 1, the liquid crystal device 100 has a structure in which a TFT array substrate (element substrate) 10 and an opposing substrate 20 are joined by a sealing member 52 having a substantially rectangular edge shape in plan view. The liquid crystal (electro-optic material) 50 which has and is hold | maintained between the said board | substrates 10 and 20 is sealed between the said board | substrates with the sealing material 52. As shown in FIG.

In the inner region of the sealing material 52, a light shielding film (hash treatment) 53 made of a light shielding material is formed in a rectangular frame shape. In the peripheral circuit region outside the sealing material 52, the data line driving circuit 101 and the mounting terminal 102 are disposed along one side of the TFT array substrate 10, and on this side, the data line driving circuit ( Scan line driver circuits 104 and 104 are provided on both sides of the 101.

On the inner surface side (liquid crystal 50 side) of the TFT array substrate 10, a plurality of pixel electrodes 9 are arranged in an array, and an alignment film (not shown) is formed to cover the pixel electrodes 9. The common electrode 21 of planar beta is formed in the inner surface side of the opposing board | substrate 20. As shown in FIG. An alignment film (not shown) is formed to cover the common electrode 21.

2 is a schematic circuit diagram showing the electrical configuration of the TFT array substrate 10. FIG. 3 is a circuit diagram illustrating the upper left portion of the schematic circuit diagram of FIG. 2 in more detail.

In the planar region of the TFT array substrate 10, a substantially rectangular display region 110 is formed in a plan view, and the display region 110 includes a plurality of pixels 19 arranged in a matrix in plan view. It is prepared. In the display area 110, a plurality of data lines 16 and a plurality of scanning lines 18a extending from the outside of the area are formed, and an intersection of the data lines 16 and the scanning lines 18a is formed. In the vicinity, these data lines 16 and scanning lines 18a and the pixels 19 are electrically connected.

Here, as shown in FIG. 3, the pixel 19 formed in the display region 110 is provided with a TFT 60 and a pixel electrode 9 electrically connected to the drain of the TFT 60. The data line 16 to which the image signal is supplied is electrically connected to the source of the TFT 60, and the scan line 18a is electrically connected to the gate of the TFT 60.

Under the above configuration, each pixel 19 turns on the TFT 60 serving as the switching element only for a certain period of time by the scan signal supplied through the scan line 18a, thereby predetermining the image signal supplied from the data line 16. The pixel electrode 9 is written at the timing of.

An image signal of a predetermined level written in the liquid crystal through the pixel electrode 9 is held for a predetermined period between the pixel electrode 9 and the common electrode 21 facing through the liquid crystal 50. The light is modulated by changing the orientation and order of the molecules of the liquid crystal according to the applied voltage level, thereby enabling arbitrary gray scale display.

In addition, in order to prevent the image signal written in the liquid crystal from leaking out, the storage capacitor may be added to each pixel in parallel with the liquid crystal capacitance formed between the pixel electrode 9 and the common electrode 21. In this case, a capacitor line extending substantially parallel to the scan line 18a is formed on the TFT array substrate 10.

Returning to FIG. 2, the data line 16 electrically connected to each pixel 19 extends to the outside of the display area 110 (lower side) and is electrically connected to the data line driving circuit 101. It is. The other end side of the data line 16 is electrically connected to the corresponding electrostatic protection circuit 72, respectively. Each electrostatic protection circuit 72 is electrically connected to two electrostatic protection circuits 71 via connection wirings 83 and 82. In addition, each of the electrostatic protection circuits 71 is electrically connected to the common electrode wiring 90 through the connection wiring 81.

Scan lines 18a electrically connected to the respective pixels 19 extend to the outside (right side) of the display area 110, respectively, and are electrically connected to the scan line driver circuit 104. The other end side of the scanning line 18a extends to the outside (left side) of the display region 110 and is electrically connected to the electrostatic protection circuit 74, respectively. Each electrostatic protection circuit 74 is electrically connected with two electrostatic protection circuits 73 via connection wirings 86 and 85, and the two electrostatic protection circuits 73 are connected via connection wiring 84, respectively. It is electrically connected to the common electrode wiring 90.

The 1st shield wiring part 91 which consists of four wiring members 18c-18f extended so that the display area 110 may be enclosed is provided. The wiring member 18c extends between the electrostatic protection circuit 72 arranged along the array direction of the data line 16 and the display region 110 in the left and right directions. The wiring member 18d extends between the electrostatic protection circuit 74 arranged along the arrangement direction of the scan line 18a and the connection wiring 85 in the up and down direction. The wiring member 18e extends from the lower end of the wiring member 18d to the right side of the drawing and extends along an end portion of the display region 110 in the lower side of the illustration. The wiring member 18f extends from the display region 110 to between the scan line 18a connected to the scan line driver circuit 104 and the wiring member 90a extending along the right end of the TFT array substrate 10. Extends along the vertical direction.

The left end of the wiring member 18c and the upper end of the wiring member 18d are electrically connected to each other, and are electrically connected to the connection wiring 84 through the connecting member 9b, and the wiring member 18c is illustrated. The right end and the upper end of the wiring member 18f are electrically connected to each other and electrically connected to the common electrode wiring 90 via the connecting member 9a.

Therefore, the wiring members 18c to 18f are electrically connected to each other and electrically connected to the common electrode wiring 90 through the connection members 9a and 9b.

The common electrode wiring 90 is roughly hooked in plan view from the left edge end of the TFT array substrate 10 to the right edge of the city via the top edge of the city, and has a common electrode at one end of the left side edge of the TFT array substrate 10. It is electrically connected to the power supply 108. In addition, it is electrically connected to the narrow wiring member 90a at the front-end | tip part of the right side edge part of illustration. Therefore, electrically, the common electrode wiring 90 and the wiring member 90a are arranged so as to surround three sides of the display region 110, and constitute the second shield wiring portion 92 according to the present invention. have.

In the present embodiment, the wiring members 18c to 18f are wiring members formed on the same layer as the scan line 18a by using the same material. On the other hand, the connection wirings 81-86, the common electrode wiring 90, and the wiring member 90a are wiring members formed in the same layer as the data line 16 using the same material. Although the connection wiring 86 electrically connected to one end of the electrostatic protection circuit 74 and the scanning line 18a electrically connected to the other end are wiring members formed in different wiring layers, respectively, the electrostatic protection circuit 74 ), Electrical conduction between layers is achieved.

Next, the electrostatic protection circuits 71 to 74 will be described with reference to FIG. 3. FIG. 3 is a circuit diagram illustrating a detailed configuration of an upper left portion of FIG. 2.

As shown in FIG. 3, the electrostatic protection circuit 71 connects the first MOS diode 71a formed by connecting the gate and drain of the TFT and the second MOS diode 71b formed by connecting the gate and drain of the TFT. And a structure formed by connecting in opposite directions to each other. The source of the first MOS diode 71a (drain of the second MOS diode 71b) and the connection wiring 81 are electrically connected, and the drain of the first MOS diode 71a (of the second MOS diode 71b). Source) is electrically connected to the connection wiring 82. The other electrostatic protection circuits 72 to 74 have substantially the same configuration.

The electrostatic protection circuits 71 to 74 having the above constitution have nonlinearities in both directions in current and voltage characteristics. Each diode has a high impedance when the low voltage is applied, and a low impedance state when the high voltage is applied. Moreover, since each diode is a transistor substantially, the ability to flow an electric current is large and a static electricity can be absorbed at high speed, high electrostatic protection capability is acquired.

Under the above configuration, each of the electrostatic protection circuits 71 to 74 turns on when a positive or negative excessive surge is applied, and has a function of flowing the surge to the common electrode wiring 90 (LC COM.) At high speed. Thus, the TFT 60 of the display area 110 is protected.

Next, the pixel configuration of the liquid crystal device 100 will be described with reference to FIGS. 4 and 5. 4 is a plan view showing the pixel configuration of the liquid crystal device 100. FIG. 5 is a cross-sectional view taken along the line D-D 'of FIG. 4 in the case where the reflective liquid crystal device or the transmissive liquid crystal device is configured.

As shown in FIG. 4, in the display area of the liquid crystal device 100, a plurality of scan lines 18a extend in the left and right directions shown in the drawing, and a plurality of data lines 16 extend in a direction crossing these scan lines. . In FIG. 4, the rectangular region is the pixel region (pixel 19) when viewed in a plane surrounded by the adjacent scanning line 18a and the adjacent data line 16.

In each pixel region, a substantially rectangular pixel electrode 9 is provided in a plan view made of a transmissive conductive film such as ITO (indium tin oxide), and the pixel electrode 9, the scanning line 18a, and the data line are provided. The TFT 60 is inserted between the 16 and the 16. The TFT 60 includes a semiconductor layer 33 made of amorphous silicon (a-Si), a gate electrode 18b provided below the semiconductor layer 33 (substrate side), and an upper layer of the semiconductor layer 33. A source electrode 34 and a drain electrode 35 provided on the side are provided.

The gate electrode 18b is formed by branching a part of the scanning line 18a toward the pixel electrode 9, and at the distal end thereof, through the semiconductor layer 33 and an insulating film (gate insulating film) (not shown) in the paper vertical direction. Is facing. The source electrode 34 is formed by branching a part of the data line 16 in the extending direction of the scan line 18a and is electrically connected to the semiconductor layer 33 (source region). One end (left end) of the drain electrode 35 is electrically connected to the semiconductor layer 33 (drain region), and the other end (right end) of the drain electrode 35 is electrically connected to the pixel electrode 9. It is.

The TFT 60 under the above configuration is turned on for only a predetermined period by a gate signal input through the scanning line 18a, so that the switching for writing the image signal supplied through the data line 16 to the liquid crystal at a predetermined timing. It functions as an element.

FIG. 5 is a cross-sectional configuration diagram of the TFT array substrate 10 along the line D-D 'in FIG. 4 when the liquid crystal device 100 is a reflective liquid crystal device or a transmissive liquid crystal device. Referring to the cross-sectional structure shown in the drawing, the TFT array substrate 10 is mainly composed of the TFT 60 formed on the inner surface side (upper surface side) of the glass substrate P and the pixel electrode 9 mainly. .

On the glass substrate P, the gate electrode 18b (scan line 18a) is patterned, and the gate insulating film 43 which consists of silicon oxide, silicon nitride, etc. is formed covering the gate electrode 18b. The semiconductor layer 33 is formed at the position overlapping planarly with the gate electrode 18b on the gate insulating film 43.

The semiconductor layer 33 consists of an amorphous silicon layer 33a and the N + silicon layer 33b laminated | stacked on this amorphous silicon layer 33a. The N + silicon layer 33b is divided into two parts spaced apart on the amorphous silicon layer 33a in plan view, and one (left) N + silicon layer 33b extends on the gate insulating film 43 to form the N +. The N + silicon layer 33b on the other side (right side) is electrically connected to the source electrode 34 formed to sit on the silicon layer 33b, and extends on the gate insulating film 43 to form the N + silicon layer ( It is electrically connected to the drain electrode 35 formed so that it may rise on 33b).

A passivation film 44 made of silicon nitride or the like is formed to cover the source electrode 34 and the drain electrode 35. The passivation film 44 has a part opening on the drain electrode 35, and the pixel electrode 9 electrically connected with the drain electrode 35 is formed through this opening.

In the case of a transmissive liquid crystal device, the pixel electrode 9 is formed using a transparent conductive material such as ITO (indium tin oxide). In the case of a reflective liquid crystal device, a light reflective metal material such as Al or Ag is used. It is formed using. In the case of the reflective liquid crystal device, light scattering means for improving the visibility of the display is provided on the pixel electrode 9 or the liquid crystal side thereof.

Further, in practice, an alignment film for controlling the initial alignment state of the liquid crystal is formed on the surface of the pixel electrode 9, and a phase difference for controlling the polarization state of light incident on the liquid crystal layer on the outer surface side of the glass substrate P. A plate and a polarizing plate are provided. Moreover, in the case of a transmissive liquid crystal device, the backlight used as an illumination means is provided in the outer side (back panel side) of the TFT array substrate 10. As shown in FIG.

As shown in FIG. 1, the opposing substrate 20 has a common electrode 21 made of a planar beta-transmissive conductive film on the inner surface (opposed surface of the TFT array substrate) of the same substrate as the glass substrate P. As shown in FIG. It has a formed configuration. The same alignment film as that of the TFT array substrate is formed on the common electrode 21, and a retardation plate and a polarizing plate are disposed on the outer surface of the substrate as necessary.

In addition, the liquid crystal 50 sealed between the TFT array substrate 10 and the counter substrate 20 is mainly composed of liquid crystal molecules. As the liquid crystal molecules constituting the liquid crystal layer, any liquid crystal molecules may be used as long as the liquid crystal molecules, the smectic liquid crystals, and the like can be aligned, but in the case of the TN type liquid crystal panel, it is preferable to form the nematic liquid crystals. For example, phenylcyclohexane derivative liquid crystal, biphenyl derivative liquid crystal, biphenylcyclohexane derivative liquid crystal, terphenyl derivative liquid crystal, phenyl ether derivative liquid crystal, phenyl ester derivative liquid crystal, bicyclohexane derivative liquid crystal, azomethine derivative liquid crystal, azoxy derivative Liquid crystal, a pyrimidine derivative liquid crystal, a dioxane derivative liquid crystal, a cuban derivative liquid crystal, etc. are mentioned.

Next, a specific configuration example of the electrostatic protection circuit 71 will be described with reference to FIGS. 6 and 7.

6 is a diagram showing the structure of a MOS diode applicable to the electrostatic protection circuits 71 to 74. FIG. 7 is a diagram showing the structure of a capacitively coupled operation type MOS diode applicable to the electrostatic protection circuits 71 to 74. FIG.

First, an example of the configuration of the electrostatic protection circuit 71 shown in FIG. 6 will be described. FIG. 6A is a planar configuration diagram of the electrostatic protection circuit 71, and FIG. 6B is a cross-sectional configuration diagram taken along the line AA ′ of FIG. 6A.

The electrostatic protection circuit 71 shown in FIG. 6A has a configuration in which the first MOS diode 71a and the second MOS diode 71b formed by shorting the gate and drain of the TFT are connected in opposite directions. The first MOS diode 71a is electrically connected to the semiconductor layer 173a, the gate electrode 177 provided on the back side (substrate P side) of the semiconductor layer 173a, and the semiconductor layer 173a. The source electrode 171a and the drain electrode 172a are provided. The source electrode 171a is formed by branching the source side wiring 171. The source side wiring 171 and the gate electrode 177 are electrically connected through the contact hole and the relay electrode 178. In addition, the drain electrode 172a is electrically connected to the gate wiring 176 through the contact hole and the relay electrode 174.

On the other hand, the second MOS diode 71b is electrically connected to the gate wiring 176 (gate electrode), the semiconductor layer 173b formed at a position overlapping the gate wiring 176 in a planar manner, and the semiconductor layer 173b. The connected source electrode 171b and the drain electrode 172b are provided, and the drain electrode 172b and the gate wiring 176 are electrically connected through the contact hole and the relay electrode 175. The source electrode 171b is formed by branching the source side wiring 171.

In the cross-sectional structure shown in FIG. 6B, the gate wiring 176 is formed on the substrate P, and the gate insulating film 43 is formed to cover the gate wiring 176. A semiconductor layer 173b (an amorphous silicon layer and an N + silicon layer) is formed on the gate insulating film 43 at a position overlapping the gate wiring 176 in a planar manner, so as to rise on both sides of the semiconductor layer 173b. The source electrode 171b and the drain electrode 172b are formed. The passivation film 44 is formed covering the source electrode 171b and the drain electrode 172b. The passivation film 44 on the drain electrode 172b partially opens, and the gate insulating film 43 and the passivation film 44 on the gate wiring 176 on the right side of the figure are partially open, and the relay electrode partially embedded in these openings. The drain electrode 172b and the gate wiring 176 are electrically connected by 175.

In the electrostatic protection circuit 71 having the above-described configuration, when a surge occurs on the connection wiring 82 side, as described above, a low impedance state is turned on, and the surge is relayed to the common electrode wiring to display the display area. The switching element 110 can be protected.

In addition, when comparing the configuration of the electrostatic protection circuit 71 and the above-described TFT 60, the gate wiring 176 (and the gate electrode 177) is the gate electrode 18b of the TFT 60 (scanning line ( 18a), and the source electrodes 171a and 171b and the drain electrodes 172a and 172b are the source electrode 34 (data line 16) and the drain electrode 35 of the TFT 60. Located on the same floor as the The relay electrodes 175, 174, and 178 are located on the same layer as the pixel electrode 9 connected to the TFT 60.

Therefore, in the manufacturing process of the TFT array substrate 10, the electrostatic protection circuit 71 of this embodiment can be formed simultaneously with the pixel 19 which comprises the display area 110 in the same process.

Next, another example of the configuration of the electrostatic protection circuit 71 shown in FIG. 7 will be described. FIG. 7A is a planar configuration diagram of the electrostatic protection circuit 71, and FIG. 7B is a cross-sectional configuration diagram taken along the line BB ′ of FIG. 7A.

The electrostatic protection circuit 71 shown in FIG. 7A has a configuration in which the first MOS diode 71a and the second MOS diode 71b formed by shorting the gate and drain of the TFT are connected in opposite directions. have. The first MOS diode 71a is electrically connected to the semiconductor layer 183a, the gate electrode 186 provided on the back side (substrate P side) of the semiconductor layer 183a, and the semiconductor layer 183a. The source electrode 181a and the drain electrode 182a are provided. The source electrode 181a extends to the left side of the figure and is electrically connected to the common electrode power source 108. The source electrode 181a and the gate electrode 186 are electrically connected through the contact hole and the relay electrode 185. The drain electrode 182a extends toward the second MOS diode 71b and is electrically connected to the source electrode 181b of the second MOS diode 71b. The electrode branched from the source electrode 181a and extending toward the second MOS diode 71b constitutes the drain electrode 182b of the second MOS diode 71b.

The source electrode 181a and the gate electrode 186 of the first MOS diode 71a are partially overlapped in a planar manner, and the capacitor C1 is formed at such an overlapping position.

On the other hand, the second MOS diode 71b includes a semiconductor layer 183b, a source electrode 181b and a drain electrode 182b electrically connected to the semiconductor layer 183b, and the source electrode 181b The gate electrode 187 is electrically connected through the contact hole and the relay electrode 188. The source electrode 181b extends to the right side of the drawing and is electrically connected to the connection wiring 82.

In the second MOS diode 71b, the source electrode 181b and the gate electrode 188 are partially overlapped in a planar manner, and the capacitor C2 is formed at such an overlapping position.

In the cross-sectional structure shown in FIG. 7B, the gate electrode 187 is formed on the substrate P, and the gate insulating film 43 is formed to cover the gate electrode 187. A semiconductor layer 183b (an amorphous silicon layer and an N + silicon layer) is formed on the gate insulating film 43 at a position overlapping the gate electrode 187 in a planar manner, so as to rise on both sides of the semiconductor layer 183b. Thus, the source electrode 181b and the drain electrode 182b are formed. The passivation film 44 is formed covering the source electrode 181b and the drain electrode 182b. The passivation film 44 on the drain electrode 182b is partially opened, and the gate insulating film 43 and the passivation film 44 on the gate electrode 187 on the right side of the drawing are partially open, and the relay electrode partially embedded in these openings. The drain electrode 182b and the gate electrode 187 are electrically connected to each other by (188).

In addition, when the structure of the electrostatic protection circuit 71 and the above-described TFT 60 are compared, the gate electrode 187 (and the gate electrode 186) is the gate electrode 18b of the TFT 60 (scanning line ( 18a)), and the source electrodes 181a and 181b and the drain electrodes 182a and 182b are the source electrode 34 (data line 16) and the drain electrode 35 of the TFT 60. Located on the same floor as the The relay electrodes 188 and 185 are located on the same layer as the pixel electrode 9 connected to the TFT 60.

Therefore, the electrostatic protection circuit 71 of the present embodiment can also be formed simultaneously in the same process as the pixel 19 constituting the display region 110 in the manufacturing process of the TFT array substrate 10.

The electrostatic protection circuit 71 having the above-described configuration is configured by connecting the capacitively coupled operation type MOS diodes 71a and 71b in opposite directions to each other, and is also compared with the electrostatic protection circuit 71 shown in FIG. 6. It is suitable as an electrostatic protection circuit of the apparatus. Normally, a MOS diode short-circuiting the gate and drain of a TFT does not operate as a protection circuit unless the gate and drain are connected. However, in the electrostatic protection circuit 71 shown in FIG. 7, relay electrodes 185 and 188 are not provided. Even if it is not, the first MOS diode 71a can be operated by the capacitance ratio of the capacitor C1 and the gate insulating film 43, and the second MOS diode 71b by the capacitance ratio of the capacitor C2 and the gate insulating film 43. ) Can also be operated. That is, in the case where the electrostatic protection circuit 71 and the pixel 19 are simultaneously formed in the same process, the MOS diode shown in FIG. 6 does not operate as a protection circuit unless the pixel electrode 9 is formed. Since the capacitively coupled operation type MOS diode shown in FIG. 7 operates when the source / drain electrodes are formed, the electrostatic protection circuit can be operated at an earlier stage of the manufacturing process, and the TFT 60 can be effectively protected. It is.

As described above with reference to the drawings, the liquid crystal device 100 of the present embodiment includes the first shield wiring portion 91 surrounding the display region 110 and the first shield wiring portion 91. Since the second shield wiring portion 92 has a configuration provided on the TFT array substrate 10, excellent electrostatic resistance can be obtained. In addition, since the shield wiring portions 91 and 92 are included in the liquid crystal device as a product, the shield wiring portions 91 and 92 are well protected not only in the manufacturing process but also in use, and protect the circuit from static electricity, and are excellent in reliability.

The shield wiring portions 91 and 92 can both be formed simultaneously in the manufacturing process of the pixel 19 of the display region 110, and the electrostatic protection circuit included in the liquid crystal device of the present embodiment is all pixels ( It can be manufactured simultaneously in the manufacturing process of 19). Therefore, according to this embodiment, the reliability of the liquid crystal device can be improved without increasing the number of manufacturing steps.

(Example 2)

Next, Embodiment 2 of the present invention will be described with reference to FIG. 8 is a diagram showing a schematic circuit configuration of the TFT array substrate 10 in the liquid crystal device of this embodiment. In addition, since structures other than the circuit structure shown in FIG. 8 are the same as that of Example 1 mentioned above, common structure is demonstrated, abbreviate | omitting detail suitably.

As shown in FIG. 8, the TFT array substrate 10 of the liquid crystal device according to the present embodiment includes a display region 110 and a display region 110 in which a plurality of pixels 19 are arranged in a matrix in plan view. The data line driving circuit 101, the two scanning line driving circuits 104, and the two common electrode power supplies 108 are arranged along the substrate end at the bottom of the drawing. The data line 16 extending from the data line driving circuit 101 and each pixel 19 are electrically connected to each other, and the scanning line 18a and each pixel 19 extending from the scanning line driving circuits 104 and 104 are respectively connected. It is electrically connected.

Each data line 16 extending upward from the display region 110 is electrically connected to an electrostatic protection circuit 72, and the electrostatic protection circuit 72 is provided via two electrostatic protection circuits 71. It is electrically connected to the wiring member 192a which extends to the board | substrate edge part in the left-right direction shown. Each scanning line 18a extending from the display area 110 in the left and right directions in the drawing is electrically connected to the electrostatic protection circuit 74, respectively. The blackout protection circuit 74 arranged at the left side of the illustration is electrically connected to the wiring member 192b via two blackout protection circuits 73, and the blackout protection circuit 74 arranged at the right side of the illustration has two blackouts. It is electrically connected to the wiring member 192d via the protection circuit 73.

The liquid crystal device of the present embodiment includes a first shield wiring portion 191 and a display region 110 formed of a substantially 'c' shaped wiring member in plan view extending along three ends of the TFT array substrate 10. Planar view provided between the second shield wiring portion 192 including the four wiring members 192a to 192d disposed to surround the first shield wiring portion 192 and the first shield wiring portion 191 and the second shield wiring portion 192. A third shield wiring portion 193 made of '-' shaped common electrode wiring is provided.

The wiring members 192a to 192d constituting the second shield wiring portion 192 are electrically connected to each other at each end portion, and the third shield wiring is connected through the connection members 9c to 9f disposed at the top of the substrate. It is electrically connected to the part 193 (common electrode wiring). Moreover, the wiring member 192c is arrange | positioned so that the back side (substrate P side) of the data line driving circuit 101 may pass. Although the data line 16 of the same layer is connected to the data line driver circuit 101 with the wiring member 192c, the wiring member 192c is disposed so as to pass through the IC chip mounting area to interfere with the data line 16. You can do it.

The first shield wiring portion 191 is formed on the same layer as the scan line 18a using the same material, and the second shield wiring portion 192 and the third shield wiring portion 193 are both data lines ( It is formed in the same layer as 16) using the same material. Therefore, also in this embodiment, the shield wiring portions 191 to 193 can be formed simultaneously with the pixel 19 of the display region 110 in the same process.

According to the liquid crystal device of the present embodiment having the above configuration, since three shield wiring portions 191 to 193 are disposed so as to surround the display region 110, the liquid crystal device of the first embodiment described above is also provided. A liquid crystal device having better electrostatic resistance can be obtained. Therefore, it is hard to generate | occur | produce damage in a manufacturing process, it can manufacture by a high product ratio, and is a liquid crystal device excellent in reliability.

(Electronics)

9 is a perspective view showing an example of an electronic apparatus according to the present invention. The mobile telephone 1300 shown in this figure is equipped with the liquid crystal device of the said embodiment as the display part 1301 of a small size, and is provided with the some operation button 1302, the telephone receiver 1303, and the telephone receiver 1304. FIG. It is composed.

The electro-optical device of each of the above embodiments is not limited to the mobile phone, but is an e-book, a personal computer, a digital still camera, a liquid crystal television, a view finder type or a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook. Can be suitably used as an image display means such as an electronic calculator, a word processor, a workstation, a video telephone, a POS terminal, a device equipped with a touch panel, and can display a display unit with excellent reliability in any electronic device. This greatly contributes to improving the reliability of electronic devices.

According to the present invention described above, it is possible to provide an electro-optical device having a structure capable of satisfactorily protecting an active element from static electricity, and which can also realize the efficiency of the manufacturing process and the improvement of the product ratio.

Claims (14)

An electro-optical device comprising a display area formed by arranging a plurality of pixels in a matrix and a switching element provided corresponding to each pixel. A first shield wiring portion surrounding at least three sides of the display region on an element substrate; A second shield wiring portion surrounding the first shield wiring portion Electro-optical device comprising a. The method of claim 1, At least one of the said 1st shield wiring part and a 2nd shield wiring part is formed in the rectangular shape surrounding the said display area, The electro-optical device characterized by the above-mentioned. The method of claim 2, The first shield wiring portion and the second shield wiring portion are electrically connected to a common electrode formed over the plurality of pixels. The method according to any one of claims 1 to 3, A common electrode wiring electrically connected to a common electrode formed over the plurality of pixels is further provided on the element substrate, The common electrode wiring forming a third shield wiring portion surrounding at least three sides of the display area; Electro-optical device, characterized in that. The method according to any one of claims 1 to 3, The switching element is a thin film transistor having a gate electrode formed on the element substrate, a semiconductor layer opposing the gate electrode and a gate insulating film therebetween, and a source / drain electrode electrically connected to the semiconductor layer, One of the said 1st shield wiring part and the 2nd shield wiring part is formed in the same layer as the said source / drain electrode using the same material. Electro-optical device, characterized in that. The method of claim 5, Either of the first shield wiring portion and the second shield wiring portion is formed on the same layer as the gate electrode by using the same material. The method of claim 5, A pixel electrode electrically connected to the switching element via the source / drain electrode; One of the first shield wiring portion and the second shield wiring portion is formed on the same layer as the pixel electrode using the same material. Electro-optical device, characterized in that. The method according to any one of claims 1 to 3, A pixel electrode electrically connected to the switching element via the source / drain electrode; At least two of the said 1st-3rd shield wiring parts are electrically connected to each other by the connection member formed in the same layer as the said pixel electrode using the same material. Electro-optical device, characterized in that. The method of claim 5, A plurality of data lines and a plurality of scan lines are formed on the device substrate so as to cross each other, and the pixels are provided corresponding to the intersections of the data lines and the scan lines. The first shield wiring section or the second shield wiring section, and the scanning line or the data line are electrically connected through at least one electrostatic protection circuit. The method of claim 9, The electrostatic protection circuit has an MOS diode having a semiconductor layer formed on the same layer as the thin film transistor. The method of claim 10, The electrostatic protection circuit is formed by connecting a first MOS diode and a second MOS diode formed by shorting a gate electrode and a drain electrode of the thin film transistor in opposite directions to each other. The method of claim 11, The source electrode and the gate electrode in the first MOS diode are planarly superimposed, and the source electrode and the gate electrode in the second MOS diode are partially capacitively superimposed. Electro-optical device. The method of claim 12, The capacitively coupled MOS diode is electrically connected to the shield wiring portion formed on the same layer as the data line. An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 3.

Images