KR20070014984A - Non-volatile, resistive memory cell based on metal oxide nanoparticles, process for manufacturing the same and memory cell arrangement of the same - Google Patents

Abstract

A non-volatile resistive memory cell based upon metal oxide nano particles is provided to reduce fabricating costs and realize a high storage density by including metal oxide nano particles arranged between two electrode regions such that the metal oxide nano particles connect the electrode region electrically and designate a bistable resistance characteristic. A memory region is disposed between a first conductive electrode region and a second conductive electrode region, containing one or more metal oxide nano particles(10). The first conductive electrode region can be a tungsten electrode. The second conductive electrode region can be made of at least one metal selected from a group of aluminum, titanium and platinum. The metal oxide nano particles pass through contact positions(K1,K2) to come in contact with the first and the second conductive electrode regions, electrically connected to the first and the second conductive electrode regions. The metal oxide nano particles designate bistable resistivity when an external voltage is applied.

Description

Non-volatile, resistive memory cell based on metal oxide nanoparticles, process for manufacturing the same and memory cell arrangement of the same}

1 schematically illustrates an arrangement of metal oxide nanoparticles embedded in a dielectric disposed between two electrodes in one embodiment of the present invention;

Figure 2a is a view showing a nanostructure of 2.9nm particle size prepared according to one embodiment of the present invention;

Figure 2b is a view showing a nanostructure of the 7.9nm particle size prepared according to an embodiment of the present invention;

3 illustrates that conductive filaments are formed in nanoparticles;

4 is a diagram illustrating a memory cell array having a form of an intersection array serving as one embodiment of the present invention;

5A is a cross-sectional view taken along the line A-A 'of FIG. 4;

FIG. 5B is a cross sectional view along line BB ′ in FIG. 4; And

6A to 6D are views illustrating a manufacturing process of the bottom contact.

<Explanation of symbols for main parts of drawing>

1: silicon substrate 2: silicon oxide layer

2a: etch stop layer of silicon nitride 3,3a, 3b: silicon oxide layer

4: NiO _1-x nanoparticle 5: silicon oxide insulating layer

6,12: top contact 9-1: bottom contact

9-1a: tungsten deposition

9-1b: sublithographic plug made of tungsten

10: nanoparticle 11: insulating matrix

K1: Contact position for the bottom contact K2: Contact position for the top contact

S, S1 to S9: memory elements

The present invention relates to a nonvolatile resistive memory cell based on bistable resistivity of metal oxide nanoparticles, a method for manufacturing the nonvolatile memory cell, and a single memory cell arrangement of a plurality of memory cells.

Conventional storage techniques (floating gate memories such as flash and DRAM) are based on the storage of charge on inorganic silicon based materials. These techniques for storing charges will reach scale limits in the near future. Therefore, research on other methods for storing information is increasing. At this point, the principle of resistive memories based on the bistable resistive change for metal oxide nanoparticles will be in the spotlight.

By the way, according to the conventional method for producing a resistive switching metal oxide resistive material, several nanometers of active memory cells cannot be realized. Techniques currently used for the deposition of microcrystalline storage materials include conventional thin film fabrication techniques such as oxidation of metal films following deposition or sputtering (JFGibbons and WEBeadle, Solid-State Electron., 7, 785 (1964); WR). Hiatt and TW Hickmott, Appl. Phys. Lett., 6, 106 (1965) and F. Argall, Solid-State Electron., 11, 535 (1968). During the deposition process, in part, quite high internal mechanical stresses occur in the layers. This stress is increased by uneven heating of large layer volumes due to thermistor effect, so that the adhesion of the layers often limits the switching cycle and the layers will peel off (S.Seo, MJLee, DHSeo, EJ Jeong, D.-S.Suh, YSJoung, IKYoo, IRHwang, SHKim, ISGyun, J.-S.Kim, JSChoi and BHPark, Appl.Phys. Lett., 85, 5655 (2004) and S.Seo, MJLee, SKChoi, DSSuh, YSJoung, IKYoo, ISByun, IRHwang, SHKim, BHPark, Appl. Phys. Lett., Vol. 86 (2005), S. 093509) . Until now, bistable switching in nickel oxide has only been observed in connection with chemical conversion or chemical reaction of oxide materials in narrow filaments. Here, the layer broke after a limited number of cycles.

In addition, since the reduction in size is difficult, high storage density cannot be realized with this technique.

The mechanism of monostable or temporarily limited bistable switching is based on the insulator discharge and thermistor effects associated with diffusing the contact material into the memory cell, so that only a small number of switching cycles are possible. This severely limits the lifetime.

It is therefore an object of the present invention to provide a new type of memory cell that is easy to manufacture. According to the invention, this object is achieved by the claims 1, 5 and 14 below.

According to a first embodiment of the present invention, the nonvolatile memory cell comprises metal oxide nanoparticles arranged between two electrode regions. At this time, the metal oxide nanoparticles electrically connect the electrode regions and exhibit bistable resistance characteristics.

Due to the reduced switching and storage effects on only a few or even single nanoparticles, the memory cell according to the invention achieves a low cost and a significantly high storage density. Therefore, lower switching power and faster switching time can be realized than storage techniques for conventionally deposited NiO _1-x layers.

The present invention using metal oxide nanoparticles can switch between two bistable resistive states in nanoparticles. Applying a corresponding voltage within a narrow range enables switching between these resistive states. Due to thermal-electronic interactions to the trap centers and metal diffusion along the nanocrystal boundaries, the high conductivity state is stabilized. Formation and breakdown of high conductivity filament regions are also associated with thermistor effects. Due to the uneven temperature distribution in the metal oxide storage material when a voltage is applied, the thermistor effect improves the diffusion process, the charging and discharging processes in a bad state.

According to a second aspect of the present invention, a method of manufacturing a nonvolatile memory cell includes: providing a first conductive electrode region on a substrate; Arranging metal oxide nanoparticles on the first conductive electrode region; Filling a gap between the metal oxide nanoparticles, thereby forming a common surface between the metal oxide nanoparticles and the dielectric; And arranging a second conductive electrode region on the common surface.

The present invention provides chemical oxide deposition of biblock copolymers on CMOS compatible contacts using a simple low cost low temperature process to generate metal oxide nanoparticles, ie metal oxide nanoparticles made of non-stoichiometric NiO _1-x . Provide a method for

Due to the small dimensions, density and uniformity of deposition of the metal oxide nanoparticles, memory cells of high density and improved switching and storage characteristics can be realized. Bistable switching can be performed using single particles of about 3 nm x 3-5 nm. Therefore, the conductive filaments can be reduced to dimensions of about 3 nm or less in the on-state. This magnitude corresponds to the limits for thermo-electronic switching and storage effects.

Even when several nanoparticles are in contact with a pair of contacts, bistable switching is performed by only one nanoparticle. Nanoparticles first take the form of conductive filaments that perform information storage. Therefore, if a nanoparticle does not work, another nanoparticle can immediately resume the function of the failed nanoparticle. Minimum dimensions for memory cells are simply limited by the current CMOS technology.

Therefore, the present invention provides a nonvolatile memory cell based on the bistable resistance characteristics of metal oxide nanoparticles. The manufacturing process of such memory elements is based on the formation of nanocrystals applied via a biblock copolymer monolayer.

According to another embodiment of the present invention, a memory cell arrangement includes a plurality of nonvolatile memory cells.

According to a preferred embodiment of the present invention, the metal oxide nanoparticles are made of NiO _1-x nanoparticles. In this case, x is in the range of 0.5 to 0.95, preferably 0.7 to 0.9.

Among the metal chalcogenides, nickel oxide has an exceptional position due to the broadband gap of about 4.5 eV. At room temperature, the nickel oxide of the stoichiometric composition is an isolation semiconductor. In addition, because of the steep change in resistance temperature characteristics when an appropriate voltage is applied, nickel oxide has a negative differential resistance and monostable switching in its IU-characteristics due to the thermistor effect. Indicates an area with monostable switching.

On the one hand, electron defects are formed in layers of NiO _1-x nanoparticles due to oxygen deficiency, and on the other hand, nickel ion diffusion increases along the defects and grain boundaries due to excessive nickel. The diffusion of nickel is a thermally activated process. This process is a very complex process of charging and discharging deep defects caused by oxygen deficiency, and thermally enhanced interaction of nickel ion diffusion. Due to the nonstoichiometric composition of NiO _1-x , this composition lacks oxygen.

According to another preferred embodiment of the present invention, the first electrode region is a tungsten electrode.

According to another improved embodiment of the present invention, the second electrode region is made of aluminum, titanium or platinum.

According to another preferred embodiment of the present invention, the substrate is a silicon substrate.

According to a more preferred embodiment of the present invention, the applied metal oxide nanoparticles are made of NiO _1-x nanoparticles. In this case, x is in the range of 0.5 to 0.95, preferably 0.7 to 0.9.

According to a more preferred embodiment of the present invention, the first conductive electrode region is a tungsten bottom contact.

According to a more preferred embodiment of the present invention, the second conductive electrode region is made of aluminum, titanium or platinum.

According to a more preferred embodiment of the present invention, the dielectric provided between the metal oxide nanoparticles is SiO ₂ , Si ₃ N ₄ or Al ₂ O ₃ .

According to a more preferred embodiment of the present invention, dielectric SiO ₂ is deposited through dissociation of hexamethyldisiloxane.

According to a more preferred embodiment of the present invention, the metal oxide nanoparticles have a size of 2.5 to 15nm, preferably 3 to 8nm.

According to a more preferred embodiment of the present invention, the memory cells are arranged in a crosspoint array.

The above and other objects and features of the present invention will become more apparent from the detailed description of the preferred embodiment with reference to the accompanying drawings. Like reference numerals in the drawings denote like or functionally identical parts.

1 shows a memory element S. As shown in FIG. Two nanoparticles 10 of NiO _1-x are embedded in the insulating matrix 11 of the dielectric. The nanoparticles 10 are in contact with the bottom contact 9 via contact positions K1 and in contact with the upper contact 12 via contact positions K2.

2A and 2B show nanostructures made in accordance with the present invention and having particle diameters of 2.9 nm and 7.9 nm, respectively.

FIG. 3 shows NiO _1-x nanoparticles 10 of insulating matrix 11 with or without conductive filaments (left side of the figure) (right side of the figure). Nanoparticle 10 is in contact with bottom electrode 9 and top electrode 12.

4 and 5 are diagrams showing the configuration of the memory element arrangement. 4 is a plan view of a memory element arrangement. The word lines 9-1, 9-2 and 9-3 as well as the bit lines 12-1, 12-2 and 12-3 are arranged on the substrate 1 made of silicon. An insulating matrix 11 in which nanoparticles are embedded is arranged between word lines and bit lines. Each word line and bit line is in contact with memory elements S1-S9.

5A is a cross-sectional view taken along the line A-A 'of FIG. 4, and FIG. 5B is a cross-sectional view taken along the line B-B' of FIG. In Fig. 5A, the word line 9-1 is arranged on the substrate 1. An insulating matrix 11 in which nanoparticles are embedded is arranged on this word line. Each memory element S7, S8, S9 is connected via bit lines 12-1, 12-2, 12-3 running perpendicular to the word line 9-1.

FIG. 5B is a cross-sectional view taken along the line BB ′ of FIG. 4. A silicon oxide layer 2, an etch stop layer 2a of silicon nitride and another silicon oxide layer 3 are arranged on the substrate 1. Word line contacts 9-1, 9-2, 9-3 are arranged in layer 3 made of silicon oxide. An insulating matrix layer 11 is arranged on the silicon oxide layer 3. Nanoparticles defining memory elements S7, S4, S1 via word lines 9-1, 9-2, 9-3 are embedded in this layer 11. The bit lines 12-1 in contact with the memory elements S7, S4, S1 are arranged on the layer 11 of the insulating matrix.

6A to 6D are views illustrating a manufacturing process of the bottom contact. A silicon oxide layer 2, an etch stop layer 2a made of silicon nitride and another silicon oxide layer 3a are arranged on the silicon substrate 1. 6B shows how tungsten 9-1a is deposited into silicon oxide layer 3a. 6C shows that the silicon oxide layer 3b is arranged over the silicon oxide layer 3a. This silicon oxide layer 3b completely covers the deposition of tungsten 9-1a. Silicon oxide layers 3a and 3b may be bonded to layer 3. 6D shows how a sublithographic plug 9-1b is arranged in the silicon oxide layer 3b in contact with a deposit of tungsten 9-1a. Elements 9-1a and 9-1b may be combined with bottom contact 9-1.

The manufacture of the memory elements is based on silicon wafers pre-cleaned according to the prior art. Electrode structures on such silicon wafers are manufactured according to CMOS technology. This is shown diagrammatically for the formation of the bottom electrode in FIG. 6. According to current technology, the size of sublithographic plugs that limit the effective size of a memory cell is limited to about 40 nm. Therefore, the dimensions of the memory elements are determined by the dimensions available in CMOS technology. As this technology develops, even smaller memory elements become possible.

Preparation of metal oxide nanoparticles is described in R. F. Muligan, A. Iliadis, P. Koofinas; J.Appl. Polymer Science, vol. 89 (2003) und R. T. Clay, R. E. Cohen; Supramol. Scienc., Vol. 5 (1998). In an embodiment of Mulligan et al, zinc oxide nanoparticles are deposited. However, this process can be performed similarly for NiO, for example.

Metal oxide nanoparticles are involved in the process of self-organized deposition of biblock-copolymer-monolayers (self-assembled monolayers, SAMs). It can be made of polynorbornene and polynorbornene carboxylic acids and forms the basis for even deposition of metal oxide nanocrystallites.

Nanoparticles are embedded in a diblock copolymer. Such diblock copolymers can be made, for example, of polynorbornene and poly (norbornenedicarboxylic acid). After synthesis of the copolymer, the copolymer is added to the solution again after drying and the desired amount of Nicl ₂ dissolved in tetrahydrofurane is added to the solution. Ni ²⁺ ions present in solution are associated with the carboxylic acid groups of one component of the copolymer. When such a solution is applied to a tungsten bottom contact, a hexagonally ordered layer grows in a self-organizing process. Such a solution can be applied, for example, by spin coating. However, it is possible to simply dip the wafer into the solution. The resulting metal salt is converted to the corresponding metal oxide by the ammonium hydroxide base. The copolymer is removed by plasma-ahsing.

The nickel oxide particles are then partially reduced by the hydrogen treating gas in the plasma process and contact with the oxygen deficient NiO _1-x composition. The uniform high density structure of NiO _1-x nanoparticles remaining on the wafer has a size of 2.9-7.9 nm as shown in FIG. 2.

In order to isolate the nickel oxide nanoparticles 10, a thin SiO ₂ layer 11 is incidentally deposited by dissociation of hexamethyldisiloxane. The thin SiO ₂ layer 11 is removed from the NiO _1-x particles 10 by chemical mechanical polishing (CMP) until the isolated SiO ₂ remains only in the gap between them. A dielectric is provided to prevent short circuits between the top and bottom contacts. The arrangement of top contacts 12 made by sputtering of aluminum, titanium or platinum completes the memory arrangement.

Although the present invention has been described in terms of preferred embodiments, the present invention is not limited to these embodiments, and many modifications are possible. In particular, nanoparticles can be made of transition metal oxides, in particular oxides of niobium, titanium, tungsten, vanadium and iron.

Claims (15)

As a nonvolatile memory cell, A first conductive electrode region; A second conductive electrode region; And Arranged between the first conductive electrode region and the second conductive electrode region and containing one or more metal oxide nanoparticles, the metal oxide nanoparticles via the contact positions and the first conductive electrode region and the first conductive electrode region; And a metal region in contact with and electrically connected to the conductive electrode region, wherein the metal oxide nanoparticles exhibit bistable resistance when an external voltage is applied. 2. The nonvolatile memory cell of claim 1, wherein the metal oxide nanoparticles are NiO _1-x nanoparticles, wherein x is in the range of 0.5 to 0.95, preferably 0.7 to 0.9. The nonvolatile memory cell of claim 1, wherein the first conductive electrode region is a tungsten electrode. The nonvolatile memory cell of claim 1, wherein the second conductive electrode region is made of at least one metal selected from the group consisting of aluminum, titanium, and platinum. As a method of manufacturing a nonvolatile resistive memory cell, Providing a first conductive electrode region on the substrate; Arranging metal oxide nanoparticles on the first conductive electrode region; Filling a gap between the metal oxide nanoparticles, thereby forming a common surface between the metal oxide nanoparticles and the dielectric; And Arranging a second conductive electrode region on the common surface such that the second conductive electrode region is in contact with the metal oxide nanoparticles. The method of claim 5, wherein the substrate is a silicon substrate. 6. The method of claim 5, wherein the metal oxide nanoparticles are NiO _1-x nanoparticles, wherein x is in the range of 0.5 to 0.95, preferably 0.7 to 0.9. 6. The method of claim 5, wherein the first conductive electrode region is a tungsten contact. 6. The method of claim 5, wherein the second conductive electrode region is made of at least one metal selected from the group consisting of aluminum, titanium, and platinum. The method of claim 5, wherein the dielectric is at least one selected from the group consisting of SiO ₂ , Si ₃ N _4, and Al ₂ O ₃ . The method of claim 10, wherein the SiO ₂ is deposited by dissociation of hexamethyldisiloxane. The method of claim 5, wherein the metal oxide nanoparticles have a size of 2.5 to 15 nm. The method of claim 5, wherein the metal oxide nanoparticles have a size of 3 to 8 nm. A nonvolatile memory cell arrangement comprising a plurality of memory cells according to any one of claims 1 to 4. 15. The nonvolatile memory cell arrangement of claim 14, wherein said memory cells are arranged in a crosspoint array.

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