KR20070012098A - Capacitor embeddied ltcc multilayer boards - Google Patents

Abstract

An LTCC(low temperature co-fired ceramic) stack board is provided to solve a signal leakage problem caused by connection of a high dielectric layer and a signal line by embodying a built-in capacitor while using at least one layer with a high dielectric constant as a dielectric layer and by forming a window region greater than the diameter of a conductive via hole in a specific region of the high dielectric layer used as the built-in capacitor. A predetermined circuit pattern and a conductive via hole are formed in a plurality of low dielectric layers(11) made of a low-dielectric ceramic material. A high dielectric layer(12) is interposed between the plurality of low dielectric layers, including a capacitor region and a non-capacitor region. First and second electrodes(13a,13b) are formed on the upper and the lower surfaces of the capacitor region, and at least one open window region is formed in the non-capacitor region. A conductive via hole is formed in two low-dielectric layers adjacent to the high dielectric layer among the plurality of low dielectric layers has a smaller diameter than that of the window region, interconnected by the window region. A buffer layer(19a,19b) is formed on the first and the second electrodes to prevent the constitution elements of the high dielectric layer from being diffused to the adjacent low-dielectric layers through the first and the second electrodes.

Description

CAPACITOR EMBEDDIED LTCC MULTILAYER BOARDS Built-in Capacitor

1 is a cross-sectional view showing a conventional stacked capacitor array.

2A and 2B are an exploded perspective view and a top plan view of a capacitor layer showing a capacitor-embedded low temperature co-fired ceramic (LTCC) laminated substrate according to an embodiment of the present invention, respectively.

3 is a cross-sectional view illustrating a capacitor-embedded LTCC laminated substrate shown in FIG. 2A.

4 is a graph showing an effective impedance bandwidth of a conventional multilayer capacitor array and a LTCC laminated substrate with a capacitor according to the present invention.

<Code Description of Main Parts of Drawing>

11a, 11b, 11c, 11d, and 11e: low dielectric constant layer 12: high dielectric constant layer

13a, 13b: first and second electrodes 19a, 19b: buffer layer

20: low temperature simultaneous firing ceramic substrate

The present invention relates to a low temperature co-fired ceramic laminated substrate used as a semiconductor package substrate, and more particularly, to a low temperature co-fired ceramic laminated substrate having a capacitor using a high dielectric constant layer.

In general, as additional functions such as WLAN, Bluetooth, DMB, camera, etc. are applied to the wireless communication terminal, modularization of each terminal is rapidly progressing. On the other hand, the clock rate of digital integrated circuits such as a central processing unit (CPU) of a computer is increasing. In this tendency, the elimination of power supply noise and coupling noise is greatly required, so a decoupling capacitor is used.

Typically a stacked chip capacitor (MLCC) is used as the decoupling capacitor. However, since dozens of such decoupling capacitors are mounted in one electronic product, it is difficult to reduce the module size. In addition, there is a problem that the parasitic inductance is further increased according to the distance of the power stage.

As a conventional method for solving such a problem, Korean Patent Laid-Open Publication No. 2001-0066819 (July 11, 2001, Applicant: Murata Seisakusho Murata Yastaka) uses the stacked capacitor array 10 shown in FIG. Suggesting.

Referring to FIG. 1, a mother board 1 having a power supply line and a ground line, a wiring board 3 mounted on the mother board 1, and a stacked type mounted below the wiring board 3. And a capacitor (2), wherein the wiring board (3) comprises a signal line formed of a conductive via hole (4) and a circuit pattern (5), and on the wiring board (3) a microprocessing unit (MPU) chip (5). ) Is mounted.

The stacked capacitor 2 shown in FIG. 1 has a structure in which both first and second electrodes are formed on an upper surface thereof, and is mounted in a cavity region C provided on a lower surface of the wiring board 3 to form an MPU chip 5 and a mosquito. It can be connected in the signal line between the power supply line and the ground line of the plate (1).

According to this structure, the signal line can be relatively shortened, thereby reducing inductance and mounted in the wiring board, and thus can be implemented in a compact module.

However, since the signal line for the connection with the MLCC (2) in the wiring board 3 has a complicated configuration, not only the inductance caused by it, but also because the MLCC (2) in the form of individual elements are used, There is a disadvantage in that the MLCC 2 itself also has an ESL.

SUMMARY OF THE INVENTION The present invention has been made to solve the above technical problem, and an object thereof is to provide a low temperature co-fired ceramic laminated substrate in which at least one layer is formed of a dielectric layer having a high dielectric constant to implement an embedded capacitor.

In order to solve the above technical problem, the present invention

A predetermined circuit pattern and a conductive via hole are formed, interposed between a plurality of low dielectric constant layers made of a low dielectric constant ceramic material and the plurality of low dielectric constant layers, and the first and second electrodes having a capacitor region formed on upper and lower surfaces thereof. And a high dielectric constant layer including a non-capacitor region having at least one window region, wherein conductive via holes formed in two low dielectric constant layers adjacent to the high dielectric constant layer among the plurality of low dielectric constant layers are smaller than the diameter of the window region. It has a low-temperature co-fired ceramic laminated substrate with a capacitor, characterized in that connected to each other through the window area.

Preferably, the method further includes a buffer layer formed on the first and second electrodes in order to prevent the elements of the high dielectric constant layer from diffusing to the adjacent low dielectric constant layers through the first and second electrodes.

Each of these buffer layers is preferably 10 mu m or less, and is preferably formed to a thickness of 5 mu m or more for sufficient diffusion prevention effect.

Preferably, the high dielectric constant layer may be BaTiO ₃ , in this case, the buffer layer may be BaTiO ₃ .

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

FIG. 2A is an exploded perspective view showing a capacitor-embedded low temperature co-fired ceramic (LTCC) laminated substrate according to an embodiment of the present invention. FIG.

Referring to FIG. 2A, a low temperature co-fired ceramic substrate for a package substrate includes first to fifth low dielectric constant layers 11a, 11b, 11c, 11d, and 11e made of a low dielectric constant ceramic material, and the third and fourth low dielectric constants. A high dielectric constant layer 12 interposed between the layers 11c and 11d.

The first to fifth low dielectric constant layers 11a, 11b, 11c, 11d, and 11e have predetermined circuit patterns 14, 17a, and 17b and conductive via holes 15, 16, and 18, respectively. A portion of the circuit pattern 14 formed on the dielectric constant layer 11a may be provided as a conductive pattern for mounting a semiconductor chip.

The first and fifth low dielectric constant layers 11a, 11b, 11c, 11d, and 11e are ceramic substrates having a low dielectric constant used in a conventional LTCC substrate, and the high dielectric constant layer 12 is formed of BaTiO ₃ and ferroelectric materials. It may be made of the same ceramic. Preferably, the high dielectric constant layer 12 may be formed to a thickness of 10 to 30㎛.

The high dielectric constant layer 12 may be divided into a capacitor region 12b and a non-capacitor region 12a as shown in FIG. 2B. First and second electrodes 13a and 13b are formed on the upper and lower surfaces of the capacitor region 12b, respectively, to act as capacitors. The first and second electrodes 13a and 13b are connected to the conductive via holes 16a and 16b of the adjacent third and fourth low dielectric constant layers 11c and 11d.

Preferably, buffer layers 19a and 19b may be employed between the first and second electrodes 13a and 13b and the third and fourth low dielectric constant layers 11c and 11d respectively formed in the capacitor region 12b. have. Ferroelectric materials, which are generally used, can diffuse certain elements into other adjacent layers, reducing reliability. For example, in the high dielectric constant layer made of BaTiO ₃ , Ba elements may be diffused through the first and second electrodes 13a and 13b to greatly reduce reliability. In order to prevent such an undesired diffusion, buffer layers 19a and 19b are introduced. In the case where the high dielectric constant layer is BaTiO ₃ , the buffer layers 19a and 19b are preferably BaTiO ₃ . The buffer layers 19a and 19b employed in the present invention are preferably 10 mu m or less, respectively, and preferably formed in a thickness of 5 mu m or more for sufficient diffusion preventing effect.

In addition, the high dielectric constant layer 12 includes a non-capacitor region 12a for connecting signal lines (particularly, conductive via holes 16a and 16b) of the third and fourth low dielectric constant layers 11c and 11d. . In general, since the signal leakage occurs in the high dielectric constant layer 12, it is required not to be directly connected to the signal line. To this end, at least one window region W having an open shape is formed in the non-capacitor region 12a. In addition, the window region W is formed to have a diameter d2 larger than the diameter d1 of the conductive via hole 16 passing through the window region W. FIG.

Meanwhile, among the conductive via holes formed in the third and fourth low dielectric constant layers 11c and 11d adjacent to the high dielectric constant layer 12, the conductive via holes 16a and 16b that pass through the non-capacitor region are filled with a window region ( It forms so that it may partially protrude toward W). As a result, the conductive via hole portions 16a and 16b of the third and fourth low dielectric constant layers 11c and 11d may be directly connected through the window region W without being directly connected to the high dielectric constant layers in the stack pressing process. have.

As will be apparent to those skilled in the art, five low dielectric constant layers are illustrated in the embodiment shown in FIG. 2A, but are not limited thereto. In addition, the high dielectric constant layer may be inserted at a position other than the third and fourth low dielectric constant layers.

3 is a cross-sectional view showing the capacitor-embedded LTCC laminated substrate 20 shown in FIG. 2A.

As shown in FIG. 3, the low temperature cofired ceramic substrate 20 for a package substrate includes first to fifth low dielectric constants having predetermined circuit patterns 14, 17a, and 17b and conductive via holes 15, 16, and 18. And a high dielectric constant layer 12 interposed between the layers 11a, 11b, 11c, 11d and 11e and the third and fourth low dielectric constant layers 11c and 11d. The semiconductor chips 21 and 25 may be mounted on the circuit pattern 14 formed on the first low dielectric constant layer 11a.

Meanwhile, as shown in FIG. 2A, the conductive via hole portions 16a and 16b formed in the third and fourth low dielectric constant layers 11c and 11d formed to pass through the non-capacitor region of the high dielectric constant layer 12 are via holes. Since it is formed to partially protrude toward the window area W having a diameter larger than the diameter of the, as shown in FIG. 3 during the stack pressing process, the conductive via hole penetrating through the high dielectric constant layer 12 is a high dielectric constant layer ( It may be directly connected through the window area W without being in contact with 12).

As a result, signal leakage due to the high dielectric constant layer can be solved by preventing signal lines from being connected to the high dielectric constant layer.

4 is a graph showing an effective impedance bandwidth of a conventional multilayer capacitor array and a LTCC laminated substrate with a capacitor according to the present invention.

As a conventional example, in the conventional manner described in Fig. 1, a 47 kHz capacity MLCC having a size of 0.6 × 0.5 mm was used.

According to the present invention, as shown in FIG. 3, a capacitor-embedded LTCC substrate was manufactured. Internal capacitors are designed to have similar capacitances. The size of the upper and lower electrode patterns for the capacitor was 12 × 12 mm and a BaTiO ₃ film having a thickness of 0.2 mm was used as the high dielectric constant layer. The measured capacitance value was 49.5 kV and it was confirmed to have a capacitance value similar to that of the conventional MLCC.

Subsequently, the effective impedance bandwidth of each capacitor for the conventional example and the invention example was measured.

As a result, compared with the effective impedance bandwidth of the conventional example, the capacitor-embedded LTCC substrate (b) was found to have an effective impedance bandwidth of 3 to 4 times larger. In addition, as a result of the ESL measurement, the conventional example was measured to 0.46nH, while the capacitor according to the present invention was confirmed to be reduced by more than three times to about 0.17nH.

These results can be expected to be due to the fact that the parasitic impedance effect is greatly reduced by implementing the capacitor using a high dielectric constant layer in the present invention. In addition, it can be confirmed that the signal leakage by the high dielectric constant layer is hardly generated.

In this way, the increase in the effective impedance bandwidth means that fewer capacitors of the same capacity can be used, so that the module size can be more easily reduced.

The above-described embodiments and the accompanying drawings are merely illustrative of preferred embodiments, and the present invention is intended to be limited by the appended claims. In addition, it will be apparent to those skilled in the art that the present invention may be substituted, modified, and changed in various forms without departing from the technical spirit of the present invention described in the claims.

As described above, according to the present invention, at least one layer is formed of a dielectric layer having a high dielectric constant to implement an embedded capacitor, and at the same time, a window area larger than the diameter of the conductive via hole in a specific region of the high dielectric constant layer used as the embedded capacitor. The present invention can solve the signal leakage problem caused by the connection of the high dielectric constant layer and the signal line (that is, the conductive via hole), and can reduce the parasitic inductance to provide a capacitor-embedded package substrate having a large effective impedance bandwidth.

Claims (5)

A plurality of low dielectric constant layers formed with a predetermined circuit pattern and conductive via holes and made of a low dielectric constant ceramic material; And A high dielectric constant layer interposed between the plurality of low dielectric constant layers, the first and second electrodes including a capacitor region having upper and lower surfaces and a non-capacitor region having at least one open window region; The conductive via holes formed in the two low dielectric constant layers adjacent to the high dielectric constant layers among the plurality of low dielectric constant layers have a diameter smaller than the diameter of the window region and are connected to each other through the window region. Ceramic laminated substrate. The method of claim 1, And a buffer layer formed on the first and second electrodes in order to prevent the elements of the high dielectric constant layer from diffusing to the adjacent low dielectric constant layers through the first and second electrodes. Built-in low temperature simultaneous firing ceramic laminated substrate. The method of claim 2, Capacitor-embedded low-temperature copper firing ceramic laminated substrate, characterized in that each buffer layer is 10㎛ or less. The method according to claim 1 or 2, The high dielectric constant layer is BaTiO ₃ Capacitor embedded low-temperature co-fired ceramic laminated substrate, characterized in that. The method of claim 4, wherein The buffer layer is BaTiO ₃ Capacitor embedded low-temperature simultaneous firing ceramic laminated substrate, characterized in that.

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