KR20070010854A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20070010854A KR20070010854A KR1020050065809A KR20050065809A KR20070010854A KR 20070010854 A KR20070010854 A KR 20070010854A KR 1020050065809 A KR1020050065809 A KR 1020050065809A KR 20050065809 A KR20050065809 A KR 20050065809A KR 20070010854 A KR20070010854 A KR 20070010854A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66174—Capacitors with PN or Schottky junction, e.g. varactors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/93—Variable capacitance diodes, e.g. varactors
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- Microelectronics & Electronic Packaging (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
도 1a 내지 도 1c 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 도시한 단면도. 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11 : 기판 12 : 소자분리막11
13 : 액티브 영역 14 : p형 웰13 active region 14 p-type well
15 : n형 웰 16 : p형 웰15: n-type well 16: p-type well
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 가변용량다이오드 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of forming a variable capacitance diode of a semiconductor device.
가변용량다이오드는 외부 전압에 의해 전기용량을 변화시킬 수 있는 바도체 다이오드로, 버랙터(Varactor)라고도 한다. p형 반도체와 n형 반도체를 접합시켜 만든 반도체 다이오드를 p-n 접합 반도체 다이오드라 하는데, 이것에 외부 전압을 걸지 않은 상태에서 p-n 접합면 가까이에서는 양반도체 사이에 전자와 정공이 서로 확산되어 전하가 중화되어서 가동전하가 없는 공핍층이 형성된다. 여기서 가동전하가 없는 공핍층은 절연체, 가동전하가 있는 공핍층의 양쪽은 금속과 같은 전기전도체에 해당하는 부분이므로, 이 반도체의 p-n 접합에 의해 만들어진 다이오드는 용량이 축적되는 소자인 콘덴서에 해당하는 것이라 생각할 수 있다.Variable-capacitance diodes are bar conductor diodes that can change their capacitance by an external voltage, also known as varactors. A semiconductor diode made by bonding a p-type semiconductor and an n-type semiconductor is called a pn junction semiconductor diode, and electrons and holes are diffused between the two semiconductors near the pn junction surface without an external voltage applied thereto, and the charge is neutralized. A depletion layer without moving charges is formed. Since the depletion layer without movable charge is an insulator and both sides of the depletion layer with movable charge are parts of an electric conductor such as a metal, the diode made by the pn junction of this semiconductor corresponds to a capacitor which is a device in which capacitance is accumulated. I can think of it.
이 다이오드에 p형 영역이 음전위, n형 영역이 양전위가 되는 방향으로 전압(역방향 바이어스 전압)을 가하면 정공은 음전위 부위에, 전자는 양전위 부위에 이동하기 때문에 공핍층은 더 넓어진다. 다시 말해서, 콘덴서의 양쪽 극판 사이의 거리가 증대되어서 축적 용량이 감소된다. 즉, 이 다이오드에서는 외부에서 가하는 직류바이어스 전압을 변동시킴으로써 공핍층 양쪽 극판 부위의 용량을 변동시킬 수 있다. 즉, p-n 접합 반도체다이오드는 가변용량다이오드로서 이용될 수 있다. p형 반도체 또는 n형 반도체의 불순물의 농도 기울기를 달리함으로써, 여러 전압-용량 특성의 가변용량다이오드를 만들 수 있다. 이들 가변용량다이오드는 텔레비전·라디오 등의 전자동조기 또는 동조의 어긋남을 자동적으로 보정하는 자동주파수제어에 사용된다. 이 밖에 주파수변조, 저잡음 파라메트릭증폭기 등 분야에서도 이용되고 있다.Applying a voltage (reverse bias voltage) in a direction in which the p-type region becomes negative potential and the n-type region becomes positive potential to the diode, the holes deplete further because holes move to the negative potential region and electrons move to the positive potential region. In other words, the distance between both pole plates of the capacitor is increased to reduce the storage capacity. That is, in this diode, the capacitance of both pole plate portions of the depletion layer can be changed by changing the DC bias voltage applied from the outside. That is, the p-n junction semiconductor diode can be used as a variable capacitance diode. By varying the concentration gradient of impurities of the p-type semiconductor or the n-type semiconductor, variable voltage diodes of various voltage-capacitance characteristics can be made. These variable capacitive diodes are used for automatic frequency control for automatically correcting deviations of an electronic tuner such as a television or a radio. Other applications include frequency modulation and low noise parametric amplifiers.
상술한 바와 같이, 일반적인 p-n 접합 가변용량다이오드는 p 형, n형 다이오드를 접합시켜 역전압바이어스를 인가하여 형성되는 절연층의 두께에 따라 변하는 캐패시턴스를 이용한다.As described above, a general p-n junction variable capacitance diode uses a capacitance that varies depending on the thickness of an insulating layer formed by applying p-type and n-type diodes to apply a reverse voltage bias.
한편, 접합 캐패시턴스가 증가함에 따라 조정능력(tunability)도 같이 증가하는 가변용량다이오드 특성 때문에 캐패시턴스를 증가시키기 위해서 접합 면적을 증가시켜야 하는데, 이를 위한 방법으로 핑거 타입의 p, n 접합을 교대로 만들거나 넓은 n형 접합을 형성하고, 가운데 p형 접합을 형성한 아일랜드 형(island type)이 이용되어 왔다.On the other hand, due to the variable capacitance diode characteristic of increasing tunability as the junction capacitance increases, the junction area should be increased to increase the capacitance. An island type in which a wide n-type junction is formed and a p-type junction is formed in the middle has been used.
그러나, 위와 같은 방법들은 소자가 차지하는 면적을 증가시켜 칩의 가격을 증가시키는 요인으로 작용해왔다.However, these methods have been a factor in increasing the price of the chip by increasing the area occupied by the device.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 캐패시턴스를 증가시켜 동조 특성을 향상시키는데 적합한 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device suitable for improving the tuning characteristics by increasing the capacitance.
상기 목적을 달성하기 위한 일 특징적인 본 발명의 반도체 소자 제조 방법은 반도체 기판의 내부에 제 1 도전형 웰을 형성하는 단계, 상기 제 1 도전형 웰 내부에 제 2 도전형 웰을 형성하는 단계, 및 상기 제 2 도전형 웰을 매립하도록 상기 제 1 도전형 웰과 같은 도전형의 제 3 도전형 웰을 형성하되 상기 제 1 도전형 웰과 상기 제 3 도전형 웰은 서로 연결되도록 형성하는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: forming a first conductive well in a semiconductor substrate, forming a second conductive well in the first conductive well, And forming a third conductive well of the same conductivity type as the first conductive well so as to fill the second conductive well, wherein the first conductive well and the third conductive well are connected to each other. Include.
또한, 본 발명은 반도체 기판, 상기 반도체 기판 내부에 형성된 제 1 도전형 웰, 및 상기 제 1 도전형 웰의 일정 깊이 내부에 매립된 형태로 형성된 상기 제 1 도전형 웰과 서로 다른 도전형의 제 2 도전형 웰이 형성된 구조를 제공한다.The present invention also provides a semiconductor substrate, a first conductivity type well formed in the semiconductor substrate, and a conductive material different from the first conductivity type well formed in a form embedded in a predetermined depth of the first conductivity type well. Provided is a structure in which two conductivity wells are formed.
이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .
도 1a 내지 도 1c는 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 1a에 도시된 바와 같이, 반도체 기판(11) 상에 STI(Shallow Trench Isolation) 법을 사용하여 소자분리막(12)을 형성한다.As shown in FIG. 1A, the
이어서, 반도체 기판(11)의 액티브 영역(13)에 p형 불순물을 도핑하여 일정 깊이 내부에 제 1 도전영역인 p형 웰(14)을 형성한다.Subsequently, the p-type impurity is doped into the
한편, p형 불순물은 B 또는 BF2를 사용한다.On the other hand, p-type impurity is a B or BF 2.
도 1b에 도시된 바와 같이, 제 1 도전영역인 p형 웰(14)이 형성된 반도체 기판(11)의 액티브 영역(13)에 n형 불순물을 도핑하여 p형 웰(14) 내부에 제 2 도전영역인 n형 웰(15)을 형성한다. 이 때, 제 2 도전영역인 n형 웰(15)은 제 1 도전영역인 p형 웰(14)의 내부에 매립되도록 형성하고, n형 웰(15)의 폭의 제한은 없지만 p형 웰(14)과 후속 공정에서 형성되는 제 3도전영역인 p형 웰(16)이 연결되어 하나의 콘택으로 이어지도록 형성한다. As shown in FIG. 1B, n-type impurities are doped into the
한편, n형 불순물은 P(인) 또는 Arsenic(아세닉)을 사용한다.On the other hand, n-type impurities use P (phosphorus) or Arsenic (acenic).
도 2c에 도시된 바와 같이, 반도체 기판(11)의 액티브 영역(13)에 p형 불순물을 도핑하여 n형 웰(15)을 매립하도록 제 3 도전 영역인 p형 웰(16)을 형성한다.As shown in FIG. 2C, the p-
한편, p형 불순물은 B 또는 BF2를 사용한다.On the other hand, p-type impurity is a B or BF 2.
상술한 바와 같이, n형 웰이 p형 웰의 내부에 매립되는 구조로 형성하기 때문에(PNP 구조) 칩 면적을 줄일 수 있고, p형 웰과 n형 웰의 접촉 면적이 증가하여 역바이어스 상태에서 n형 웰이 완전이 공핍되는 순간까지 캐패시턴스의 변화를 얻을 수 있고, 따라서 높은 조절능력을 얻을 수 있다.As described above, since the n-type well is formed into a structure embedded in the p-type well (PNP structure), the chip area can be reduced, and the contact area between the p-type well and the n-type well is increased, and in a reverse bias state. Capacitance change can be obtained until the n-type well is completely depleted, and thus high controllability can be obtained.
한편, NPN 구조로도 적용할 수 있다.On the other hand, it can also be applied to the NPN structure.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 조정능력이 큰 MOS 가변용량다이오드에 비해 낮은 튜닝 범위로 이용이 꺼려왔던 p-n 접합 가변용량다이오드의 단점을 개선하여 소자의 동작 특성을 향상시키는 효과를 얻을 수 있다.The present invention described above can improve the operating characteristics of the device by improving the shortcomings of the p-n junction variable capacitance diode, which has been reluctant to be used in a low tuning range, compared to the MOS variable capacitance diode having a large adjustment capability.
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