KR20070008234A - Semiconductor device comprising stacked transistor structure and method of manufacturing the same - Google Patents

Abstract

A semiconductor device including a stacked transistor structure is provided to form a quality polysilicon layer similar to a single crystal by using as a seed a single crystalline silicon layer with an orientation of formed as a silicon plug. A MOS is formed on a silicon substrate(40). The MOS transistor is covered with an interlayer dielectric(52). A thin film transistor with a fin channel is formed on the interlayer dielectric to be connected to the MOS transistor. The MOS transistor and the thin film transistor penetrate the interlayer dielectric, interconnected by a single crystalline silicon plug(56) with an orientation of . The thin film transistor includes at least two fin channels separated from each other.

Description

Semiconductor device comprising stacked transistor structure and method of manufacturing the same

1 is a perspective view of a semiconductor device including a stacked transistor structure according to an embodiment of the present invention.

2 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

9 through 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

12 and 13 are graphs showing the effect of the present invention.

* Explanation of symbols for main parts of drawings *

40: substrate 40a: silicon pillar

42, 44: First and second impurity regions

46: channel region 48: gate oxide film

50: gate electrode 52: interlayer insulating layer

54: contact hole 56, 80: silicon plug

58: amorphous silicon layer 58a, 58b: first and second portions

60a: crystalline silicon pad layer 60b: crystalline silicon fin

60: crystalline silicon layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a stacked transistor structure and a method for manufacturing the same.

As the Internet spreads widely along with the development of technology in all industries, various information can be obtained through the Internet. In such a situation, there is a demand for an information storage device capable of storing more information and processing more information quickly. Accordingly, nonvolatile memory devices such as flash memory, MRAM, FRAM, PRAM, and the like are introduced from volatile memory devices such as DRAM and SRAM, and variants thereof are also being developed.

Since the memory device includes basic elements such as transistors and capacitors or nonvolatile memory storage cells, it is necessary to increase the integration of these basic elements in order to store more information in the memory device. As a method, the integration of the memory device has been increased by reducing the area occupied by the basic devices in the memory device while maintaining the electrical characteristics of the basic devices. In recent years, the demand for memory devices having higher integration has increased. Instead of forming transistors constituting the basic elements, for example, CMOS elements, on a plane, they are stacked vertically to increase the degree of integration of the memory device. An example of this is a case where a MOS transistor is formed below and a thin film transistor (TFT) is formed above. At this time, the TFT is formed on the polysilicon layer.

By the way, although the size of the polysilicon layer has a large grain, not only has a random crystal direction, but also has crystal defects, the TFT is difficult to obtain the desired operating characteristics and the processing speed is not so high.

SUMMARY OF THE INVENTION The present invention has been made in an effort to improve the above-described problems of the related art, and to provide a semiconductor device including a stacked transistor including an upper transistor having a transistor formed on the basis of a high quality polysilicon layer similar to a single crystal. .

Another object of the present invention is to provide a method of manufacturing a semiconductor device including the multilayer transistor.

In order to achieve the above technical problem, the present invention has a MOS transistor formed on a silicon substrate, an interlayer insulating layer covering the MOS transistor and a fin channel, which is provided to be connected to the MOS transistor on the interlayer insulating layer. Provided is a semiconductor device comprising a thin film transistor.

The MOS transistor and the thin film transistor may be connected to a single crystal silicon plug penetrating the interlayer insulating layer and having a <100> direction.

The thin film transistor may include at least two fin channels spaced apart from each other.

The source region and the drain region of the phase thin film transistor may have different sizes.

In order to achieve the above technical problem, the present invention provides a method of forming a single crystal silicon pillar on a silicon substrate, forming a MOS transistor on the silicon substrate, and interlayer covering the MOS transistor on the silicon substrate around the silicon pillar. Forming an insulating layer, forming an amorphous silicon layer covering the upper surface of the silicon pillar on the interlayer insulating layer, a first portion and the first portion covering the amorphous silicon layer on the upper surface of the silicon pillar Patterning a second portion perpendicular to and having a fin shape, crystallizing the first and second portions, sequentially depositing a gate oxide film and a gate electrode on a portion of the crystallized second portion; And injecting conductive impurities into the crystallized first and second portions. A method for manufacturing a semiconductor device is provided.

In this manufacturing method, the silicon pillar may be formed by etching the silicon substrate to a predetermined thickness.

According to another aspect of the present invention, there is provided a method of forming a MOS transistor on a silicon substrate, forming an interlayer insulating layer covering the MOS transistor on the silicon substrate, and forming the MOS transistor on the interlayer insulating layer. Forming an exposed contact hole, filling the contact hole with a silicon plug, forming an amorphous silicon layer covering the top surface of the silicon plug on the interlayer insulating layer, and forming the amorphous silicon layer on the silicon pillar Patterning a first portion covering an upper surface and a second portion perpendicular to the first portion and having a fin shape, crystallizing the first and second portions, on a portion of the crystallized second portion Sequentially depositing a gate oxide film and a gate electrode and applying conductive impurities to the crystallized first and second portions. It provides a method for manufacturing a semiconductor device comprising the step of injecting.

In this case, the silicon plug may be formed by growing an area exposed through the contact hole of the silicon substrate by an epitaxial method.

In the manufacturing methods, the crystallization of the first and second portions may be performed by irradiating an excimer laser light to the first and second portions.

At least two second portions may be formed and spaced apart from each other.

Using this invention, a polysilicon layer of high quality similar to a single crystal can be obtained by using a single crystal silicon layer in the <100> direction as a seed. In the stacked transistor structure, the source, drain, and channel regions of the upper TFT, which is the upper transistor, are patterned in such a way that the polysilicon layer is used to increase the operating speed of the semiconductor device.

Hereinafter, a semiconductor device having a stacked transistor according to an exemplary embodiment of the present invention and a method of manufacturing the same will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.

First, a semiconductor device (hereinafter referred to as the device of the present invention) including a stacked transistor according to an embodiment of the present invention will be described.

Referring to FIG. 1, first and second impurity regions 42 and 44 into which a predetermined conductive impurity is injected are present in the silicon substrate 40. The first and second impurity regions 42 and 44 are spaced apart from each other with the channel region 46 interposed therebetween. One of the first and second impurity regions 42 and 44 may be a source region and the other may be a drain region. The gate oxide film 48 and the gate electrode 50 are sequentially stacked on the channel region 46 of the silicon substrate 40. The first and second impurity regions 42 and 44, the channel region 46, and the gate electrode 50 constitute a MOS transistor. An interlayer insulating layer 52 covering the MOS transistor is formed on the silicon substrate 40. The interlayer insulating layer 52 may be a silicon oxide film or another insulating film. A contact hole 54 through which the first impurity region 42 is exposed is formed in the interlayer insulating layer 52, and the contact hole 54 is filled with the silicon plug 56. Silicon plug 56 may be a single crystal silicon plug having a (100) plane. On the interlayer insulating layer 52 is a crystalline silicon layer 60 covering the top surface of the silicon plug 56. The crystalline silicon layer 60 may be a polysilicon layer having a grain structure similar to a single crystal. The crystalline silicon layer 60 includes a crystalline silicon pad layer 60a and a plurality of crystalline silicon fins 60b vertically connected thereto. The crystalline silicon pad layer 60a is a portion covering the upper surface of the silicon plug 56, and the plurality of crystalline silicon fins 60b are spaced apart from each other. The plurality of crystalline silicon fins 60b has a fin structure, literally, in which the height T is higher than the width W. FIG. The ratio of the height T to the width W is about 0.1 to about 100. The plurality of crystalline silicon fins 60b includes a source region s and a drain region d, and includes a channel region positioned between the source and drain regions s and d. A gate oxide layer 62 is formed on the interlayer insulating layer 52 to cover the channel region of the crystalline silicon fin 60b. The gate oxide film 62 is formed in a direction perpendicular to the crystalline silicon fins 60b. The gate electrode 64 is formed on the gate oxide film 62. The crystalline silicon fin 60b, the gate oxide film 62, and the gate electrode 64 constitute a thin film transistor (Fin TFT) having a fin channel as an upper transistor.

Next, the manufacturing method for the above-described device of the present invention will be described.

<First Embodiment>

Reference is made to FIGS. 2 to 8. In each of FIGS. 2 to 8, (a) is a cross-sectional view of FIG. 1 cut in the 2-2 'direction, and (b) is a plan view of FIG. 1 viewed from above.

First, referring to FIG. 2, a single crystal silicon pillar 40a is formed on a predetermined region of the silicon substrate 40. The pillar 40a is used as a silicon plug, and forms a photoresist pattern on the upper surface of the silicon substrate 40 having the same height as the silicon pillar 40a to define a region where the silicon pillar 40a is to be formed. The silicon substrate 40 may be formed by etching the silicon substrate 40 to the same depth as the silicon pillar 40a using the etching mask. After the etching, the photoresist pattern is removed.

Referring to FIG. 3, the gate oxide film 48 and the gate electrode 50 are sequentially stacked on a predetermined region spaced apart from the silicon pillar 40a of the silicon substrate 40. Conductive impurities, such as n-type conductive impurities, are implanted into the upper surface of the silicon substrate 40 on which the gate electrode 50 is formed. As a result, the first impurity region 42 is formed in the region including the silicon pillar 40a of the silicon substrate 40, and corresponds to the width of the gate electrode 50, that is, the channel length, from the first impurity region 42. The second impurity region 44 is formed at a spaced apart distance.

Next, referring to FIG. 4, an interlayer insulating layer 52 covering the silicon pillar 40a is formed on the silicon substrate 40. The interlayer insulating layer 52 may be formed of a silicon oxide film, or may be formed of another insulating material, for example, BPSG. The upper surface of the interlayer insulating layer 52 is polished until the silicon pillar 40a is exposed.

Subsequently, as shown in FIG. 5, the amorphous silicon layer 58 is formed on the interlayer insulating layer 52 to have a predetermined thickness.

Next, as shown in FIG. 6, the amorphous silicon layer 58 is a plurality of agents perpendicular to the first portion 58a and the first portion 58a covering the upper surface of the silicon pillar 40a and having a predetermined length. Two portions 58b are formed. The second portions 58b are spaced apart from each other. After the amorphous silicon layer 58 is patterned in this manner, the excimer laser light L is irradiated to the first and second portions 58a and 58b for a predetermined time. Lateral crystallization proceeds from the silicon pillar 40a by irradiation of the excimer laser light L. As a result, as shown in FIG. 7, the first portion 58a is formed on the interlayer insulating layer 52. A crystalline silicon layer 60 is formed that includes the crystalline silicon pad layer 60a that is the result of crystallization of crystalline silicon and the crystalline silicon fin 60b that is the result of crystallization of the second portion 58b.

Next, referring to FIG. 8, the gate oxide layer 62 and the gate electrode 64 covering a portion of the crystalline silicon fin 60b are sequentially stacked on the interlayer insulating layer 52. The region formed under the gate electrode 64 of the crystalline silicon fin 60b is used as the channel region. After the gate electrode 64 is formed, the conductive impurity 70 is ion implanted into the crystalline silicon fin 60b using the gate electrode 64 as a mask. As a result, the source and drain regions s and d are formed in the crystalline silicon fin 64b. In this way, a thin film transistor having a fin channel is formed on the interlayer insulating layer 52.

Second Embodiment

The same reference numerals are used for the same members as in the first embodiment.

Referring to FIG. 9, first and second impurity regions 42 and 44 are formed in a silicon substrate 40, and a gate oxide film is formed on the substrate 40 between the first and second impurity regions 42 and 44. 48 and the gate electrode 50 are formed sequentially.

Referring to FIG. 10, a contact hole h1 exposing the first impurity region 42 is formed in the interlayer insulating layer 52. Then, as illustrated in FIG. 11, a silicon plug (I) is formed in the contact arc h1. 80). The silicon plug 80 is a single crystal silicon layer in a <100> direction and may be formed by growing an exposed portion of the silicon substrate 40 through the contact hole h1 by an epitaxial method. The subsequent process is according to the first embodiment.

12 and 13 show the current-voltage characteristics and the threshold voltage change according to the gate length for the TFT having the fin channel of the present invention and the TFT using the conventional low temperature forming polysilicon layer (LTPS), respectively.

In Fig. 12, the first graph G1 shows the current-voltage characteristic according to the present invention, and the second graph G2 shows the current-voltage characteristic for the conventional TFT.

Comparing the first and second graphs G1 and G2 of FIG. 12, it can be seen that the TFTs of the present invention have lower threshold voltages than the conventional TFTs, and the threshold voltages can be more clearly distinguished from the inclination of the graphs. Can be.

In Fig. 13, the first graph GG1 is for the TFT of the present invention, and the second graph GG2 is for the conventional TFT.

Comparing the first and second graphs GG1 and GG2 of FIG. 13, in the case of the present invention, the threshold voltage according to the gate length is almost constant, whereas in the conventional case, the threshold voltage also increases with the gate length. have. From these results, it can be seen that the present invention is much better in improving the short channel effect than the conventional TFT.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, one of ordinary skill in the art may replace the type of the lower transistor and the upper transistor with another one. In addition, the conditions for forming the silicon plug may be different, and a patterning process may be performed after crystallization of the amorphous silicon layer after the amorphous silicon layer is formed. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, the present invention can obtain a polysilicon layer of high quality similar to a single crystal by using a single crystal silicon layer in the <100> direction formed of a silicon plug as a seed. In the stacked transistor structure, the source, drain, and channel regions of the upper TFT, which is the upper transistor, are patterned in such a way that the polysilicon layer is used to increase the operating speed of the semiconductor device.

Claims (12)

Silicon substrates; A MOS transistor formed on the silicon substrate; An interlayer insulating layer covering the MOS transistor; And And a thin film transistor having a fin channel provided on the interlayer insulating layer so as to be connected to the MOS transistor. The semiconductor device of claim 1, wherein the MOS transistor and the thin film transistor are connected to each other by a single crystal silicon plug penetrating the interlayer insulating layer and having a <100> direction. The semiconductor device of claim 1, wherein the thin film transistor comprises at least two fin channels spaced apart from each other. The semiconductor device according to claim 1, wherein a size of a source region and a drain region of the thin film transistor is different. Forming a single crystal silicon pillar on the silicon substrate; Forming a MOS transistor on the silicon substrate; Forming an interlayer insulating layer covering the MOS transistor on the silicon substrate around the silicon pillar; Forming an amorphous silicon layer on the interlayer insulating layer to cover an upper surface of the silicon pillar; Patterning the amorphous silicon layer into a first portion covering an upper surface of the silicon pillar and a second portion perpendicular to the first portion and having a fin shape; Crystallizing the first and second portions; Sequentially depositing a gate oxide film and a gate electrode on a portion of the crystallized second portion; And And injecting conductive impurities into the crystallized first and second portions. The method of claim 5, wherein the silicon pillar is formed by etching the silicon substrate by a predetermined thickness. The method of claim 5, wherein the crystallization of the first and second portions is performed by irradiating excimer laser light to the first and second portions. The method of claim 5, wherein at least two second portions are formed and spaced apart from each other. Forming a MOS transistor on the silicon substrate; Forming an interlayer insulating layer covering the MOS transistor on the silicon substrate; Forming a contact hole in the interlayer insulating layer to expose the MOS transistor; Filling the contact hole with a silicone plug; Forming an amorphous silicon layer on the interlayer insulating layer to cover an upper surface of the silicon plug; Patterning the amorphous silicon layer into a first portion covering an upper surface of the silicon pillar and a second portion perpendicular to the first portion and having a fin shape; Crystallizing the first and second portions; Sequentially depositing a gate oxide film and a gate electrode on a portion of the crystallized second portion; And And injecting conductive impurities into the crystallized first and second portions. The method of claim 9, wherein the silicon plug is formed by growing an exposed portion of the silicon substrate through the contact hole by an epitaxial method. The method of claim 9, wherein the first and second portions are crystallized by irradiating excimer laser light to the first and second portions. The method of claim 9, wherein at least two second portions are formed and spaced apart from each other.

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