KR20070008024A - Cmos device and method of manufacturing the same - Google Patents

Abstract

A CMOS device is provided to improve integration by including a stacked structure in which an n-MOS transistor and a p-MOS transistor are vertically stacked. An n-type transistor is formed on a silicon substrate(30) whose upper surface is (100). The silicon substrate is a part of an SOI substrate. The n-type transistor is covered with an interlayer dielectric(40). A p-type transistor is formed on the interlayer dielectric. The channel of the n-type transistor is , and the channel of the p-type transistor is . The p-type transistor can be a p-MOS FET or a p-MOS FinFET(T2).

Description

CMOS device and its manufacturing method {CMOS device and method of manufacturing the same}

1 is a cross-sectional view of a CMOS device according to an embodiment of the present invention.

2 is a plan view of a CMOS device according to an embodiment of the present invention.

3 to 10 are cross-sectional views showing step-by-step method of manufacturing a CMOS device according to an embodiment of the present invention.

FIG. 11 is a stereoscopic view showing only the pin pet separated from FIG. 10.

FIG. 12 is a stereoscopic view showing the result of excluding the gate stack in FIG. 11.

13 to 16 are cross-sectional views illustrating various modifications of the manufacturing method illustrated in FIGS. 3 to 10.

* Explanation of symbols for main parts of drawings *

30: Substrate 32, 34: n-type first and second impurity regions

35: channel region 36, 70: gate oxide film

38: gate electrode 40: interlayer insulating layer

42a: Finned crystalline silicon layer

48, 70: First part 50, 72: Second part

50: silicon plug 52, 100: amorphous silicon layer

62: insulating films 52a, 52c: first and second crystalline silicon layers

80: p-type conductive impurity 70a, 70b, 72a, 72b: first to fourth regions

90: crystalline silicon layer C1: channel region

GS: Gate laminate P1: Photoresist pattern

T1: n-MOS Transistor T2: p-MOS Pin Fet (Fin FET)

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a CMOS device and a method for manufacturing the same.

The widespread use of the Internet and various communication equipment has made it easier for the public to use information. As a result, the amount of information available to the general public is increasing rapidly. In line with this trend, various electronic products have been provided with increased data processing capacity and improved processing speed. Since such electronic products are based on semiconductor technology, the data processing capacity and processing speed of electronic products may ultimately depend on the development of semiconductor technology.

Important issues related to the development of semiconductor technology are the integration and processing speed of semiconductor devices, especially memory devices. Memory devices include transistors and various data storage means such as capacitors, MTJ cells, phase change layers, etc. as basic elements. Therefore, in order to increase the integration degree of the memory device, it is necessary to form these basic elements as much as possible in the unit area, and to increase the processing speed of the memory device, the carrier speed in the basic elements should be increased.

From this point of view, various methods for increasing the density and processing speed of a memory device have been introduced, and one of them uses a transistor having a fin channel, that is, a fin FET, instead of a transistor formed on a plane. .

Since the fin pet has a three-dimensional structure while the conventional transistor is a planar structure, it can be formed in a narrower area than the conventional transistor, and can flow more current through the fin channel. In addition, a method of vertically stacking devices, using an SOI substrate, and using channel engineering are introduced as a method for improving the integration density and processing speed of a memory device while maintaining current design rules.

On the other hand, the processing speed of the memory device depends on the carrier mobility in the basic elements. Carrier mobility is closely related to the crystal direction of the substrate on which the basic element is formed. In other words, in the case of an n-MOS transistor, it is formed on the (100) plane of the silicon substrate, and the carrier mobility is optimal when the channel direction is the <100> direction. And, in the case of the p-MOS transistor, formed on the (110) plane of the silicon substrate, when the channel direction is <110>, the carrier mobility is optimal.

Accordingly, in the example of the conventional CMOS device fabrication method, when the n-MOS and p-MOS transistors are formed on the (100) plane of the silicon substrate, the carrier mobility is optimized in the channel direction of each transistor. It was formed in one crystal direction. As a result, the channel direction of the p-MOS transistor and the channel direction of the n-MOS transistor are opened at a predetermined angle.

In another example of the conventional CMOS device fabrication method, after bonding two substrates having different crystal planes, holes are formed in the upper substrate to expose the lower substrate, and the portions exposed through the holes of the lower substrate are formed. Grow to the same height as the surface of the upper substrate Thereafter, one of n-MOS and p-MOS transistors is formed on the upper substrate, and the remaining transistors are formed in a portion grown at the same height as the upper substrate of the lower substrate.

 Such a conventional CMOS fabrication method is a new CMOS fabrication method that has not existed previously. However, since both transistors are formed on the same plane, it is difficult to obtain a desired integration density due to low integration. In addition, bonding of silicon substrates having different crystal planes is not so easy. In addition, the CMOS manufacturing method according to the prior art still does not deviate from the framework of the conventional CMOS manufacturing method, there are inherent difficulties with the conventional CMOS manufacturing method.

The technical problem to be achieved by the present invention is to improve the above-described problems of the prior art, it is possible to improve the process difficulties of the conventional CMOS device manufacturing method, and to improve the integration and carrier mobility CMOS device In providing.

Another object of the present invention is to provide a method of manufacturing such a CMOS device.

In order to achieve the above technical problem, the present invention includes an n-type transistor formed on a silicon substrate having an upper surface (100), an interlayer insulating layer covering the n-type transistor, and a p-type transistor formed on the interlayer insulating layer. However, the n-type transistor provides a CMOS device, characterized in that the channel is formed in the <100> direction, the p-type transistor is formed in the channel <110> direction.

In the CMOS device, the silicon substrate may be part of an SOI substrate.

The p-type transistor may be a p-MOS field effect transistor or a p-MOS fin FET.

In order to achieve the above technical problem, the present invention provides a first step of forming an n-type transistor on a silicon substrate having an upper surface (100), and forming an interlayer insulating layer covering the n-type transistor on the silicon substrate. And a third step of forming a p-type transistor on the interlayer insulating layer, wherein the n-type transistor forms a channel in a <100> direction, and the p-type transistor forms a channel in a <110> direction. It provides a CMOS device manufacturing method characterized in that formed.

In the manufacturing method, the n-type transistor may be an n-MOS field effect transistor.

In addition, the p-type transistor may be a p-MOS field effect transistor or a p-MOS pint.

When the p-type transistor is the p-MOS fin, the third step is a third step of forming a crystalline silicon layer on the interlayer insulating layer, patterning the crystalline silicon layer to form a fin on the interlayer insulating layer Step 3B of forming a crystalline silicon layer pattern, Step 3C of sequentially forming a gate oxide film and a gate electrode on a region to be used as a channel of the crystalline silicon layer pattern, and except for a region to be used as the channel in the crystalline silicon pattern The method may further include a 3D step of implanting the p-type conductive impurity into the region. In this case, the step 3A may include forming a contact hole in which the substrate is exposed in the interlayer insulating layer, filling the contact hole with a silicon plug, and forming an amorphous silicon layer covering the silicon plug on the interlayer insulating layer. Converting the amorphous silicon layer into a first crystalline silicon layer, forming a second crystalline silicon layer on the first crystalline silicon layer, and forming an insulating film on the second crystalline silicon layer. It may further include.

The 3B step may include forming a photoresist pattern defining the fin crystalline silicon layer pattern on the insulating layer, and using the photoresist pattern as an etching mask, the insulating layer, the second crystalline silicon layer, and the first crystalline layer. The method may further include sequentially etching the silicon layer and removing the photoresist pattern.

The second crystalline silicon layer may be formed by growing the first crystalline silicon layer by a homo epitaxy method.

The silicon plug may be formed by growing a portion exposed through the contact hole of the substrate by a selective epitaxy method.

The amorphous silicon layer may be converted into the first crystalline silicon layer by irradiating an excimer laser light.

The p-type conductive impurity may be implanted with ion implantation.

According to another embodiment of the present invention, the step 3A may include forming a contact hole in which the substrate is exposed in the interlayer insulating layer, and forming the crystalline silicon layer filling the contact hole on the interlayer insulating layer. And planarizing the crystalline silicon layer to a predetermined thickness.

According to another embodiment of the present invention, the step 3A may include forming a contact hole in which the substrate is exposed in the interlayer insulating layer, filling the contact hole with a silicon plug, and forming the silicon on the interlayer insulating layer. The method may further include forming an amorphous silicon layer covering the plug at the same height as the pin-shaped crystalline silicon layer pattern and irradiating an excimer laser light to the amorphous silicon layer. In this case, the silicon plug may be formed by growing a portion exposed through the contact hole of the substrate by a selective epitaxy method.

The substrate may be part of an SOI substrate.

 Using the present invention, since the n-MOS transistor and the p-MOS pint have a vertically stacked structure, the degree of integration can be increased. Also, in the vertical stacked structure, the channels of the n-MOS transistor and the p-MOS fin are formed in a crystal direction in which carrier mobility can be optimized, thereby obtaining an optimum operating speed. In addition, since the n-MOS transistor and the p-MOS fin are formed in different material layers, the use of a mask related to doping, as in the conventional CMOS process, is unnecessary, thereby simplifying the process.

Hereinafter, a CMOS device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.

First, a CMOS device (hereinafter, referred to as the device of the present invention) according to an embodiment of the present invention will be described.

In the device of the present invention, an n-MOS transistor and a p-MOS fin (FET) are sequentially stacked, and the p-MOS fin is formed on a material layer different from the substrate on which the n-MOS transistor is formed. It is done.

Specifically, referring to FIG. 1, first and second impurity regions 32 and 34 exist on the substrate 30. The substrate 30 is preferably a silicon substrate having an upper surface of (100), but may also be an SOI substrate. The first and second impurity regions 32 and 34 are spaced apart from each other, and each region is doped with n-type conductive impurities. The first and second impurity regions 32, 34 extend from the surface of the substrate 30 to a given depth. One of the first and second impurity regions 32 and 34 is a source region and the other is a drain region. The first and second impurity regions 32 and 34 are formed in the <100> direction. Therefore, the direction in which the channel region 35 connecting the first and second impurity regions 32 and 34 is formed is a <100> direction. The gate oxide film 36 and the gate electrode 38 are sequentially stacked on the substrate 30 between the first and second impurity regions 32 and 34. The first and second impurity regions 32 and 34 and the gate electrode 38 are formed on the (100) plane, and constitute the n-MOS transistor T1 in which the channel region 35 is formed in the <100> direction. . An interlayer insulating layer 40 covering the n-MOS transistor T1 is formed on the substrate 30. The interlayer insulating layer 40 may be, for example, a silicon oxide film (SiO 2). Finned crystalline silicon layer 42a is present on the interlayer insulating layer 40. This layer 42a may be a polysilicon layer and is divided into first and second impurity regions doped with p-type conductive impurities and a fin channel region located between these regions. An insulating film 44 is formed on the fin crystalline silicon layer 42a. The insulating film 44 may be a silicon oxide film and may have a thickness equivalent to that of the gate oxide film 36 of the n-MOS transistor T1. The insulating film 44 is covered with the pin gate electrode 46. The crystalline silicon layer 42a, the insulating film 44, and the fin gate electrode 46 in the form of a fin are some of the elements constituting the p-MOS finpet. In addition, the pin-shaped crystalline silicon layer 42a is formed in the <110> direction based on the substrate 30. In the substrate 30 having the upper surface as the (100) plane, the <100> direction and the <110> direction form a predetermined angle, for example, 45 degrees. Accordingly, the angle between the channel region 35 of the n-MOS transistor T1 formed in the <100> direction and the fin crystalline silicon layer 42a formed in the <110> direction is about 45 degrees. This can be clearly seen by referring to Fig. 2 showing the device of the present invention from above, that is, a planar configuration. Since the channel region 35 and the crystalline silicon layer 42a in the form of fins are opened at an angle of about 45 degrees, the channel region 35 and the crystalline silicon layer 42a in the form of fins are shown together in the same cross section. Can't. However, FIG. 1 shows the channel region 35 and the fin crystalline silicon layer 42a in the same cross section for convenience of understanding the structure of the device of the present invention. This illustration also applies to the manufacturing method. FIG. 1 is a cross-sectional view illustrating a part of the p-MOS finpet shown in FIG. 1, and FIG. 2 is cut in the 2b-2b 'direction, and the cross-section of the n-MOS transistor T1 is taken in the 2a-2a' direction. will be.

Subsequently, referring to FIG. 2, it can be seen that the gate electrode 46 of the p-MOS fin FET T2 covers only a part of the fin crystalline silicon layer 42a. A portion of the fin crystalline silicon layer 42a covered with the gate electrode 46 is a fin channel region. The crystalline silicon layer 42a in the form of a fin includes first and second portions 48 and 50 facing the gate electrode 46. The first and second portions 48 and 50 are first and second impurity regions doped with p-type conductive impurities, respectively, one portion may be a source region and the other portion may be a drain region.

Next, the manufacturing method for the above-described device of the present invention will be described.

Referring to FIG. 3, first and second impurity regions 32 and 34 are spaced apart from the silicon substrate 30. The first and second impurity regions 32 and 34 may be formed by implanting n-type conductive impurities in a conventional ion implantation process. In this case, the first and second impurity regions 32 and 34 are formed in the <100> direction. One of the first and second impurity regions 32 and 34 is a source region, and the other is used as a drain region. Therefore, the predetermined region 35 of the substrate 30 between the first and second impurity regions 32 and 34 becomes a channel region. Hereinafter, the predetermined region 35 is called a channel region. Since the first and second impurity regions 32 and 34 are formed in the <100> direction, the channel region 35 is also formed in the <100> direction.

Subsequently, the gate oxide film 36 and the gate electrode 38 are sequentially formed on the channel region 35 of the substrate 30. The gate oxide film 36 may be formed of a silicon oxide film. The gate electrode 38 may be formed of a metal, a metal silicide, or a material doped with conductive impurities. By forming the gate electrode 38 in this manner, the n-MOS transistor T1 is formed on the substrate 30.

Next, referring to FIG. 4, an interlayer insulating layer 40 covering the gate electrode 38 and the gate oxide film 36 is formed on the substrate 30 to have a predetermined thickness, and the surface thereof is planarized. The interlayer insulating layer 40 may be formed of a silicon oxide film, but may be formed of another insulating material layer such as BPSG. A contact hole h1 through which a portion of the substrate 40 is exposed is formed in the interlayer insulating layer 40.

Next, as shown in FIG. 5, the silicon plug 50 having the contact hole h1 (100) surface is filled. The silicon plug 50 may be formed by growing a portion exposed through the contact hole h1 of the substrate 30 using a selective epitaxy process. An amorphous silicon layer 52 covering the silicon plug 50 is formed on the interlayer insulating layer 40. Subsequently, a crystallization process is performed on the amorphous silicon layer 52. As an example of the crystallization process, the excimer laser light L may be irradiated onto the amorphous silicon layer 52. As a result of the crystallization process, the amorphous silicon layer 52 becomes the first crystalline silicon layer 52a as shown in FIG.

Next, referring to FIG. 7, the second crystalline silicon layer 52c is formed on the first crystalline silicon layer 52a using the first crystalline silicon layer 52a as a seed layer. The second crystalline silicon layer 52c is formed by growing the first crystalline silicon layer 52a by a predetermined thickness by a silicon homo epitaxy method. Therefore, the second crystalline silicon layer 52c is the same as the first crystalline silicon layer 52a so that there is no boundary between the first and second crystalline silicon layers 52a and 52c. In FIG. 7, dotted lines 60 separating the first and second crystalline silicon layers 52a and 52c are written for convenience. The first and second crystalline silicon layers 52a and 52c form one crystalline silicon layer 42. Subsequently, an insulating film 62 is formed on the crystalline silicon layer 42. The insulating film 62 can be formed of a silicon oxide film.

Next, referring to FIG. 8, a photosensitive film pattern P1 defining a region where a fin channel is to be formed is formed on the insulating layer 62. The insulating layer 62 and the crystalline silicon layer 42 are sequentially etched using the photoresist pattern P1 as an etching mask. The etching is performed until the interlayer insulating layer 40 is exposed. As a result of the etching, as shown in FIG. 9, a crystalline silicon layer 42a in the form of a fin is formed on the interlayer insulating layer 40. After the etching, the photoresist pattern P1 is removed from the resultant of FIG. 9.

Meanwhile, in the process of forming the crystalline silicon layer 42a in the fin form, the crystalline silicon layer 42a in the fin form is preferably formed in the <110> direction, and in the silicon substrate 30 having the (100) plane, Since the <110> direction forms an angle of about 45 degrees with the <100> direction of the channel region 35, when the photosensitive film pattern P1 for forming the fin-shaped crystalline silicon layer 42a is formed, the photosensitive film pattern P1 is preferably formed in a direction inclined at about 45 degrees with respect to the direction in which the channel region 35 is formed, or at another angle having the same inclination. When such formation conditions are maintained, the position where the crystalline silicon layer 42a in the form of fin is formed on the interlayer insulating layer 40 is arbitrary. In other words, the crystalline silicon layer 42a in the form of a fin may be formed so as to be positioned directly above the gate electrode 38 as shown in FIG. 9, and as shown in FIG. 2, the position spaced apart from the gate electrode 38. It can also be formed on the interlayer insulating layer 40 of.

Subsequently, after the photosensitive film pattern P1 is removed, as shown in FIG. 10, the gate oxide film 70 is formed on the crystalline silicon layer 42a having a fin shape and the insulating film 62. Subsequently, a gate electrode 46 is formed on the gate oxide film 70. The gate oxide film 70 may be formed of a silicon oxide film, but may be formed of another equivalent insulating film. The gate electrode 47 may be formed of a metal, a metal silicide, or a material doped with conductive impurities. After the gate electrode 46 is formed, the p-type conductive impurity 80 is ion implanted into the crystalline silicon layer 42a having a fin shape. The ion implantation 80 is for forming p-type first and second impurity regions to be used as source or drain regions in the crystalline silicon layer 42a in the fin form. Such ion implantation may be performed by injecting the p-type conductive impurity at an angle smaller than 90 degrees with respect to the upper surface of the interlayer insulating layer 40. To this end, the substrate 30 may be tilted at the angle, or the ion implantation equipment may be tilted at the angle. The ion implantation is implanted only in a portion of the crystalline silicon layer 42a in the form of a fin. 11 shows this more clearly. Specifically, FIG. 11 includes a fin crystalline silicon layer 42a formed in the <110> direction in the resultant of FIG. 10, and a stack GS including the gate oxide layer 70 and the gate electrode 46. Show the three-dimensional appearance of the p-MOS pinpet. Referring to FIG. 11, the incident ion implantation of the p-type conductive impurity 80 is performed on the entire vertical plane of the crystalline silicon layer 42a in the form of fin, but the gate electrode of the crystalline silicon layer 42a in the form of a fin is formed. The conductive impurity is not injected into the portion covered with the gate stack GS including the 46 (this portion is a channel). As a result, the p-type conductive impurity 80 is implanted only into the first and second portions 48 and 50 of the crystalline silicon layer 42a in the form of fins not covered with the gate stack GS. After the ion implantation, the first portion 48 becomes the p-type first impurity region and may be used as the source region. The second portion 50 becomes the p-type second impurity region and may be used as a drain region.

FIG. 12 shows a three-dimensional appearance of the pinned crystalline silicon layer 42a in which the stack GS is removed in FIG. 11 after the ion implantation, that is, the p-type conductive impurity 80 is ion-implanted. Referring to FIG. 12, it can be seen that the fin channel C1 is provided between the first and second portions 48 and 50 of the crystalline silicon layer 42a having a fin shape.

In the manufacturing method for the device of the present invention described above, the first and second portions 48 and 50 of the crystalline silicon layer 42a in the form of fins can be deformed in the form of straight lines having the same width. 13 shows an example.

Referring to FIG. 13, the first and second portions 70 and 72 of the crystalline silicon layer 42b in the fin form are symmetrical with respect to the gate electrode 46 and include portions having different widths. Specifically, the first portion 70 includes a first region 70a and a second region 70b that is wider than the first region 70a. The second portion 72 includes a third region 72a corresponding to the first region 70a and a fourth region 72b corresponding to the second region 70b.

In addition, the crystalline silicon layer 42 of FIG. 7 may be formed by a method different from that described above. As a first example, as shown in FIG. 14, a crystalline silicon layer 90 having a (100) surface filling the contact hole h1 is formed on the interlayer insulating layer 40. The crystalline silicon layer 90 may be formed by growing a portion exposed through the contact hole h1 of the substrate 30 by a selective epitaxy process. At this time, the crystalline silicon layer 90 is preferably grown to a thickness corresponding to the crystalline silicon layer 42 of FIG. When the crystalline silicon layer 90 is formed as described above, the above-described manufacturing method omits the process of forming the amorphous silicon layer 52, the excimer laser light L irradiation process, and the process of forming the second crystalline silicon layer 52c. can do. As a second example, as shown in FIG. 15, an amorphous silicon layer 100 having a predetermined thickness covering the upper surface of the silicon plug 50 is laminated on the interlayer insulating layer 40. The thickness of the amorphous silicon layer 100 is formed to correspond to the thickness of the crystalline silicon layer 42 of FIG. 7. Next, the excimer laser light L is irradiated to the amorphous silicon layer 100. The excimer laser light L is irradiated until the amorphous silicon layer 100 becomes the crystalline silicon layer 100a as shown in FIG. 16. In the second example, the process of forming the second crystalline silicon layer 52c may be omitted in the above-described manufacturing method.

On the other hand, in the CMOS device of the present invention, the p-MOS pint may be replaced with a p-MOS transistor.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, one of ordinary skill in the art to which the present invention pertains may configure various logic devices using the CMOS devices as described above. In addition, the conditions of each step of the manufacturing method may be modified. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, in the CMOS device of the present invention, the n-MOS transistor and the p-MOS pin-pet have a vertically stacked structure. Therefore, the degree of integration can be increased by using the present invention. In the vertical stacked structure, channels of the n-MOS transistor and the p-MOS fin are formed in a crystal direction in which carrier mobility may be optimal. Therefore, using the present invention can also increase the operating speed. In addition, since the n-MOS transistor and the p-MOS fin are formed in different material layers, the use of a mask related to doping is unnecessary as in the conventional CMOS process, thereby simplifying the process. In addition, in the case of the CMOS device of the present invention, a bonding step is not necessary.

Claims (17)

A silicon substrate having an upper surface of (100); An n-type transistor formed on the silicon substrate; An interlayer insulating layer covering the n-type transistor; And A p-type transistor formed on the interlayer insulating layer, And the n-type transistor has a channel formed in a <100> direction, and the p-type transistor has a channel formed in a <110> direction. The CMOS device of claim 1, wherein the silicon substrate is part of an SOI substrate. The CMOS device of claim 1, wherein the p-type transistor is a p-MOS field effect transistor or a p-MOS fin FET. A first step of forming an n-type transistor on a silicon substrate having an upper surface (100); Forming an interlayer insulating layer covering the n-type transistor on the silicon substrate; A third step of forming a p-type transistor on the interlayer insulating layer, And the n-type transistor forms a channel in a <100> direction, and the p-type transistor forms a channel in a <110> direction. The method of claim 4, wherein the n-type transistor is an n-MOS field effect transistor. 5. The method of claim 4, wherein the p-type transistor is a p-MOS field effect transistor or a p-MOS fin. 7. The method of claim 6, wherein when the p-type transistor is the p-MOS pint, the third step is Forming a crystalline silicon layer on the interlayer insulating layer; Patterning the crystalline silicon layer to form a fin-like crystalline silicon layer pattern on the interlayer insulating layer; A third C step of sequentially forming a gate oxide film and a gate electrode on a region to be used as a channel of the crystalline silicon layer pattern; And And a 3D step of injecting a p-type conductive impurity into a region other than the region to be used as the channel in the crystalline silicon pattern. The method of claim 7, wherein the step 3A, Forming a contact hole in the interlayer insulating layer to expose the substrate; Filling the contact hole with a silicone plug; Forming an amorphous silicon layer covering the silicon plug on the interlayer insulating layer; Converting the amorphous silicon layer into a first crystalline silicon layer; Forming a second crystalline silicon layer on the first crystalline silicon layer; And And forming an insulating film on the second crystalline silicon layer. The method of claim 8, wherein the step 3B is Forming a photoresist pattern on the insulating layer, the photoresist pattern defining a fin crystalline silicon layer pattern; The insulating film, the second crystalline silicon layer, and the first crystalline silicon layer are sequentially formed using the photoresist pattern as an etching mask. Etching; And And removing the photosensitive film pattern. The method of claim 8, wherein the second crystalline silicon layer is formed by growing the first crystalline silicon layer by a homo epitaxy method. The method of claim 8, wherein the silicon plug is formed by growing a portion exposed through the contact hole of the substrate by a selective epitaxy method. The method of claim 8, wherein the amorphous silicon layer is converted into the first crystalline silicon layer by irradiating an excimer laser light. The method of manufacturing a CMOS device according to claim 7, wherein the p-type conductive impurity is implanted with tetragonal ion implantation. The method of claim 7, wherein the step 3A, Forming a contact hole in the interlayer insulating layer to expose the substrate; Forming the crystalline silicon layer filling the contact hole on the interlayer insulating layer; And Planarizing the crystalline silicon layer to a predetermined thickness. The method of claim 7, wherein the step 3A, Forming a contact hole in the interlayer insulating layer to expose the substrate; Filling the contact hole with a silicone plug; Forming an amorphous silicon layer covering the silicon plug on the interlayer insulating layer at the same height as the pinned crystalline silicon layer pattern; And And irradiating an excimer laser light to the amorphous silicon layer. The method of claim 15, wherein the silicon plug is formed by growing a portion exposed through the contact hole of the substrate by a selective epitaxy method. 5. The method of claim 4 wherein the substrate is part of an SOI substrate.

Images