KR20070005791A - Nonvolatile semiconductor memory device - Google Patents

Abstract

A non-volatile semiconductor memory device is provided to guarantee a process margin capable of forming a via for connecting a common source line and an interconnection by extending both ends of the common source line in a direction of the interconnection. A common source line(40) is formed on a substrate(10). A plurality of bitlines(30) are formed at both sides of the common source line. A pair of interconnections(50) cross each other at both ends of the common source line. A pair of vias(52) are formed at both ends of the common source line, connecting the common source line to the interconnection. Both the ends of the common source line are extended in the direction of the interconnection. The plurality of bitlines cross one of the pair of interconnections.

Description

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE}

1 is a plan view illustrating a nonvolatile semiconductor memory device according to an embodiment of the present invention.

♧ explanation of the reference numerals for the main parts of the drawing.

10 substrate 12a cell active region

12b: source active area 12c: surrounding active area

20: word line 25: source line

30: bit line 32: bit line contact

40: common source line 42: common source line contact

50: wiring line 52: via

60: gate line 70: signal line

72: signal line contact 80a: first wye pass transistor

80b: second Y-pass transistor

The present invention relates to a semiconductor device, and more particularly to a nonvolatile semiconductor memory device.

The nonvolatile semiconductor memory device may permanently preserve the contents stored in the memory cell even when the external power supply is interrupted. Among such nonvolatile semiconductor memory devices, a flash memory device capable of electrically erasing or writing (programming) information may be largely classified into a NAND flash memory device and a NOR flash memory device. Noah-type flash memory devices can control memory cells independently, resulting in high operating speed, but require one bit line contact per two cells, resulting in a larger cell area than NAND flash memory devices.

In order to solve the above disadvantages, while reducing the interval between the bit line and the word line, a problem that is not a problem in the prior art acts as a big obstacle to the operation of the cell. In the Noah type flash memory device, when the wiring line is connected to only one end of the common source line, the resistance increases as the distance from the wiring line increases. As a result, cells far away from the wiring line applying the source voltage rise in source voltage to form a back gate bias voltage and thus cannot read an accurate threshold voltage. This is also affected by the backgate bias effect during the write operation. Therefore, in the NOA type flash memory device, connecting the wiring line for applying the source voltage to both ends of the common source line is a very important factor in the operation of the cell. In this case, however, it is difficult to secure process margins.

The present invention has been proposed in consideration of the above-mentioned situation, and the technical problem to be achieved by the present invention is to secure a process margin for forming vias.

In order to achieve the above technical problem, the present invention provides a nonvolatile semiconductor memory device having both ends of a common source line extending in a wiring line direction. A nonvolatile semiconductor memory device according to an embodiment of the present invention includes a common source line formed on a substrate, a plurality of bit lines formed on both sides of the common source line, a pair of wiring lines crossing both ends of the common source line, and A pair of vias formed at both ends of the common source line to connect the common source line and the wiring line, and both ends of the common source line extend in the wiring line direction.

According to the present invention, even if the gap between the common source line and the bit line is shortened, since both ends of the common source line are extended, a space for forming a via, that is, a process margin is secured.

Each end of the common source line may extend in only one direction, and the extended direction of both ends of the common source line may be opposite to each other.

The plurality of bit lines may cross one wiring line of the pair of wiring lines. The nonvolatile semiconductor memory device according to the present invention may further include a cell array region between the pair of wiring lines, and a peripheral circuit region adjacent to the cell array region bordering the wiring line. In this case, the cell array region may be divided into a first region and a second region by the common source line, and a plurality of bit lines positioned in the first and second regions intersect a wiring line and the peripheral circuit region. May be connected to each other, and the wiring line where the bit lines positioned in the first region intersect and the wiring line where the bit lines positioned in the second region intersect may be different from each other. In this case, the Y-pass transistors that transmit the signal of the column decoder to the bit lines are located in opposite directions. That is, the wire pass transistor for transmitting a signal to the bit line of the first region and the wire pass transistor for transmitting a signal to the bit line of the second region are located in opposite directions with a pair of wiring lines therebetween.

Both ends of the common source line may extend in a direction opposite to a portion where the wiring line and the bit line cross each other.

A nonvolatile semiconductor memory device according to the present invention includes a common source line formed on a substrate, a plurality of bit lines formed on both sides of the common source line, a pair of wiring lines intersecting at both ends of the common source line, and a pair of The cell array region between wiring lines and a peripheral circuit region adjacent to the cell array region may be included at the boundary of the wiring line. In this case, the cell array region is divided into a first region and a second region by the common source line, and a plurality of bit lines positioned in the first and second regions are connected to the peripheral circuit region by crossing a wiring line. However, the wiring line where the bit lines positioned in the first region cross and the wiring line where the bit lines positioned in the second region cross may be different from each other.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey.

Although the terms first, second, etc. are used to describe various layers (or films) and regions in the embodiments of the present specification, the layers (or films) and regions should not be limited by these terms. do. These terms are only used to distinguish one given layer (or film) and region from another layer (or film) and region.

In the drawings, the thicknesses of layers (or layers) and regions may be exaggerated for clarity. Also, where it is mentioned that a layer (or film) is on or above another layer (or film) or substrate, it can be formed directly on another layer (or film) or substrate or between a third A layer (or film) may be interposed.

The same reference numerals throughout the specification represent the same components.

1 is a plan view illustrating a nonvolatile semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a region on the semiconductor substrate 10 is divided into a cell array region A and a peripheral circuit region B. FIG. At least one source active region 12b positioned between the cell active region 12a and the cell active region 12a is defined by an isolation layer (not shown) on the cell array region A. In addition, the peripheral active region 12c is defined on the peripheral circuit region B. FIG. A tunnel oxide film (not shown) is positioned on the cell active region 12a and the source active region 12b, and a gate oxide film (not shown) is positioned on the peripheral active region 12c. A plurality of word lines 20 intersect the cell active region 12a and the source active region 12b. The floating gate 22 is positioned between the cell and source active regions 12a and 12b and the word line 20. A control gate (not shown) is located on the floating gate 22. The control gate constitutes a word line 20. Generally, the floating gate 22 and the control gate are formed of a conductive film such as doped polysilicon. A gate interlayer dielectric film (not shown) is positioned between the floating gate 22 and the control gate. In general, the gate interlayer dielectric layer is formed of an ONO (oxide / nitride / oxide) layer. The floating gate 22 performs a memory cell function. In the write operation, electrons are accumulated in the floating gate 22 by hot electron injection. In the erase operation, the Fowler-Nordheim tunneling phenomenon from the bulk region formed on the substrate to the control gate is prevented. As a result, electrons accumulated in the floating gate 22 are emitted to the source region. In the read operation, it is possible to determine whether current flows from the drain region to the source region to determine whether electrons are accumulated in the floating gate 22, that is, whether data is stored.

A self aligned saucer line 25 is positioned between the word lines 20. That is, two word lines 20 share one source line 25.

The bit line 30 and the common source line 40 intersect the word line 20. The bit line 30 is located on the cell active region 12a and the common source line 40 is located on the source active region 12b. Bit line 30 is electrically connected to cell active region 12a and peripheral active region 12c by bit line contact 32, and common source line 40 is sourced by common source line contact 42. It is electrically connected to the active region 12b.

In one embodiment of the present invention, the bit line contact 32 and the common source line contact 42 are aligned in the direction of the word line 20, but need not be aligned. That is, the cell array region between the two wiring lines 50 may be in any form. A pair of wiring lines 50 for applying a source voltage across the common source line 40 cross each other. The wiring line 50 is electrically connected to the common source line 40 by the vias 52.

The bit line 30 positioned at one side of the common source line 40 and the bit line 30 positioned at the other side intersect the different wiring lines 50. Accordingly, the Y-pass transistors 80a and 80b that transmit signals from the column decoder (not shown) to the bit lines 30 are located in opposite directions with a pair of wiring lines 50 interposed therebetween. . In the pass transistors 80a and 80b, two bit lines 30 share one signal line 70. The peripheral active region 12c is divided into three regions by a pair of gate lines 60. The middle region is electrically connected to the signal line 70 by a signal line contact 72. Two other regions except for the center region are electrically connected to the bit line 30 by the bit line contact 32. The region connected to the signal line 70 becomes a drain region, and the region connected to the bit line 30 becomes a source region. However, the present invention should not be limited to the form of such a pass transistor, and may be in any form.

In the related art, the wire pass transistors 80a and 80b for transmitting a signal from the column decoder (not shown) to the bit line 30 are located in the same wiring line 50 direction. That is, since the bit lines 30 on both sides of the common source line 40 cross the same wiring line 50, the both ends of the common source line 40 could not extend in the wiring line 50 direction. Further, as the gap between the common source line 40 and the bit line 30 is shortened by high integration of the semiconductor device, it is difficult to form the vias 52.

However, in the exemplary embodiment of the present invention, since the pass transistors 80a and 80b are divided by the wiring line, both ends of the common source line 40 may be connected to the wiring line 50 and the bit line 30, respectively. It may extend in the opposite direction of the intersection. The process margin for forming the via 50 can be ensured.

In an embodiment of the present invention, both ends of the common source line extend in the wiring line direction, but the form thereof is not limited thereto. It may extend in the direction perpendicular to the wiring direction or the diagonal direction as well as the wiring direction, and may be in any form.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, of course, various modifications are possible without departing from the scope of the invention.

Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined not only by the claims below but also by the equivalents of the claims of the present invention.

According to the present invention described above, both ends of the common source line can be extended in the wiring line direction, so that a process margin for forming a via connecting the common source line and the wiring line can be secured. In addition, integration and reliability can be improved at the same time.

Claims (7)

A common source line formed on the substrate; A plurality of bit lines formed on both sides of the common source line; A pair of wiring lines intersecting at both ends of the common source line; And A pair of vias formed at both ends of the common source line and connecting the common source line and the wiring line, And both ends of the common source line extend in the wiring line direction. The method of claim 1, And each of both ends of the common source line extends in only one direction. The method of claim 2, And extending directions of both ends of the common source line are opposite to each other. The method of claim 1, And the plurality of bit lines cross one wiring line of the pair of wiring lines. The method of claim 4, wherein A cell array region between the pair of wiring lines; And Further comprising a peripheral circuit region adjacent to the cell array region bordering the wiring line, The cell array region is divided into a first region and a second region by the common source line, The plurality of bit lines positioned in the first and second regions may be connected to the peripheral circuit region by crossing the wiring lines. And a wiring line intersecting a bit line positioned in the first region and a wiring line intersecting a bit line positioned in the second region. The method of claim 5, And both ends of the common source line extend in a direction opposite to a portion where the wiring line and the bit line cross each other. A common source line formed on the substrate; A plurality of bit lines formed on both sides of the common source line; A pair of wiring lines intersecting at both ends of the common source line; A cell array region between the pair of wiring lines; And A peripheral circuit region adjacent to the cell array region bordering the wiring line; The cell array region is divided into a first region and a second region by the common source line, The plurality of bit lines positioned in the first and second regions may be connected to the peripheral circuit region by crossing the wiring lines. And a wiring line intersecting a bit line positioned in the first region and a wiring line intersecting a bit line positioned in the second region.

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