KR20070003036A - Method of implanting partially manufacturing three dimension transistor - Google Patents

Abstract

A nonuniform ion implantation method in a three-dimensional transistor fabrication is provided to enhance distribution characteristics of a predetermined device by controlling a scanning speed in X and Y axes. A wafer includes a predetermined lower structure for forming a three dimensional transistor. The wafer includes a first region and a second region. An ion implantation process is performed on the resultant structure(120). At this time, scanning speeds in X and Y axes are different from each other according to the first and second regions. The predetermined lower structure includes a trench or a step type profile. The trench is formed by recessing partially a substrate.

Description

Non-uniform ion implantation method for manufacturing three-dimensional transistors {Method of implanting partially manufacturing three dimension transistor}

FIG. 1 is a graph illustrating threshold voltage distribution characteristics of a cell according to an overlay split in a typical 3D transistor.

Figure 2 is a flow chart shown to explain a non-uniform ion implantation method for manufacturing a three-dimensional transistor according to the present invention.

3A and 3B are diagrams illustrating the steps of the flowchart of FIG. 2 in more detail.

4 is a graph showing the cell threshold voltage distribution characteristics of the device made by the non-uniform ion implantation method for manufacturing a three-dimensional transistor according to the present invention compared with the conventional case.

Explanation of symbols on the main parts of the drawing

200: wafer 220: first region

230: second area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to performing a non-uniform ion implantation process in a wafer having a transistor having a three-dimensional structure. A non-uniform ion implantation method for manufacturing a transistor.

Recently, as the DRAM cell CELL is highly integrated, the size of the transistor is decreasing. As the size of the transistor becomes smaller, in the case of a semiconductor device, especially a semiconductor device having a planner gate, the channel length between the source and the drain is shortened, thereby intensifying the short channel effect of the transistor. However, when the channel effect is intensified, the threshold voltage is reduced. Accordingly, in the case of a dynamic random access memory (DRAM) device, a write write time (tWR) is reduced and a refresh characteristic is reduced. It is well known that problems such as deterioration occur.

In order to solve the above problem, a recent research has been actively conducted to increase the effective channel length without reducing the density of devices instead of the planar gate. In this specification, a transistor having a structure in which the effective channel length is increased without reducing the integration degree of the device will be referred to as a three-dimensional transistor. An example of the three-dimensional transistor is a transistor having a recess gate structure. The recess gate structure is a structure in which a portion of the semiconductor substrate is recessed to form a trench for a recess gate, and a gate is formed so as to overlap the recess gate trench on the recess gate trench. Another example is a transistor having a step gate, in which a gate is formed to overlap the stepped profile after the substrate is formed to have a stepped profile.

In the case of such a three-dimensional transistor, various characteristics of the device may vary depending on how accurately the gate aligns with the trench or stepped profile. However, it can be easily expected that the alignment is not easy as compared with the conventional planar gate structure. The problem is that if the gates are not correctly aligned, the uniform device characteristics by ion implantation for the threshold voltage adjustment already performed will not be obtained, and the uniformity of the threshold voltage will be further increased by the subsequent unit processes. Will fall further.

FIG. 1 is a graph illustrating threshold voltage distribution characteristics of a cell according to an overlay split in a typical 3D transistor.

Referring to FIG. 1, it can be seen that the threshold voltage characteristics of the device exhibit a threshold voltage distribution characteristic in a wide range ranging from about 0.75V to about 1.9V. This is due to the overlay split, or incorrect alignment, of the three-dimensional transistor.

Therefore, there is a limit to overcome the deterioration of device characteristics due to the misalignment by conventional ion implantation for conventional threshold voltage, and it is urgently needed to develop an ion implantation method for threshold voltage control suitable for three-dimensional transistors. have.

The present invention is to solve the above problems, the technical problem to be achieved by the present invention is to perform a non-uniform ion implantation method for manufacturing a three-dimensional transistor for improving the scattering characteristics of the device by performing a non-uniform ion implantation process in the wafer To provide.

In order to achieve the above technical problem, a non-uniform ion implantation method for manufacturing a three-dimensional transistor according to an embodiment of the present invention, including a first region and a second region of the wafer having a substructure for forming a three-dimensional transistor In the non-uniform ion implantation method of implanting different concentrations of impurity ions into a plurality of regions, the ion beam scanned on the wafer is scanned in the X direction and the wafer is scanned in the Y direction, using X scan and Y scan, The scanning speed of at least one of the X scan and the Y scan is different in the first region and the second region so that impurity ions having different concentrations are implanted into the first region and the second region.

The substructure for forming the 3D transistor may include a structure in which a portion of the semiconductor substrate has a recessed trench or a stepped profile.

The lower structure for forming the 3D transistor may include a recess gate structure in which a gate electrode layer is disposed to overlap the trench.

The lower structure for forming the 3D transistor may include a step gate structure in which a gate electrode layer is disposed on the stepped profile semiconductor substrate.

The impurity ions may be performed by tilting and rotating the wafer to be implanted at different angles in the plurality of regions.

The tilt and rotation can be made to have a multi-mode than the bi-mode.

In the region where the ion implantation concentration is relatively high among the first region and the second region, the scanning speed of the X scan and the Y scan may be relatively reduced.

In the region where the ion implantation concentration is relatively low among the first region and the second region, the scanning speed of the X scan and the Y scan may be relatively increased.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

2, 3A and 3B are views illustrating a non-uniform ion implantation method for manufacturing a 3D transistor for manufacturing a semiconductor device according to the present invention. FIG. 2 is a flowchart illustrating a non-uniform ion implantation method for manufacturing a 3D transistor according to the present invention, and FIGS. 3A and 3B are views illustrating the steps of the flowchart of FIG. 2 in more detail. .

First, referring to FIGS. 2, 3A, and 3B, an ion implantation map for a 3D transistor is formed (step 100). The ion implantation map is divided into a plurality of regions according to the distribution of the threshold voltage injected into the wafer 200. For example, the region where the threshold voltage increases by the subsequent process may be set as the first region 220, and the region where the threshold voltage is lower than the first region 220 may be set as the second region 230. The first region 220 and the second region 230 may be divided based on a circular boundary line 210 formed at the center of the wafer 200. For example, the first region 220 may be positioned inside the boundary line 210 and the second region 230 may be positioned outside the boundary line, and the second region 230 may be positioned inside the boundary line and the first region outside the boundary line. Naturally, region 230 may be located.

Such an ion implantation map can be made by analyzing a threshold voltage change after performing all subsequent processes on a test wafer. In the present invention, although the ion implantation map is divided into the first region 220 and the second region 230, it is obvious that the ion implantation map may be divided into at least two or more regions. In addition, the circular boundary line 210 formed at the center of the wafer 200 may be biased toward the upper side of the wafer 200, or may be biased toward the lower side of the wafer 200.

Next, a substructure for forming a 3D transistor is formed on the semiconductor substrate (step 110). An example is a transistor having a recess gate structure. The recess gate structure is a structure in which a portion of the semiconductor substrate is recessed to form a trench for a recess gate, and a gate is formed so as to overlap the recess gate trench on the recess gate trench. Another example is a transistor having a step gate, in which a substrate is formed to have a stepped profile, and then a gate is formed so as to overlap the stepped profile.

Next, a non-uniform ion implantation process is performed on the semiconductor substrate on which the recess gate trench is formed by varying the speed of the ion beam (step 120). The heterogeneous ion implantation process allows impurity ions to be implanted into the first region 220 at a high dose amount and impurity ions to be implanted into the second region at a low dose based on the ion implantation map. To this end, X scan and Y scan are used, but the ion implantation process is performed while controlling the scanning speed of the X scan and the Y scan.

The X scan and the Y scan are scanned while moving in different directions. For example, when the wafer 200 moves in the X-axis direction and scans, the ion beam moves in the Y-axis direction and scans. In this case, the X and Y axes may or may not be perpendicular. In addition, the scanning speed of at least one of the X scan and the Y scan is different in the first region 220 and the second region 230 so that the impurity ions have different dose amounts in the first region 220 and the second region 230. Inject.

For example, when the threshold voltage formed in the first region 220 is relatively higher than the threshold voltage formed in the second region 230 after performing a subsequent process, the threshold voltage of the first region 220 is lowered. For this purpose, the ion beam is scanned from the a to d region while repeatedly moving the ion beam to the upper 241 and the lower 242 in the Y axis direction. In the regions b to c, the scanning speed is relatively slower than that in the regions a to b so that impurity ions are implanted at a large dose. Subsequently, in the areas c to d, the scanning speed is increased again so that impurity ions are implanted at a low dose. As described above, the non-uniform ion implantation process was performed by varying the scanning speeds of the ion beams 240 in the regions b through c, which are the first region 220, and regions a through b, which are the second region 230, and regions c through d, respectively. Therefore, the threshold voltages in the first region 220 and the second region 230 may be uniformly adjusted.

As an opposite example, when the threshold voltage formed in the first region 230 is relatively lower than the threshold voltage formed in the second region 220 after performing a subsequent process, the ion beam is imaged in the Y axis direction 241. , Scanning from a to d region while repeatedly moving to 242, but slowing down the scanning speed in a to b region so that impurity ions are implanted at a high dose amount, and scanning speed is increased from a to b region. The impurity ions are implanted at a lower dose by making them relatively faster than in the region b. Subsequently, in the areas c to d, the scanning speed is slowed again so that impurity ions are implanted at a high dose. As described above, the non-uniform ion implantation process was performed by varying the scanning speeds of the ion beams 240 in the regions b through c, which are the first region 230, and regions a through b, which are the second region 220, and regions c through d, respectively. Therefore, the threshold voltages in the first region 230 and the second region 220 may be uniformly adjusted.

The heterogeneous ion implantation process can be applied to a lightly doped drain (LDD) formation process, a source / drain impurity region formation process, and an asymmetric junction formation process. In this case, 11B, 49BF ₂ , 30BF, 31P, 75AS, 115In, and 122SB may be used as ions for adjusting the threshold voltage in the ion implantation process.

The X scans and the Y scans used to perform the heterogeneous ion implantation process are scanned while moving in different directions. For example, when the wafer 200 moves in the Y-axis direction and scans, the ion beam moves in the X-axis direction and scans. In this case, the X and Y axes may or may not be perpendicular.

During the X scan and the Y scan, the wafer 200 may be tilted so that ions are implanted at an inclined angle, or rotated so as to have an angle between 0 ° and 180 °. When the ion implantation process is performed by tilting the wafer 200, a bi-mode may be used, or a multi-mode may be repeatedly performed three or more times.

4 is a graph showing the cell threshold voltage distribution characteristics of the device made by the non-uniform ion implantation method for manufacturing a three-dimensional transistor according to the present invention compared with the conventional case. The horizontal axis represents threshold voltages of cell transistors, and the vertical axis represents distribution of threshold voltages.

Referring to FIG. 4, the graph 410 is a graph before performing non-uniform ion implantation, and it can be seen that the threshold voltage characteristics of the device exhibit threshold voltage distribution characteristics in a wide range from about 0.75V to about 0.83V. have. On the other hand, graph 420 is a graph after performing non-uniform ion implantation, and it can be seen that the dispersion characteristics of threshold voltages improved from about 0.79V to about 0.83V when the threshold voltage characteristics of the device were examined.

As described so far, when the non-uniform ion implantation method for manufacturing a three-dimensional transistor according to the present invention is applied, the scanning speed of the X scan and the Y scan is uneven while controlling the wafer having a nonuniform threshold voltage distribution. Since the ion implantation process is performed, the scattering characteristics of the device can be improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of protection of rights.

Claims (8)

In the non-uniform ion implantation method of implanting impurity ions of different concentrations into a plurality of regions including a first region and a second region of the wafer having a substructure for forming a three-dimensional transistor, The ion beam scanned on the wafer is scanned in the X direction and the wafer is scanned in the Y direction using X scan and Y scan, wherein the scan speed of at least one of the X scan and the Y scan is set to the first region and the second scan. Non-uniform ion implantation method for manufacturing a three-dimensional transistor, characterized in that to implant different concentrations of impurity ions in the first region and the second region in different regions. The method of claim 1, The substructure for forming the 3D transistor comprises a structure in which a portion of the semiconductor substrate has a recessed trench or a stepped profile. The method of claim 2, The lower structure for forming the 3D transistor has a recess gate structure in which a gate electrode layer is disposed to overlap the trench, wherein the method for implanting a 3D transistor is non-uniform. The method of claim 2, The lower structure for forming the 3D transistor has a step gate structure in which a gate electrode film is disposed on the stepped profile semiconductor substrate. The method of claim 1, The impurity ion is a non-uniform ion implantation method for manufacturing a three-dimensional transistor, characterized in that for performing the tilt and rotation of the wafer so as to be implanted at different angles in the plurality of regions The method of claim 2, The tilt and rotation is a non-uniform ion implantation method for manufacturing a three-dimensional transistor, characterized in that to have a multi-mode of bi-mode or more. The method of claim 1, Non-uniform ion implantation method for manufacturing a three-dimensional transistor, characterized in that for reducing the scanning speed of the X scan and Y scan in the region of relatively high ion implantation concentration of the first region and the second region. The method of claim 1, Non-uniform ion implantation method for manufacturing a three-dimensional transistor, characterized in that for increasing the scanning speed of the X scan and Y scan in the region of relatively low ion implantation concentration of the first region and the second region.

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