KR20070003011A - Method for fabricating cmos image sensor - Google Patents

Abstract

A method for manufacturing a CMOS image sensor is provided to improve photo characteristics by using a D2 annealing process for removing dangling bonds. A gate pattern of a transfer transistor is formed on a substrate(40). The gate pattern is composed of a silicon oxide layer and a silicon electrode layer. A photodiode(43) is formed at one side of the gate pattern. A floating node is formed at the other side of the gate pattern. A D2 annealing process is performed on the resultant structure to remove dangling bonds existing at an interface between a gate oxide layer and the substrate.

Description

Manufacturing method of CMOS image sensor {METHOD FOR FABRICATING CMOS IMAGE SENSOR}

1 is a circuit diagram showing one unit pixel in a CMOS image sensor.

FIG. 2 is a process cross-sectional view of four MOS transistors forming a unit cycle shown in FIG.

3 is a process plan view of four MOS transistors shown in FIG.

Figure 4 is a schematic cross-sectional view of an image sensor according to the prior art.

Figure 5 is a cross-sectional view showing a manufacturing method of an image sensor according to the prior art.

Figure 6 is a process cross-sectional view showing a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

40 substrate 41 device isolation film

42: source region 43: photodiode

44: gate pattern

The present invention relates to a CMOS image sensor and a manufacturing method thereof, and more particularly, to an optical characteristic improvement of the CMOS image sensor.

In general, an image sensor of a semiconductor device is a semiconductor device that converts an optical image into an electrical signal. Representative image sensor devices include a charge coupled device (CCD) and a CMOS image sensor.

Among them, the charge-coupled device is a device in which charge carriers are stored and transported in the capacitor while individual metal-oxide-silicon (MOS) capacitors are located very close to each other. By using CMOS technology that uses a signal processing circuit as a peripheral circuit, a MOS transistor (typically four MOS transistors) corresponding to the number of pixels is made and sequentially output using the MOS transistor.

1 is a circuit diagram showing one unit pixel in a CMOS image sensor.

Referring to FIG. 1, one unit pixel includes one photodiode 10 and four an MOS transistors 11, 12, 13, and 14. As shown in FIG. Four NMOS transistors 11, 12, 13, and 14 are a transfer MOS transistor 11 for transporting the photocharge generated in the photodiode 10 to the charge sensing node N, and a charge for the next signal detection. The reset MOS transistor 12 for discharging the charge stored in the sensing node 11, the drive MOS transistor 13 serving as a source follower 13, and the switching role may be addressed. It is composed of a select MOS transistor 14 to enable.

Four MOS transistors 11, 12, 13, and 14 and one photodiode 10 form one unit pixel, and are provided in the pixel array of the CMOS image sensor according to the number of unit pixels included in the CMOS image sensor. The number of photodiodes 10 and the number of MOS transistors for unit pixels corresponding thereto are determined.

FIG. 2 is a process cross-sectional view of four MOS transistors constituting a unit circuit shown in FIG. 1, and four MOS transistors 11, 12, 13, and 14 respectively transmit signals Tx, Rx, Dx, and Sx to gates. The light transmitted to the photodiode PD is transmitted to the output terminal.

3 is a process plan view of four MOS transistors shown in FIG.

As shown in FIG. 3, gate patterns Tx of four MOS transistors 11, 12, 13, and 14 for transferring electrons collected by light transmitted from the photodiode 10 to an output terminal. , Rx, Dx, and Sx are disposed, and active regions 101 to 104 are disposed to the left and right of the gate patterns Tx, Rx, Dx, and Sx, respectively.

In this case, the active region 101 is a sensing node that receives electrons collected by the photodiode.

Referring to the operation of one unit device briefly, electrons collected by light transmitted to the photodiode 10 are transferred to the sensing node 101 through the transfer transistor 11.

Since the sensing node 101 is connected to the gate of the driving transistor 13, the driving transistor 13 adjusts the voltage level of the active region 103 bonded to one end in accordance with the voltage applied to the sensing node 101. Driving. Subsequently, the select transistor 104 is turned on to output a voltage applied to the active region 103 through an output terminal.

4 is a cross-sectional view schematically showing an image sensor according to the prior art.

Referring to FIG. 4, a color filter array (CFA) such as blue, red, and green, which form unit pixels on the substrate 20 on which the photodiodes 10 and PD are formed, is formed. A color filter array 24 is disposed, and a flattening film called an overcoating layer (OCL) 25 is formed thereon, and an upper portion of the region overlapping with the color filter array 14; Convex microlenses 16 are formed.

Multi-layered wirings 23 are formed between the multi-layered insulating films 22, and the wirings 23 are disposed in regions not overlapping with the photodiode 10. The wirings formed of metal serve as a light blocking film. do.

In addition, a plurality of MOS transistors (region A) are formed on the substrate 20 adjacent to the photodiode 10, which is a transfer transistor, a select transistor, a reset transistor, and a drive as described above in the case of a 4Tr unit pixel. The transistor is placed.

A protective film 27 is formed on the microlens 26 to protect the microlens 26 from scratches and the like. Reference numeral 29 denotes a device isolation film.

Also, although not shown here, a macro lens is disposed on the upper portion of the micro lens to directly receive light incident from the outside and transmit the light to the micro lens.

As described above, the voltage applied to the gate of the driving transistor is controlled by electrons transferred from the photodiode to the floating node SD, and the source terminal of the driving transistor is driven in response to the regulated voltage.

5 is a cross-sectional view showing a manufacturing method of an image sensor according to the prior art.

Referring to FIG. 5, in the method of manufacturing a CMOS image sensor according to the related art, first, an isolation layer 31 is formed on a substrate 30, a photodiode 33 and a floating node 32 are formed, and a gate is formed. The pattern 34 is formed. Here, the gate pattern 34 is a gate pattern of the transfer transistor.

In the process of manufacturing CMOS image sensor, light entering the photodiode generates electron hole pair in the photodiode. In order to send the generated electron hole pair to the floating node 32 without loss, there should be no trapped region at the interface of the silicon kidney.

When the charge of the light source is stored in the photodiode, when the transfer transistor is turned on, the charge is moved to the floating node 32 through the channel. At this time, the bottom of the gate pattern 34 of the transfer transistor inevitably forms an oxide film. It contains dangling bonds.

Silicon dangling bonds trap a charge when the charge moves, causing a lot of charge loss, so the light sensitivity is improved when it is removed.

Currently, annealing is carried out using H2 gas to convert silicon dangling bonds into Si-H bonds to reduce losses.

However, not all dangling bonds can be made of Si-H, and since Si-H bonds have very weak bonding forces, many coupling losses occur during the operation of the device, causing optical degradation and optical degradation over time. Become the main cause.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a method for manufacturing a CMOS image sensor that can reduce the dangling bond at the bottom of the gate pattern of the transfer transistor at the time of manufacturing the CMOS image sensor.

The present invention includes forming a gate pattern of a transfer transistor stacked on a substrate as a silicon oxide film / silicon electrode film; Forming a photodiode on one side of the gate pattern; forming a floating node on the other side of the gate pattern; And performing a D2 annealing process to remove dangling bonds formed at the interface between the gate oxide film and the substrate.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

6 is a process sectional view showing a method of manufacturing a CMOS image sensor according to a preferred embodiment of the present invention.

Referring to FIG. 6, the method for manufacturing the CMOS image sensor according to the present embodiment first forms an isolation layer 41 having a shape embedded in a substrate.

Subsequently, the gate pattern 44 of the transfer transistor is formed.

Subsequently, the photodiode 43 and the floating node 42 are formed.

Subsequently, annealing is performed using D2 gas at a high pressure of 5 to 30 atm for 0.5 to 2 hours in a 400 to 600 degree range.

At this time, D2 penetrates the polycrystalline silicon and combines with the silicon dangling bond at the interface between the oxide film formed at the bottom of the gate pattern and the substrate to form a SiD bond.

Of course, surface passivation by D2 also occurs in the areas where the active is exposed.

D2 (Deuterium) is an isotope of hydrogen, which has one more neutron in hydrogen. It refers to a molecule having a mass of 2 compared to 1, which easily bonds with silicon dangling bonds in the form of SD or Si-OD. .

The combined Si-D and Si-OD bonds replace Si-H or Si-OH bonds that form the most trap charges at the interface between the silicon substrate and the silicon oxide film (Si / SiO ₂ ). Since the bonding strength of the replaced Si-D or Si-OD is much larger than that of conventional Si-H, reliability can be improved.

However, when annealing D2, diffusion in silicon may be a problem since it may not reach the interface region between the silicon substrate and the silicon oxide film because it is later than the conventional H2.

When annealing is applied at high pressure to solve this problem, D2 can reach the interface region between the silicon substrate and the silicon oxide film even at a low temperature.

Subsequently, after the annealing process using D2 gas, the N2 annealing process is performed in the range of 400 to 450 degrees instead of the formaling gas annealing.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

For example, the above-described D2 annealing process may be performed after the metal wiring is formed.

As in the present invention, the CMOS image sensor operates by substituting Si-H or Si-OH bonds in the interface region between the silicon substrate and the silicon oxide film with Si-F, Si-D, Si-OD, etc., which have a much stronger bonding force. This eliminates the case where Si-H or Si-OH is broken and trap charges are eliminated, so that photoelectrons generated in the photodiode are hardly generated. Thus, optical properties can be greatly improved.

Claims (4)

Forming a gate pattern of a transfer transistor stacked on a substrate with a silicon oxide film / silicon electrode film; Forming a photodiode on one side of the gate pattern Forming a floating node on the other side of the gate pattern; And Performing a D2 annealing process to remove dangling bonds formed at the interface between the gate oxide film and the substrate; Method for manufacturing a CMOS image sensor comprising a. The method of claim 1, The D2 annealing process is a method of manufacturing a CMOS image sensor, characterized in that the process proceeds at a pressure of 5 ~ 30 range. The method of claim 2, The D2 annealing process Method of manufacturing a CMOS image sensor, characterized in that the process in the range of 400 ~ 600 degrees. The method of claim 3, wherein The D2 annealing process Method of manufacturing a CMOS image sensor, characterized in that the process is carried out in about 0.5 to 2 hours.

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