KR20060136058A - Overlay mark and wafer align mark of dot type - Google Patents

Abstract

Disclosed are an overlay mark used for measuring the degree of overlap in a manufacturing process of a semiconductor device and a wafer alignment mark used for wafer alignment. The overlay mark includes a mother formed in a plurality of trenches in the form of a trench in order to prevent a reverse RIE-RAG phenomenon in which an etch defect is caused for a wide pattern among the patterns of the overlay mark. do. In the wafer alignment mark, a plurality of unit wafer alignment marks in the form of a square dot are formed in order to prevent a reverse RIE-RAG phenomenon in which an etching failure is caused for a wide pattern among the patterns of the wafer alignment mark. Thus, the present invention can improve the problem of accumulated impurities or lump-like impurities due to poor etching in forming conventional overlay marks and wafer alignment marks by providing improved overlay marks and wafer alignment marks. .

Etch, Overlay, Align, Dot

Description

Overlay mark and wafer align mark of dot type

1 is a plan view of an overlay mark;

2 is a plan view of a wafer alignment mark.

3 is an enlarged perspective view of an overlay mark in which a reverse RIE-RAG phenomenon occurs.

4 is a schematic view showing an overlay mark according to an embodiment of the present invention.

5 is a schematic view showing a wafer alignment mark in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: overlay mark 102: son

101: unit mother 200: wafer alignment mark

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to overlay marks and wafer align marks in wafers for the manufacture of semiconductor devices.

Recently, as the degree of integration in a semiconductor device manufacturing process increases, new materials and structures are adopted and used. Accordingly, maintaining the accuracy of the degree of overlap between layers in the exposure process has emerged as one of the very important technologies. In order to more accurately overlap the layers during the manufacturing process of the semiconductor device, an alignment mark is formed by patterning the lower layer in a patterning process, and a sensor in the exposure equipment recognizes the position of the alignment mark in the exposure process of the next layer. To make it sortable.

In addition, an overlay mark for measuring the degree of overlap between the two layers is formed to maintain the degree of overlap accurately.

1 is a plan view of an overlay mark, and FIG. 2 is a plan view of a wafer alignment mark.

First, referring to FIG. 1, the overlay mark includes a son 12 and a mother 10. In general, the son 12 is mesa (mesa) form, the mother 10 is formed in a trench (trench) form.

Next, referring to FIG. 2, a plurality of wafer alignment marks 20 are shown. Each of the wafer alignment marks 20 has three bar unit alignment marks 22. The wafer alignment mark 20 is used when, for example, aligning a metal contact or via layer mark, which is a previous process, when the metal layer proceeds. The width of the unit alignment mark 22 is generally 2 micrometers or more, and is formed in a bar type.

In the conventional dry etching process, a wide pattern (for example, a photo key) is etched but a narrow pattern is not easily etched. Such a problem is called a rapid ion etching (RIE) -RAG. . The RIE-RAG problem has been solved by improving an etching condition or an etching selectivity.

However, in recent years, as the design rule is reduced (for example, the design rule in SRAM), the etching conditions and the etching selectivity are improved to prevent etching in a wide pattern such as a photo key. The phenomenon appears. This phenomenon is called reverse RIE-RAG.

3 is an enlarged perspective view of the overlay mark of FIG. 1 in which a reverse RIE-RAG phenomenon occurs.

Referring to FIG. 3, it can be seen that in the mother layer 10 formed in the trench form, impurities are not etched properly and impurities in the form of debris or lumps are accumulated in the mother line 10 of the overlay mark pattern. Although not shown, etching may not be performed properly not only in the overlay mark but also in the pattern of the wafer alignment mark, resulting in accumulation of impurities or lump-like impurities.

When etching by changing the etching conditions in order to improve the reverse RIE-RAG problem, there is a problem that the etching is not properly due to the small mark pattern.

In addition, since the inverse RIE-RAG is generated in the pattern of the wafer alignment mark, there is a problem that an error of data such as a photo critical dimension (CD) and a scattering value occurs.

Therefore, in the process for manufacturing a semiconductor device with a small design rule, it is urgently required to solve the reverse RIE-RAG phenomenon in which etching is not performed properly in a wide pattern.

Accordingly, an object of the present invention is to provide an overlay mark for solving the problem that the etching is not properly formed in the conventional overlay mark.

Another object of the present invention is to provide a wafer alignment mark for improving a problem in which impurities in the form of debris or lumps are accumulated due to poor etching in the pattern of the wafer alignment mark.

It is still another object of the present invention to provide an overlay mark and a wafer alignment mark for solving the reverse RIE-RAG phenomenon, which is a phenomenon in which etching is not properly performed on a wide pattern in a process for manufacturing a semiconductor device with a low design rule. .

It is still another object of the present invention to provide a wafer alignment mark that can improve a problem in which an error of data such as a photo critical dimension and a scatter value occurs due to the inverse RIE-RAG in the pattern of the wafer alignment mark. have.

In order to achieve the above objects, the overlay mark used for measuring the overlap in the manufacturing process of the semiconductor device according to an aspect of the present invention is formed in the form of mesa; And in order to prevent the reverse RIE-RAG phenomenon that the etching failure is caused for a wide pattern of the overlay mark pattern is characterized in that it comprises a plurality of the mother formed in a trench form of a square dot mother unit.

Here, the unit mother is preferably a square with one side of 0.2 to 0.5 micrometers.

In order to achieve the above objects, a wafer alignment mark used for wafer alignment in a semiconductor device manufacturing process according to an aspect of the present invention is an inverse RIE in which an etching failure is caused for a wide pattern among the patterns of the wafer alignment mark. In order to prevent the RAG phenomenon, a plurality of unit wafer alignment marks having a rectangular dot shape are formed.

Here, the wafer alignment mark may be used to align the metal contact or via layer mark, which is the previous process, during the metal layer process.

In addition, the wafer alignment mark may be formed in a trench shape, and the unit wafer alignment mark may be a rectangle having a large side length of 0.3 to 1.0 micrometers.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The descriptions in the following embodiments are merely illustrated and limited by way of example and without intention other than the intention of helping those having ordinary knowledge in the art to which the present invention pertains more thoroughly. It should not be used to limit the scope.

4 is a schematic view showing an overlay mark according to an embodiment of the present invention.

Referring to FIG. 4, the overlay mark 100 used for measuring the overlapping degree in a manufacturing process of a semiconductor device includes an inductor 102 formed in a mesa shape and a mother form formed in a trench shape.

In order to prevent the reverse RIE-RAG phenomenon in which an etching failure is caused with respect to a wide pattern among the patterns of the overlay mark 100, the mother unit is provided with a unit mother unit 101 having a rectangular dot shape. That is, the plurality of unit mothers 101 is formed in a trench form and arranged in a matrix form to form the mothers.

The unit mother unit 101 may be a square having one side of 0.2 to 0.5 micrometers. Thus, in the case of a conventional overlay mark mother whose one side is generally 1 micrometer or 2 micrometers, the problem of inferior etching caused by the reverse RIE-RAG phenomenon and the accumulation of debris or lumps on the overlay mark pattern area can be solved. have. In other words, by forming the overlay mark pattern small, it is possible to prevent the reverse RIE-RAG phenomenon. The unit mother unit 101 is more preferably 0.3 micrometers on one side in order to prevent errors in photo critical dimensions, scattering, and the like.

5 is a schematic view showing a wafer alignment mark according to an embodiment of the present invention.

Referring to FIG. 5, the wafer alignment mark 200 used in the wafer alignment in the manufacturing process of the semiconductor device prevents an inverse RIE-RAG phenomenon in which an etching failure is caused for a wide pattern among the patterns of the wafer alignment mark. To this end, a plurality of unit wafer alignment marks in the form of square dots are formed. Reference numeral 202 denotes a plurality of unit wafer align marks.

Compared with the conventional wafer align mark of FIG. 2, the unit wafer align mark 22 in the conventional wafer align mark 20 is generally 2 micrometers although the types of marks vary slightly depending on the process equipment. In contrast to the bar shape described above, the unit wafer alignment mark in the wafer alignment mark 200 according to the exemplary embodiment of the present invention is small. The unit wafer alignment mark may be a rectangle having a large side length of 0.3 to 1.0 micrometers. In order to prevent reverse RIE-RAG, it is preferable that the unit wafer align mark has a length of 0.3 micrometers with a large side.

The wafer alignment mark may be used to align the metal contact or via layer mark, which is a previous process, during the metal layer process.

In addition, the wafer alignment mark may be formed in a trench shape. Thus, the etching defects are improved, and the reverse RIE-RAG problem can be solved.

The overlay mark and the wafer alignment mark according to the embodiment of the present invention are not limited to the above embodiments, and may be variously designed and applied without departing from the basic principles of the present invention. It will be obvious to those who have ordinary knowledge.

As described above, the present invention provides an improved overlay mark and wafer alignment mark, thereby solving the problem that impurities are accumulated in the form of debris or lump due to poor etching in the formation of the conventional overlay mark and wafer alignment mark. have.

In addition, by providing an improved overlay mark and wafer alignment mark, the present invention can reduce the inverse RIE-RAG phenomenon, which is a phenomenon in which etching is poor for a wide pattern in a process for manufacturing a semiconductor device with a small design rule. .

In addition, the present invention can improve the problem that an error of data such as a photo critical dimension and a scatter value occurs due to the inverse RIE-RAG generated in the pattern of the wafer alignment mark.

Claims (6)

In the overlay mark used for the measurement of overlap in the manufacturing process of a semiconductor device: Sonja formed in mesa form; And An overlay mark, characterized in that the plurality of square-shaped unit mother in the form of a trench provided with a trench in order to prevent the reverse RIE-RAG phenomenon that the etching failure for a wide pattern of the overlay mark pattern. In the wafer alignment mark used for wafer alignment in the manufacturing process of a semiconductor device: Wafer alignment mark, characterized in that a plurality of unit wafer alignment marks in the form of a square dot is formed in order to prevent the reverse RIE-RAG phenomenon that etching failure is caused for a wide pattern of the pattern of the wafer alignment mark. The method of claim 1, The unit marker is a overlay mark, characterized in that one side is a square of 0.2 to 0.5 micrometers. The method of claim 2, The wafer alignment mark is a wafer alignment mark, characterized in that used to align the metal contact or via layer mark of the previous process during the metal layer process. The method of claim 2, The wafer alignment mark is formed in a trench shape. The method of claim 2, And the unit wafer alignment mark is a rectangle having a large side length of 0.3 to 1.0 micrometers.

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