KR20060134330A - Forming method of fine pattern using double exposure process - Google Patents

Forming method of fine pattern using double exposure process Download PDF

Info

Publication number
KR20060134330A
KR20060134330A KR1020050053930A KR20050053930A KR20060134330A KR 20060134330 A KR20060134330 A KR 20060134330A KR 1020050053930 A KR1020050053930 A KR 1020050053930A KR 20050053930 A KR20050053930 A KR 20050053930A KR 20060134330 A KR20060134330 A KR 20060134330A
Authority
KR
South Korea
Prior art keywords
pattern
layer
sion
photoresist
amorphous carbon
Prior art date
Application number
KR1020050053930A
Other languages
Korean (ko)
Other versions
KR100720243B1 (en
Inventor
조윤석
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020050053930A priority Critical patent/KR100720243B1/en
Publication of KR20060134330A publication Critical patent/KR20060134330A/en
Application granted granted Critical
Publication of KR100720243B1 publication Critical patent/KR100720243B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

A method for forming a fine pattern by using double exposure process is provided to carry out a secondary patterning process on an SiON layer when the fine pattern is formed by the double exposure process. An amorphous carbon layer and an SiON layer are formed on a non-etching layer(110). A photoresist pattern is formed on the SiON. The SiON layer is etched to form a first SiON pattern. The first photoresist pattern is removed, and a second photoresist layer(130) is formed on the entire surface of the SiON pattern. The second photoresist layer is subjected to a lithographic process to form a second photoresist pattern. The SiON is etched by using the second photoresist pattern as a mask to form a second SiON. The second photoresist pattern is removed, and the amorphous carbon layer is etched to form an amorphous carbon layer pattern. The non-etching layer is etched by using the amorphous carbon layer pattern as a mask to form a non-etching layer pattern.

Description

이중 노광 공정을 이용한 미세 패턴 형성방법{Forming method of fine pattern using double exposure process}Forming method of fine pattern using double exposure process}

도 1a 내지 도 1g는 종래의 이중 노광 공정을 이용한 패턴 형성방법을 나타낸 공정 단면도이다.1A to 1G are cross-sectional views illustrating a method of forming a pattern using a conventional double exposure process.

도 2는 종래의 이중 노광 공정을 이용한 패턴 형성방법에서 나타날 수 있는 문제점을 도시한 단면도이다.2 is a cross-sectional view showing a problem that may appear in the pattern forming method using a conventional double exposure process.

도 3a 내지 도 3j는 본 발명의 이중 노광 공정을 이용한 패턴 형성방법을 나타낸 공정 단면도이다.3A to 3J are cross-sectional views illustrating a method of forming a pattern using the double exposure process of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10, 110: 피식각층 12: 제1 피식각층 패턴10, 110: etched layer 12: first etched layer pattern

14: 제2 피식각층 패턴 20, 120: 제1 포토레지스트 패턴14: second etching layer pattern 20, 120: first photoresist pattern

30, 130: 제2 포토레지스트층 32, 132: 제2 포토레지스트 패턴30 and 130: second photoresist layer 32 and 132: second photoresist pattern

116: 피식각층 패턴 150: 비정질 탄소 하드 마스크층116: etching layer pattern 150: amorphous carbon hard mask layer

152: 비정질 탄소 하드 마스크 패턴152: amorphous carbon hard mask pattern

160: SiON 하드 마스크층 162: 제1 SiON 하드 마스크 패턴160: SiON hard mask layer 162: first SiON hard mask pattern

164: 제2 SiON 하드 마스크 패턴164: second SiON hard mask pattern

본 발명은 이중 노광 공정을 이용한 미세 패턴 형성방법에 관한 것으로, 더욱 상세하게는 SiON층/비정질 탄소층을 식각 마스크로 이용하여, 식각 선택비가 높은 SiON의 특성상 SiON 층을 매우 얇게 형성하여 식각 공정을 진행함으로써, 1차 패터닝 과정에서 형성된 패턴의 두께가 매우 얇아서 2차 패터닝을 불량 없이 진행할 수 있는 방법에 관한 것이다.The present invention relates to a method for forming a fine pattern using a double exposure process, and more particularly, by using a SiON layer / amorphous carbon layer as an etching mask, the SiON layer is formed very thin due to the characteristic of SiON having a high etching selectivity. By proceeding, the thickness of the pattern formed in the first patterning process is very thin and relates to a method that can proceed secondary patterning without defects.

이하, 종래의 이중 노광 공정을 이용한 패턴 형성방법에 대하여 도 1a 내지 도 1g를 참조하여 설명하기로 한다.Hereinafter, a pattern forming method using a conventional double exposure process will be described with reference to FIGS. 1A to 1G.

도 1a 내지 도 1g의 과정은 예를 들어 50nm의 패턴을 형성하기 위하여 100nm 노광 마스크를 두 번 사용하는 이중 노광 공정을 도시하고 있다.The process of FIGS. 1A-1G illustrates a double exposure process using, for example, a 100 nm exposure mask twice to form a 50 nm pattern.

우선, 피식각층 (10) 상부에 포토레지스트 층을 도포한 다음 소정의 리소그라피 공정을 수행하여 제1 포토레지스트 패턴 (20)을 형성하고 (도 1a 참조), 형성된 제1 포토레지스트 패턴 (20)을 식각 마스크로 이용하여 제1 피식각층 패턴 (12)을 형성한다 (도 1b 참조).First, a photoresist layer is applied on the etched layer 10, and then, a predetermined lithography process is performed to form the first photoresist pattern 20 (see FIG. 1A), and the formed first photoresist pattern 20 is formed. The first etched layer pattern 12 is formed using the etching mask (see FIG. 1B).

다음, 제1 포토레지스트 패턴 (20)을 제거하고 (도 1c 참조), 제1 피식각층 패턴 (12) 전면에 제2 포토레지스트층 (30)을 도포한다 (도 1d 참조).Next, the first photoresist pattern 20 is removed (see FIG. 1C), and the second photoresist layer 30 is applied to the entire surface of the first etched layer pattern 12 (see FIG. 1D).

여기에 소정의 리소그라피 공정을 수행하여 제2 포토레지스트 패턴 (32)을 형성 (도 1e 참조)하고, 형성된 제2 포토레지스트 패턴 (32)을 식각 마스크로 이용하여 제1 피식각층 패턴 (12)을 식각하여 상기 제1 피식각층 패턴 (12)보다 작은 선폭을 갖는 제2 피식각층 패턴 (14)을 형성한 다음 (도 1f 참조), 제2 포토레지스트 패턴 (32)을 제거한다 (도 1g 참조).The second photoresist pattern 32 is formed (see FIG. 1E) by performing a predetermined lithography process, and the first etched layer pattern 12 is formed using the formed second photoresist pattern 32 as an etching mask. Etching forms a second etched pattern 14 having a line width smaller than the first etched layer pattern 12 (see FIG. 1F), and then removes the second photoresist pattern 32 (see FIG. 1G). .

이상의 도 1a 내지 도 1g의 과정은 이중 노광 공정이 이상적으로 진행된 경우를 나타낸 것이고, 실제로는 도 1d에 도시된 공정에서 제1 피식각층 패턴 (12) 전면에 도포되는 제2 포토레지스트 (30)의 두께가 제1 피식각층 패턴 (12)의 토폴로지 (topology)에 비하여 얇은 경우 포토레지스트 도포 공정에서 평탄화가 이루어지지 않아 (도 2 참조) 도 1e에 나타낸 공정에서 포토레지스트 마스크 패턴 불량이 발생하게 된다.1A to 1G show a case where the double exposure process is ideally performed, and in fact, the process of the second photoresist 30 applied on the entire surface of the first etched layer pattern 12 in the process shown in FIG. 1D. When the thickness is thinner than the topology of the first etched layer pattern 12, no planarization is performed in the photoresist coating process (see FIG. 2), so that a photoresist mask pattern defect occurs in the process shown in FIG. 1E.

이에, 본 발명의 목적은 상기와 같은 마스크 패턴 불량이 발생하지 않는 이중 노광 공정을 이용한 미세 패턴 형성방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a fine pattern forming method using a double exposure process in which the mask pattern defect as described above does not occur.

상기와 같은 목적을 달성하기 위하여 본 발명에서는 SiON층/비정질 탄소층을 하드 마스크로 이용하는 이중 노광에 의한 미세 패턴 형성방법을 제공한다.In order to achieve the above object, the present invention provides a method for forming a fine pattern by double exposure using a SiON layer / amorphous carbon layer as a hard mask.

이하 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail.

본 발명은 이중 노광 공정을 이용한 미세 패턴 형성방법에 있어서, SiON층/비정질 탄소층을 식각 마스크로 사용하는 것에 그 특징이 있다.The present invention is characterized in that the SiON layer / amorphous carbon layer is used as an etching mask in the method of forming a fine pattern using a double exposure process.

구체적으로, 본 발명의 방법은 하기와 같은 단계를 포함한다:Specifically, the method of the present invention comprises the following steps:

피식각층 상부에 비정질 탄소층과 SiON 층을 순차적으로 형성하는 단계;Sequentially forming an amorphous carbon layer and a SiON layer on the etched layer;

상기 SiON 층 상부에 제1 포토레지스트 패턴을 형성하는 단계;Forming a first photoresist pattern on the SiON layer;

상기 제1 포토레지스트 패턴을 식각 마스크로 하여 상기 SiON 층을 식각하여 제1 SiON 패턴을 형성하는 단계;Etching the SiON layer using the first photoresist pattern as an etching mask to form a first SiON pattern;

상기 제1 포토레지스트 패턴을 제거하는 단계;Removing the first photoresist pattern;

상기 SiON 패턴 전면에 제2 포토레지스트 층을 형성하는 단계;Forming a second photoresist layer on the entire surface of the SiON pattern;

제2 포토레지스트 층에 리소그라피 공정을 수행하여 제2 포토레지스트 패턴을 형성하는 단계;Performing a lithography process on the second photoresist layer to form a second photoresist pattern;

상기 제2 포토레지스트 패턴을 식각 마스크로 하여 제2 SiON 패턴을 형성하는 단계;Forming a second SiON pattern using the second photoresist pattern as an etching mask;

상기 제2 포토레지스트 패턴을 제거하는 단계;Removing the second photoresist pattern;

상기 제2 SiON 패턴을 식각 마스크로 하여 상기 비정질 탄소층을 식각하여 비정질 탄소층 패턴을 형성하는 단계; 및Etching the amorphous carbon layer by using the second SiON pattern as an etching mask to form an amorphous carbon layer pattern; And

상기 비정질 탄소층 패턴을 식각 마스크로 하여 피식각층 패턴을 형성하는 단계.Forming an etched layer pattern using the amorphous carbon layer pattern as an etch mask.

이때 상기 비정질 탄소층은 500~3000Å의 두께로 형성되는 것이 바람직하고, SiON 층은 50~400Å의 두께로 형성되는 것이 바람직하다.At this time, the amorphous carbon layer is preferably formed to a thickness of 500 ~ 3000 500, the SiON layer is preferably formed to a thickness of 50 ~ 400Å.

한편, 상기 제1 포토레지스트 패턴 제거 및 제2 포토레지스트 패턴 제거 공정은 비정질 탄소층에 대하여 선택적으로 수행되어, 비정질 탄소층은 그대로 유지되고 포토레지스트 패턴만 제거된다.Meanwhile, the first photoresist pattern removal process and the second photoresist pattern removal process may be selectively performed on the amorphous carbon layer, so that the amorphous carbon layer is maintained as it is and only the photoresist pattern is removed.

또한, 상기 제1 포토레지스트 패턴 제거 및 제2 포토레지스트 패턴 제거 공정은 습식 공정으로서, 포토레지스트 내의 중합체를 용해시킬 수 있는 화학물질을 포함하는 용액 이용하여 수행된다.In addition, the first photoresist pattern removal process and the second photoresist pattern removal process may be performed as a wet process using a solution containing a chemical capable of dissolving a polymer in the photoresist.

이하, 본 발명의 이중 노광 공정을 이용한 패턴 형성방법에 대하여 도 3a 내지 도 3j를 참조하여 설명하기로 한다.Hereinafter, a pattern forming method using the double exposure process of the present invention will be described with reference to FIGS. 3A to 3J.

우선, 피식각층 (110) 상부에 비정질 탄소 하드 마스크 층 (150), SiON 하드 마스크층 (160) 및 포토레지스트 층을 순차적으로 도포한 다음 소정의 리소그라피 공정을 수행하여 제1 포토레지스트 패턴 (120)을 형성하고 (도 3a 참조), 형성된 제1 포토레지스트 패턴 (120)을 식각 마스크로 이용하여 얇은 두께의 SiON 하드 마스크층 (160)을 식각하여 제1 SiON 하드 마스크 패턴 (162)을 형성한다 (도 3b 참조).First, an amorphous carbon hard mask layer 150, a SiON hard mask layer 160, and a photoresist layer are sequentially applied on the etched layer 110, and then a predetermined lithography process is performed to form the first photoresist pattern 120. (See FIG. 3A), the thin SiON hard mask layer 160 is etched using the formed first photoresist pattern 120 as an etching mask to form a first SiON hard mask pattern 162 ( 3b).

다음, 제1 포토레지스트 패턴 (120)을 제거하고 (도 3c 참조), 제1 SiON 하드 마스크 패턴 (162) 전면에 제2 포토레지스트층 (130)을 도포한다 (도 3d 참조).Next, the first photoresist pattern 120 is removed (see FIG. 3C), and the second photoresist layer 130 is coated on the entire surface of the first SiON hard mask pattern 162 (see FIG. 3D).

이때 1차 패터닝에서 형성된 제1 SiON 하드 마스크 패턴 (162)의 두께가 매우 얇으므로 제2 포토레지스트층 (130)을 전면 도포할 때 평탄하게 도포되므로 상기 도 2와 같은 문제가 발생하지 않는다.In this case, since the thickness of the first SiON hard mask pattern 162 formed by the first patterning is very thin, the first SiON hard mask pattern 162 is applied to the entire surface of the second photoresist layer 130 so that the same problem as that of FIG. 2 does not occur.

다음, 리소그라피 공정을 수행하여 제2 포토레지스트 패턴 (132)을 형성 (도 1e 참조)하고, 형성된 제2 포토레지스트 패턴 (132)을 식각 마스크로 이용하여 제1 SiON 하드 마스크 패턴 (162)을 식각하여 제2 SiON 하드 마스크 패턴 (164)을 형성한다 (도 3f 참조).Next, a second photoresist pattern 132 is formed by performing a lithography process (see FIG. 1E), and the first SiON hard mask pattern 162 is etched using the formed second photoresist pattern 132 as an etching mask. To form a second SiON hard mask pattern 164 (see FIG. 3F).

다음, 제2 포토레지스트 패턴 (132)을 제거하고 (도 3g 참조), 제2 SiON 하드 마스크 패턴 (164)을 식각 마스크로 이용하여 비정질 탄소 하드 마스크 층 (150)을 식각하여 비정질 탄소 하드 마스크 패턴 (152)을 형성한다 (도 3h 참조).Next, the second photoresist pattern 132 is removed (see FIG. 3G), and the amorphous carbon hard mask layer 150 is etched using the second SiON hard mask pattern 164 as an etching mask, thereby etching the amorphous carbon hard mask pattern. 152 is formed (see FIG. 3H).

다음, 제2 SiON 하드 마스크 패턴 (164)을 제거하고, 비정질 탄소 하드 마스크 패턴 (152)을 식각 마스크로 이용하여 피식각층 (110)을 식각하여 피식각층 패턴 (116)을 형성한 다음 (도 3i 참조), 비정질 탄소 하드 마스크 패턴 (152)을 제거한다 (도 3j 참조).Next, the second SiON hard mask pattern 164 is removed, and the etching target layer 110 is etched using the amorphous carbon hard mask pattern 152 as an etching mask to form the etching target layer pattern 116 (FIG. 3I). Reference), removing the amorphous carbon hard mask pattern 152 (see FIG. 3J).

일반적인 반도체 공정에서 라인 (line) 또는 바 (bar) 패턴을 형성할 때 비정질 탄소 하드 마스크층 (150)의 두께는 500~3000Å 정도로 형성하는데, SiON 하드 마스크층 (160)은 식각 선택비가 높기 때문에 50~400Å의 얇은 두께로 형성되어도 비정질 탄소층의 식각이 가능하다. 즉, 50~400Å의 얇은 두께의 SiON에 형성된 토폴로지는 후속 리소그라피 공정에 미치는 영향이 매우 적으므로 2차 패터닝을 불량 없이 수행할 수 있다.When forming a line or bar pattern in a general semiconductor process, the thickness of the amorphous carbon hard mask layer 150 is about 500 to 3000Å, and the SiON hard mask layer 160 has a high etching selectivity. Even when formed to a thin thickness of ˜400 kPa, the amorphous carbon layer can be etched. That is, the topology formed on the SiON having a thin thickness of 50 to 400 Å has a very small influence on the subsequent lithography process, so that the secondary patterning can be performed without defects.

본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.Preferred embodiments of the present invention are for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, and such modifications may be made by the following claims. Should be seen as belonging to.

이상에서 살펴본 바와 같이, 본 발명에서는 이중 노광 공정으로 미세 패턴을 형성할 때 SiON층/비정질 탄소층을 식각 마스크로 이용한다. 따라서, 식각 선택비가 높은 SiON의 특성상 SiON 층을 매우 얇게 형성하여 식각 공정을 진행함으로써 1차 패터닝 과정에서 형성된 패턴의 두께가 매우 얇아서 2차 패터닝을 불량 없이 진 행할 수 있다.As described above, in the present invention, the SiON layer / amorphous carbon layer is used as an etching mask when forming a fine pattern in a double exposure process. Therefore, by forming the SiON layer very thin due to the characteristics of SiON having a high etching selectivity, the pattern formed in the first patterning process is very thin, and thus the secondary patterning can be performed without defect.

Claims (7)

이중 노광 공정을 이용한 미세 패턴 형성방법에 있어서,In the method of forming a fine pattern using a double exposure process, SiON층/비정질 탄소층을 식각 마스크로 사용하는 것을 특징으로 하는 미세 패턴 형성방법.A fine pattern forming method comprising using an SiON layer / amorphous carbon layer as an etching mask. 제 1 항에 있어서, 상기 방법은The method of claim 1 wherein the method is 피식각층 상부에 비정질 탄소층과 SiON 층을 순차적으로 형성하는 단계;Sequentially forming an amorphous carbon layer and a SiON layer on the etched layer; 상기 SiON 층 상부에 제1 포토레지스트 패턴을 형성하는 단계;Forming a first photoresist pattern on the SiON layer; 상기 제1 포토레지스트 패턴을 식각 마스크로 하여 상기 SiON 층을 식각하여 제1 SiON 패턴을 형성하는 단계;Etching the SiON layer using the first photoresist pattern as an etching mask to form a first SiON pattern; 상기 제1 포토레지스트 패턴을 제거하는 단계;Removing the first photoresist pattern; 상기 SiON 패턴 전면에 제2 포토레지스트 층을 형성하는 단계;Forming a second photoresist layer on the entire surface of the SiON pattern; 제2 포토레지스트 층에 리소그라피 공정을 수행하여 제2 포토레지스트 패턴을 형성하는 단계;Performing a lithography process on the second photoresist layer to form a second photoresist pattern; 상기 제2 포토레지스트 패턴을 식각 마스크로 하여 제2 SiON 패턴을 형성하는 단계;Forming a second SiON pattern using the second photoresist pattern as an etching mask; 상기 제2 포토레지스트 패턴을 제거하는 단계;Removing the second photoresist pattern; 상기 제2 SiON 패턴을 식각 마스크로 하여 상기 비정질 탄소층을 식각하여 비정질 탄소층 패턴을 형성하는 단계; 및Etching the amorphous carbon layer by using the second SiON pattern as an etching mask to form an amorphous carbon layer pattern; And 상기 비정질 탄소층 패턴을 식각 마스크로 하여 피식각층 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 미세 패턴 형성방법.And forming an etched layer pattern by using the amorphous carbon layer pattern as an etching mask. 제 2 항에 있어서,The method of claim 2, 상기 비정질 탄소층은 500~3000Å의 두께로 형성되는 것을 특징으로 하는 미세 패턴 형성방법.The amorphous carbon layer is a fine pattern forming method, characterized in that formed in a thickness of 500 ~ 3000Å. 제 2 항에 있어서,The method of claim 2, 상기 SiON 층은 50~400Å의 두께로 형성되는 것을 특징으로 하는 미세 패턴 형성방법.The SiON layer is a fine pattern forming method, characterized in that formed in a thickness of 50 ~ 400Å. 제 2 항에 있어서,The method of claim 2, 상기 제1 포토레지스트 패턴 제거 및 제2 포토레지스트 패턴 제거 공정은 비정질 탄소층에 대하여 선택적으로 수행되는 것을 특징으로 하는 미세 패턴 형성방법.The first photoresist pattern removal and the second photoresist pattern removal process is selectively performed for the amorphous carbon layer. 제 2 항에 있어서,The method of claim 2, 상기 제1 포토레지스트 패턴 제거 및 제2 포토레지스트 패턴 제거 공정은 습식 방법으로 실시하는 것을 특징으로 하는 미세 패턴 형성방법.And removing the first photoresist pattern and the second photoresist pattern by a wet method. 제 6 항에 있어서,The method of claim 6, 상기 습식 방법은 포토레지스트 내의 중합체를 용해시킬 수 있는 화학물질을 이용하여 수행되는 것을 특징으로 하는 미세 패턴 형성방법.Wherein the wet method is performed using a chemical capable of dissolving the polymer in the photoresist.
KR1020050053930A 2005-06-22 2005-06-22 Forming method of fine pattern using double exposure process KR100720243B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050053930A KR100720243B1 (en) 2005-06-22 2005-06-22 Forming method of fine pattern using double exposure process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050053930A KR100720243B1 (en) 2005-06-22 2005-06-22 Forming method of fine pattern using double exposure process

Publications (2)

Publication Number Publication Date
KR20060134330A true KR20060134330A (en) 2006-12-28
KR100720243B1 KR100720243B1 (en) 2007-05-22

Family

ID=37812723

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050053930A KR100720243B1 (en) 2005-06-22 2005-06-22 Forming method of fine pattern using double exposure process

Country Status (1)

Country Link
KR (1) KR100720243B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100110363A (en) * 2008-01-29 2010-10-12 브레우어 사이언스 인코포레이션 On-track process for patterning hardmask by multiple dark field exposures
KR101045371B1 (en) * 2008-12-22 2011-06-30 주식회사 하이닉스반도체 Method of forming fine patterns by using double patterning

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101062830B1 (en) * 2007-11-02 2011-09-07 주식회사 하이닉스반도체 Method of forming fine pattern of semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100510558B1 (en) * 2003-12-13 2005-08-26 삼성전자주식회사 Method for forming pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100110363A (en) * 2008-01-29 2010-10-12 브레우어 사이언스 인코포레이션 On-track process for patterning hardmask by multiple dark field exposures
KR101045371B1 (en) * 2008-12-22 2011-06-30 주식회사 하이닉스반도체 Method of forming fine patterns by using double patterning

Also Published As

Publication number Publication date
KR100720243B1 (en) 2007-05-22

Similar Documents

Publication Publication Date Title
KR100761857B1 (en) Method for forming fine pattern in semiconductor device and method for semiconductor device using the same
US20060292497A1 (en) Method of forming minute pattern of semiconductor device
JP2008166732A (en) Method of manufacturing semiconductor element
US20090311635A1 (en) Double exposure patterning with carbonaceous hardmask
TW201543564A (en) Semiconductor fabrication method
KR100823847B1 (en) Method for patterning a semiconductor device
KR20070069914A (en) Method for forming fine pattern in semiconductor device
US6811959B2 (en) Hardmask/barrier layer for dry etching chrome films and improving post develop resist profiles on photomasks
KR100849190B1 (en) Method for forming fine pattern in semiconductor device
KR20020000481A (en) Fine pattern formation method and semiconductor device or liquid crystal device manufacturing method employing this method
KR100720243B1 (en) Forming method of fine pattern using double exposure process
KR100983708B1 (en) Method for forming a pattern of semiconductor device
KR20070000204A (en) Method for manufacturing fine pattern
KR20060136174A (en) Method for manufacturing fine pattern
KR100790564B1 (en) Method for forming the phase shifting mask
JP2006080361A (en) Method of manufacturing stencil mask
KR20080004211A (en) Method for forming fine pattern of semiconductor device
KR100827520B1 (en) Method for manufacturing semiconductor device
JP2008283165A (en) Formation method for hard mask pattern of semiconductor element
KR100912958B1 (en) Method for fabricating fine pattern in semiconductor device
KR100818387B1 (en) Method for forming metal line of semiconductor device
JP2009170863A (en) Method of forming pattern of semiconductor device
KR20070068909A (en) Method of fabricating photo mask using reverse photoresist pattern
KR100406584B1 (en) Method for fabricating phase shift mask
KR20080002493A (en) Method for forming micropattern in semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110429

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee