KR20060133692A - Semiconductor device having recess gate - Google Patents

Semiconductor device having recess gate Download PDF

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KR20060133692A
KR20060133692A KR1020050053462A KR20050053462A KR20060133692A KR 20060133692 A KR20060133692 A KR 20060133692A KR 1020050053462 A KR1020050053462 A KR 1020050053462A KR 20050053462 A KR20050053462 A KR 20050053462A KR 20060133692 A KR20060133692 A KR 20060133692A
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South Korea
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gate
active region
semiconductor device
recess
gates
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KR1020050053462A
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Korean (ko)
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오상원
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주식회사 하이닉스반도체
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Publication of KR20060133692A publication Critical patent/KR20060133692A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor device is provided to prevent the degradation of refresh characteristics by restraining the loss of an isolation layer using an island type recess gate structure. Isolation layers(13) are formed on field regions to define a plurality of active regions(11) isolated from each other. A plurality of recess gates(12) are vertically formed on the active regions, respectively. The recess gate is formed like an island type structure. Every two recess gates are formed across one active region. The two recess gates are spaced apart from each other on the active region, so that a portion of the active region exists between the two recess gate.

Description

리세스 게이트를 구비한 반도체 소자{SEMICONDUCTOR DEVICE HAVING RECESS GATE}Semiconductor device with recess gate {SEMICONDUCTOR DEVICE HAVING RECESS GATE}

도 1은 종래기술에 따른 R(Recess)-게이트를 구비한 반도체 소자의 평면도.1 is a plan view of a semiconductor device having an R (Recess) -gate according to the prior art.

도 2는 도 1에 도시된 I-I' 절취선을 따라 도시한 SEM(Scanning Electron Microscope) 사진.FIG. 2 is a SEM (Scanning Electron Microscope) photograph taken along the line II ′ of FIG. 1.

도 3은 본 발명의 바람직한 실시예에 따른 R-게이트를 구비한 반도체 소자의 평면도.3 is a plan view of a semiconductor device having an R-gate in accordance with a preferred embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1, 11 : 액티브1, 11: active

2, 12 : R-게이트2, 12: R-gate

3, 13 : 소자 분리막 3, 13: device isolation membrane

본 발명은 반도체 소자에 관한 것으로, 특히 R(Recess)-게이트를 구비한 반도체 소자에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to semiconductor devices having R (recess) gates.

반도체 산업이 발전하고, 패턴의 형성이 점차 미세화되어 감에 따라 100nm급 이하의 패턴을 갖는 반도체 소자가 개발되고 있다. 패턴이 미세화되어 감에 따라 그에 따른 리프레쉬(refresh) 특성이 요구되고 있으며, 게이트와 액티브 영역(active region)과의 접촉면적을 확대하기 위하여 입체적인 패턴구조를 시도하고 있다. 입체적인 패턴구조 중 하나로 트렌치(trench) 구조를 갖는 R-게이트 소자가 제안되었다. As the semiconductor industry develops and the pattern formation gradually becomes finer, semiconductor devices having patterns of 100 nm or less have been developed. As the pattern becomes finer, a refresh characteristic is required, and a three-dimensional pattern structure is attempted to increase the contact area between the gate and the active region. As one of the three-dimensional pattern structure, an R-gate device having a trench structure has been proposed.

100nm 이하의 선폭을 갖는 반도체 소자, 예컨대 DRAM 소자의 셀 트랜지스터에서 요구되는 셀 문턱전압(threshold voltage)을 만족시키기 위해서는 채널 도핑(channel doping) 농도가 1018/cm3 이상이 필요하며, 이런 이유로 전기장(electric field)에 의한 접합 누설전류(junction leakage current) 때문에 더 이상 데이터 유지(data retention) 특성에 대한 요구 조건을 충족할 수 없는 상황이다. 따라서, 기존의 평면 타입(planar type)의 셀 트랜지스터를 리세스 채널(recessed channel)로 바꿔 유효채널길이(effective channel length)를 증가시키고, 채널 도핑 농도를 1017/cm3 수준으로 낮추어 전기장을 효과적으로 감소시킴으로써 접합 누설전류 측면에서 양호한 소자의 특성을 확보하여 리프레쉬(refresh) 특성을 개선시킬 수 있는 R-게이트 소자가 제안되었다. In order to satisfy the cell threshold voltage required in the cell transistor of a semiconductor device, such as a DRAM device having a line width of 100 nm or less, a channel doping concentration of 10 18 / cm 3 or more is necessary, and for this reason, Due to junction leakage currents caused by electrical fields, it is no longer possible to meet the requirements for data retention. Therefore, the planar type cell transistor is replaced with a recessed channel to increase the effective channel length and reduce the channel doping concentration to 10 17 / cm 3 to effectively reduce the electric field. By reducing the R-gate device has been proposed that can improve the refresh characteristics by securing a good device characteristics in terms of junction leakage current.

도 1은 종래기술에 따른 반도체 R-게이트 소자를 구비한 반도체 소자를 설명 하기 위하여 도시한 평면도이고, 도 2는 도 1에 도시된 I-I' 절취선을 따라 도시한 단면도이다. 1 is a plan view illustrating a semiconductor device having a semiconductor R-gate device according to the prior art, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

도 1에 도시된 바와 같이, 종래기술에 따른 R-게이트 소자를 구비한 반도체 소자에서 R-게이트(2)는 라인타입(line type)으로 X축방향의 액티브영역(1)과 수직하도록 Y축방향으로 신장된다. 이러한 R-게이트(2)는 라인타입 마스크를 이용한 식각공정을 실시하여 라인타입으로 트렌치(trench, 미도시)를 형성한 후 상기 트렌치가 매립되도록 폴리 실리콘막과 텅스텐 실리사이드층을 순차적으로 증착하여 형성한다. As shown in FIG. 1, in the semiconductor device having the R-gate device according to the related art, the R-gate 2 is a line type, and the Y-axis is perpendicular to the active region 1 in the X-axis direction. Extend in the direction. The R-gate 2 is formed by performing an etching process using a line type mask to form a trench in a line type, and then depositing a polysilicon layer and a tungsten silicide layer sequentially so that the trench is buried. do.

그러나, 이러한 구조에서는 R-게이트 형성공정, 즉 트렌치 형성공정시 도시된 'A' 부위에서와 같이 필드영역에 형성된 소자 분리막(3)과 트렌치가 형성될 영역이 서로 중첩되고, 이로 인하여 트렌치가 형성될 영역과 중첩되는 소자 분리막(3)의 일부가 식각되어 소자의 리프레쉬 특성이 저하되는 문제가 발생된다. 또한, 소자 분리막(3)의 손실로 인해 도 2에 도시된 바와 같이 후속 공정을 통해 그 상부에 증착되는 텅스텐 실리사이드층에 심(seam)(B)이 심해지는 경우 게이트 식각공정 후 좌우 비대칭으로 텅스텐 실리사이드층이 남게 되고, 이로 인하여 후속 공정을 통해 산화막과 질화막이 비정상적으로 형성되어, 랜딩 플러그(landing plug) 컨택홀 형성공정시 자기 정렬 컨택(self aligned contact) 불량이 발생되는 문제점이 있다. However, in such a structure, the device isolation film 3 formed in the field region and the region where the trench is to be formed overlap with each other, as in the 'A' region shown in the R-gate forming process, that is, the trench forming process, thereby forming a trench. A portion of the device isolation layer 3 overlapping the region to be etched is etched, which causes a problem in that the refresh characteristics of the device are degraded. In addition, when the seam (B) is deepened on the tungsten silicide layer deposited on the upper layer through the subsequent process as shown in FIG. 2 due to the loss of the device isolation layer 3, the tungsten may be asymmetrically left and right after the gate etching process. The silicide layer remains, and thus, an oxide film and a nitride film are abnormally formed through a subsequent process, so that a self-aligned contact defect occurs during the landing plug contact hole formation process.

따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출된 것으로서, R-게이트 공정시 트렌치가 형성될 영역과 중첩되는 소자 분리막의 손실을 방지하여 소자의 리프레쉬 특성이 저하되는 것을 방지하고, 후속 공정을 통해 증착되는 텅스텐 실리사이드층에 심이 발생되는 것을 억제하여 후속 공정을 통해 증착되는 산화막 및 질화막의 프로파일을 안정화시킴으로써 랜딩 플러그 컨택홀 형성공정시 자기 정렬 컨택 불량이 발생되는 것을 방지할 수 있는 반도체 소자를 제공하는데 그 목적이 있다. Accordingly, the present invention has been made to solve the above problems of the prior art, to prevent the loss of the device isolation layer overlapping the region where the trench is to be formed during the R-gate process to prevent the refresh characteristics of the device is lowered, By preventing the generation of seams in the tungsten silicide layer deposited through the subsequent process to stabilize the profile of the oxide film and the nitride film deposited through the subsequent process, a semiconductor capable of preventing self-aligned contact defects from occurring during the landing plug contact hole forming process The object is to provide an element.

상기한 목적을 달성하기 위한 일측면에 따른 본 발명은, 필드영역에 형성된 소자 분리막과, 상기 소자 분리막에 의해 고립된 복수의 액티브영역과, 상기 액티브영역을 수직으로 교차하도록 섬 형태로 형성된 복수의 R-게이트를 포함하는 반도체 소자를 제공한다. According to an aspect of the present invention, there is provided a device isolation film formed in a field region, a plurality of active regions isolated by the device isolation layer, and a plurality of islands formed to vertically intersect the active region. Provided is a semiconductor device including an R-gate.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명한다. 또한, 명세서 전체에 걸쳐서 동일한 참조번호로 표시된 부분은 동일한 구성요소들을 나타낸다. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals throughout the specification represent the same components.

실시예Example

도 3은 본 발명의 바람직한 실시예에 따른 R-게이트를 구비한 반도체 소자를 설명하기 위하여 도시한 평면도이다. 3 is a plan view illustrating a semiconductor device having an R-gate according to a preferred embodiment of the present invention.

도 3에 도시된 바와 같이, 본 발명의 바람직한 실시예에 따른 반도체 소자는 필드영역에 형성된 소자 분리막(13)과, 소자 분리막(13)에 의해 고립된 복수의 액티브영역(11)과, 액티브영역(11)을 수직으로 교차하도록 섬 형태로 형성된 복수의 R-게이트(12)를 포함한다. 또한, 액티브영역(11)의 장방향(X축방향)으로 대향하도록 서로 인접하게 형성된 액티브영역(11) 사이에는 R-게이트(12)가 형성되지 않는다. R-게이트(12)는 하나의 액티브영역(11)에 두개가 교차하도록 형성되며, 서로 다른 액티브영역(11)과 교차하는 인접한 R-게이트(12)와는 독립적으로 분리되도록형성된다. As shown in FIG. 3, a semiconductor device according to an exemplary embodiment of the present invention may include an isolation layer 13 formed in a field region, a plurality of active regions 11 isolated by the isolation layer 13, and an active region. And a plurality of R-gates 12 formed in an island shape to vertically intersect with (11). In addition, the R-gate 12 is not formed between the active regions 11 formed adjacent to each other so as to face in the longitudinal direction (the X-axis direction) of the active region 11. The R-gates 12 are formed to intersect two in one active region 11, and are formed to be separated independently from adjacent R-gates 12 that cross different active regions 11.

제조방법을 살펴보면, 우선 액티브영역(11)이 X축방향으로 섬 형태를 갖도록 STI(Shallow Trench Isolation) 마스크를 제작한 후 이 STI 마스크를 이용하여 소자 분리막(13)용 트렌치를 형성한다. 그런 다음, 트렌치가 매립되도록 소자 분리막(13)을 형성한 후 액티브영역(11)의 단축방향(Y축방향)으로 교차하도록 섬 형태를 갖는 R-게이트 마스크를 제작한 후 이 R-게이트 마스크를 이용하여 액티브영역(11)을 교차하는 트렌치를 형성한다. 그런 다음, 상기 트렌치가 매립되도록 폴리 실리콘막과 텅스텐 실리사이드층을 순차적으로 증착한 후 식각하여 R-게이트(12)를 형성한다. Referring to the manufacturing method, first, a shallow trench isolation (STI) mask is manufactured such that the active region 11 has an island shape in the X-axis direction, and then a trench for the device isolation layer 13 is formed using the STI mask. Next, after forming the isolation layer 13 to fill the trench, an R-gate mask having an island shape is formed to intersect in the short axis direction (Y-axis direction) of the active region 11, and then the R-gate mask is formed. To form a trench that crosses the active region 11. Thereafter, the polysilicon layer and the tungsten silicide layer are sequentially deposited so as to fill the trench, and then etched to form an R-gate 12.

본 발명의 기술 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한 다. 또한, 본 발명은 이 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예들이 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

이상에서 설명한 바와 같이, 본 발명에 의하면, 액티브영역을 수직으로 교차하도록 섬 형태로 형성된 복수의 R-게이트를 형성하여 R-게이트 공정시 트렌치가 형성될 영역과 중첩되는 소자 분리막의 손실을 방지하여 소자의 리프레쉬 특성이 저하되는 것을 방지할 수 있다. 또한, 후속 공정을 통해 증착되는 텅스텐 실리사이드층에 심이 발생되는 것을 억제하여 후속 공정을 통해 증착되는 산화막 및 질화막의 프로파일을 안정화시킴으로써 랜딩 플러그 컨택홀 형성공정시 자기 정렬 컨택 불량이 발생되는 것을 방지할 수 있다. As described above, according to the present invention, a plurality of R-gates formed in an island shape to vertically cross the active region is formed to prevent the loss of the device isolation layer overlapping the region where the trench is to be formed during the R-gate process. Degradation of the refresh characteristics of the device can be prevented. In addition, by suppressing the generation of seams in the tungsten silicide layer deposited through a subsequent process to stabilize the profile of the oxide film and the nitride film deposited through the subsequent process to prevent the occurrence of self-aligned contact defects during the landing plug contact hole forming process. have.

Claims (4)

필드영역에 형성된 소자 분리막;An isolation layer formed in the field region; 상기 소자 분리막에 의해 고립된 복수의 액티브영역; 및A plurality of active regions isolated by the device isolation layer; And 상기 액티브영역을 수직으로 교차하도록 섬 형태로 형성된 복수의 R-게이트A plurality of R-gates formed in an island shape to vertically intersect the active region 를 포함하는 반도체 소자.Semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 복수의 액티브영역 중 상기 액티브영역의 장방향으로 대향하도록 서로 인접하게 형성된 액티브영역 사이에는 상기 R-게이트가 형성되지 않는 반도체 소자.And the R-gate is not formed between the active regions of the plurality of active regions that are adjacent to each other so as to face in the longitudinal direction of the active region. 제 1 항 또는 제 2 항에 있어서, The method according to claim 1 or 2, 상기 R-게이트는 하나의 상기 액티브영역에 두개가 교차하도록 형성된 반도체 소자.And the R-gates are formed to cross two in one active region. 제 3 항에 있어서, The method of claim 3, wherein 상기 R-게이트는 서로 다른 상기 액티브영역과 교차하는 R-게이트와 독립적으로 분리된 반도체 소자.And the R-gate is independently separated from the R-gate crossing the different active regions.
KR1020050053462A 2005-06-21 2005-06-21 Semiconductor device having recess gate KR20060133692A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130004680A (en) * 2011-07-04 2013-01-14 삼성전자주식회사 Method of manufacturing a dram device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130004680A (en) * 2011-07-04 2013-01-14 삼성전자주식회사 Method of manufacturing a dram device

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