KR20060131334A - Layout for sub wordline driver in semiconductor memory device - Google Patents

Abstract

A sub-word line driver in a semiconductor memory device is provided to reduce a power noise of a couple-cap NMOS(Negative Metal Oxide Semiconductor) transistor in the memory device by reducing the width of another NMOS transistor, which is connected to the couple-cap NMOS transistor. First NMOS transistors(M1) are gated by a source voltage. A normal word line enable signal is applied on a drain of the first NMOS transistor. Second NMOS transistors(M2) are series-connected to an upper side of the first NMOS transistors and gated by a voltage, which is generated at source terminals of the first NMOS transistor. Third NMOS transistors(M3) are gated by a second control signal, which is delayed from the first control signal, and series-connected to a lower side of the first NMOS transistors. Fourth NMOS transistors(M4) are gated by a third control signal, which is inverted from the first control signal, and series-connected to a lower side of the third NMOS transistors. Fifth NMOS transistors(M5) are gated by the source voltage and arranged at one side of the second NMOS transistors. A ground voltage terminal is formed at a lower side of the fourth NMOS transistors.

Description

Layout of Sub-Wordline Driver in Semiconductor Memory Device

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a circuit diagram illustrating a general sub-wordline driver (SWD).

FIG. 2 is a view showing a state in which the circuit shown in FIG. 1 is laid out on a wafer.

FIG. 3 illustrates a couple cap connected between the boosted power supply terminal VPP and the ground power supply terminal VSSW in the SWD circuit shown in FIG. 1.

4 is a diagram illustrating a layout structure of a SWD region in a semiconductor memory device according to an embodiment of the present invention.

5 is a diagram illustrating a layout structure of a SWD region according to another embodiment of the present invention in a semiconductor memory device.

The present invention relates to the layout of a semiconductor memory device, and more particularly to the layout of a sub-wordline driver (SWD) of a semiconductor memory device.

In general, a sub-word line driver (SWD) region exists to boost a word line to a boosted voltage VPP level in a core region of a semiconductor memory device. The sub-wordline driver drives the corresponding wordline WL in response to the normal wordline enable signal NWE and the control signal PXI * generated from the row address decoder. At this time, the normal word line enable signal NWE and the control signal PXI * are enabled at the power supply voltage VPP level.

1 is a circuit diagram illustrating a general sub-wordline driver (SWD). 2 is a view showing a state in which the circuit shown in FIG. 1 is laid out on a wafer. 1 and 2, in the SWD region, the first to fourth NMOS transistors M1 to M4, the control signal PXI *, and the power supply voltage VPP are symmetric with respect to the ground power supply VSSW. Is placed. Meanwhile, in the case of the power supply voltage VPP in the semiconductor memory device, a couple cap is generally mounted between the power supply voltage terminals in order to minimize power noise.

However, in the related art, a couple cap does not exist between the power supply voltage VPP and the ground power supply VSSW, thereby causing noise in the power supply terminal.

An object of the present invention is to provide a semiconductor memory device in which a couple cap is laid out for noise removal between a power supply voltage terminal and a ground power supply terminal while minimizing layout loss in a sub-wordline driver region.

In order to achieve the above technical problem, the semiconductor memory according to the present invention includes a row address decoder for generating a normal word line enable signal and a first to third control signals for decoding the row address to control the enable of the corresponding word line The device comprises a plurality of first NMOS transistors arranged in series with a normal wordline enable signal applied to the drain and gated by a boosted power source, a first control signal applied to the drain and a source connected to the corresponding wordline Gated by a voltage occurring at the source of each of the NMOS transistors, a plurality of second NMOS transistors, a normal wordline enable signal, applied in series on top of the plurality of first NMOS transistors, are applied to the drain and the corresponding wordline A source is connected to the gate and the first control signal is gated by the second control signal with a predetermined time delay. And a plurality of third NMOS transistors arranged in series under the plurality of first NMOS transistors, a third control signal having a drain connected to a corresponding word line, a source connected to a ground power supply terminal, and a first control signal inverted A boosted power source gated by a plurality of fourth NMOS transistors and drains and sources arranged in series below the third NMOS transistors and connected to a ground power source and laid out to pass to one side of the plurality of second NMOS transistors. And a sub-wordline driver comprising a fifth NMOS transistor gated by one side of the plurality of second NMOS transistors, the ground power stage being laid under the plurality of fourth NMOS transistors. Do.

In order to achieve the above technical problem, the semiconductor memory according to the present invention includes a row address decoder for generating a normal word line enable signal and a first to third control signals for decoding the row address to control the enable of the corresponding word line The apparatus comprises a plurality of first NMOS transistors arranged in series with a normal wordline enable signal applied to a drain and gated by a boosted power source, a first control signal applied to the drain and a source connected to the wordline. Gated by a voltage occurring at the source of each of the 1 NMOS transistors, a plurality of second NMOS transistors, in which a normal wordline enable signal is applied to the drain and arranged in series above the plurality of first NMOS transistors, are applied to the corresponding word. A source is connected to the line and the first control signal is gated by the second control signal with a predetermined time delay. And a third control signal in which a drain is connected to a plurality of third NMOS transistors arranged in series under the plurality of first NMOS transistors and a corresponding word line, a source is connected to a ground power supply terminal, and the first control signal is inverted. And a plurality of fourth NMOS transistors arranged in series under the third NMOS transistors, wherein a ground power stage is laid under the plurality of fourth NMOS transistors, and the boost power supply is above the ground power stage. It is desirable to have a sub-wordline driver that is laid out so that the stage passes.

In accordance with an aspect of the present invention, there is provided a semiconductor memory device including a row address decoder configured to decode a row address to control an enable of a corresponding word line and generate first to third control signals. Are a plurality of first NMOS transistors arranged in series with a normal wordline enable signal applied to a drain and gated by a boosted power source, a first control signal applied to the drain, a source connected to the corresponding wordline, and a first NMOS. Gated by a voltage occurring at the source of each of the transistors, a plurality of second NMOS transistors arranged in series above the plurality of first NMOS transistors, a normal wordline enable signal is applied to the drain and applied to the corresponding wordline. The source is connected and the first control signal is gated by the second control signal with a predetermined time delay. And a plurality of third NMOS transistors arranged in series under the plurality of first NMOS transistors, a third control signal having a drain connected to a corresponding word line, a source connected to a ground power supply terminal, and a first control signal inverted A boosted power source gated by a plurality of fourth NMOS transistors and drains and sources arranged in series below the third NMOS transistors and connected to a ground power source and laid out to pass to one side of the plurality of second NMOS transistors. And a fifth NMOS transistor gated by one side of the plurality of second NMOS transistors, wherein a ground power stage is laid under the plurality of fourth NMOS transistors, and a boosted power stage passes over the ground power stage. It is desirable to have a sub-wordline driver laid out such that

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings. In understanding the drawings, it should be noted that like parts are intended to be represented by the same reference numerals as much as possible. Incidentally, detailed descriptions of well-known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a sub-wordline driver of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 3, a sub-wordline driver of a semiconductor memory device according to an embodiment of the present invention is substantially composed of first to fifth NMOS transistors M1 to M5. Here, the first NMOS transistor M1 is applied with a normal word line enable signal NWE to a drain and is gated by the boost power supply VPP. The second NMOS transistor M2 has a first control signal PXID applied to a drain, a source connected to the word line WL, and gated by a voltage generated in the source of the first NMOS transistor M1. In the third NMOS transistor M3, a normal word line enable signal NWE is applied to a drain, a source is connected to the word line WL, and gated by the second control signal PXIDG. The fourth NMOS transistor M4 has a drain connected to the word line WL, a source connected to the ground power supply terminal VSSW, and gated by the third control signal PXIB. In this case, the first and second control signals PXID and PXIDG are signals having a predetermined delay. The first control signal PXID is enabled and the second control signal PXIDG is enabled after a predetermined time. The third control signal PXIB is a signal in which the first control signal PXID is inverted.

Referring to the operation of the sub-word line driver SWD shown in FIG. 3, the normal word line enable signal NWE and the first and second control signals PXID, When the PXIDG is enabled and the third control signal PXIB is disabled, the first to third NMOS transistors M1 to M3 are turned on and the fourth NMOS transistor M4 is turned off. The word line WL is enabled at the boosted power supply level VPP by the turned on first to third NMOS transistors M1 to M3. When the third control signal PXIB is enabled by the row address decoder (not shown) and the normal word line enable signal NWE and the first and second control signals PXID and PXIDG are disabled, the third control signal PXIB is disabled. The first to third NMOS transistors M1 to M3 are turned off and the fourth NMOS transistor M4 is turned on. The word line WL is disabled to the ground power supply VSSW level by the turned-on fourth NMOS transistor M4.

In the SWD circuit shown in FIG. 3, a couple cap connected between a boosted power supply terminal VPP and a ground power supply terminal VSSW is shown. As shown in FIG. 3, a fifth NMOS transistor M5 is substantially formed between the boosted power supply terminal VPP and the ground power supply terminal VSSW. The fifth NMOS transistor M5 serves as a couple cap M5 between the boosted power supply terminal VPP and the ground power supply terminal VSSW. In this case, it is important that the fifth NMOS transistor M5 is laid out with a minimum layout loss in the SWD region of the semiconductor memory device.

4 is a diagram illustrating a layout of a sub-wordline driver of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4, in the SWD region, the first to fifth NMOS transistors M1 to M5, the control signal PXI *, and the power supply voltage VPP are arranged symmetrically with respect to the ground power supply VSSW. . Specifically, each of the plurality of first NMOS transistors M1 arranged in series is applied with a normal word line enable signal NWE to a drain and gated by the boost power supply VPP. The plurality of second NMOS transistors M2 are arranged in series above the plurality of first NMOS transistors M1, and the first control signal PXID is applied to the drain and the source is connected to the corresponding word line. Gated by the voltage generated in the source of each of the NMOS transistors M1. The plurality of third NMOS transistors M3 are arranged in series below the plurality of first NMOS transistors M1, and a normal word line enable signal NWE is applied to a drain and a source is connected to the corresponding word line. The first control signal PXID is gated by the second control signal PXIDG which is delayed by a predetermined time. The plurality of fourth NMOS transistors M4 are arranged in series under the plurality of third NMOS transistors M3, a drain is connected to a corresponding word line, a source is connected to a ground power supply terminal, and a third control signal PXIB. Is gated by. As shown, a ground power supply terminal VSSW is laid under the plurality of fourth NMOS transistors M4, and a plurality of first to fourth NMOS transistors M1 to M4 around the ground power supply terminal VSSW. Are symmetrically laid out vertically. In addition, in FIG. 4, the ground power supply terminal VSSW is laid under the plurality of fourth NMOS transistors M4.

In addition, the fifth NMOS transistor M5 includes a boosted power supply VPP in which a drain and a source are connected to the ground power supply terminal VSSW by the contact hole 100 and passed to one side of the plurality of second NMOS transistors M2. Gated and arranged on one side of the plurality of second NMOS transistors M2.

As such, since the fifth NMOS transistor M5 can be laid out on the boosted power supply (VPP) node without providing a separate layout space for the layout of the fifth NMOS transistor M5, power noise is eliminated with little layout loss. The fifth NMOS transistor M5 may be laid out.

Meanwhile, as shown in FIG. 4, when the fifth NMOS transistor M5 is laid out, a couple cap is formed between the boosted power supply terminal VPP and the ground power supply terminal VSSW to reduce power noise, as well as the second. The edge dummy effect of the NMOS transistor M2 can also be obtained. In FIG. 4, the second NMOS transistor M2 positioned at the right end of the plurality of second NMOS transistors M2 is subjected to more process change than other second NMOS transistors. At this time, by arranging the fifth NMOS transistor M5 next to the second NMOS transistor M2, the fifth NMOS transistor M5 is edged to minimize the process change of the second NMOS transistor M2 located at the end of the array. It acts as a dummy.

5 is a diagram illustrating a layout structure of a SWD region according to another embodiment of the present invention in a semiconductor memory device.

In FIG. 5, the width of the second NMOS transistor M2 arranged upside down symmetrically with respect to the ground power supply VSSW is reduced, and the fourth NMOS transistor M4 is reduced to the second NMOS transistor M2 by the reduced width. To increase the ground power (VSSW) space. By allowing the boosted power supply VPP to pass between the widened ground power supply VSSW, a fifth NMOS transistor M5 naturally serving as a couple cap is formed. As such, by laying down the fifth NMOS transistor M5 by reducing the width of the second NMOS transistor M2, the fifth NMOS transistor M5 may be laid out to reduce power noise elimination while almost no layout loss occurs.

Both layout structures described above can lay out the NMOS transistor M5 serving as a couple cap for reducing power noise between the boosted power supply terminal VPP and the grounded power supply terminal VSSW with almost no layout loss. . At this time, if the fifth NMOS transistors of FIGS. 4 and 5 are laid out together in the SWD region, the power noise removing effect can be further increased.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor memory device according to the present invention has an NMOS transistor which serves as a couple cap for reducing power noise between the boosted power supply terminal VPP and the ground power supply terminal VSSW with little layout loss in the SWD region. You can layout.

Claims (6)

A semiconductor memory device comprising a normal word line enable signal for decoding a row address to control an enable of a corresponding word line and a row address decoder for generating first to third control signals. A plurality of first NMOS transistors arranged in series with the normal wordline enable signal applied to a drain and gated by the boost power source; The first control signal is applied to a drain, a source is connected to a corresponding word line, gated by a voltage generated in a source of each of the first NMOS transistors, and is arranged in series on the plurality of first NMOS transistors. A plurality of second NMOS transistors; The normal word line enable signal is applied to a drain, a source is connected to the corresponding word line, and the first control signal is gated by the second control signal delayed by a predetermined time, and below the plurality of first NMOS transistors. A plurality of third NMOS transistors arranged in series; A plurality of fourths having a drain connected to the corresponding word line, a source connected to a ground power terminal, and gated by the third control signal in which a first control signal is inverted, and arranged in series under the third NMOS transistors; NMOS transistors; And A fifth NMOS transistor connected to the ground power source and gated by the boost power source arranged to pass to one side of the plurality of second NMOS transistors, the fifth NMOS transistor being arranged to one side of the plurality of second NMOS transistors Include, And the ground power supply terminal is disposed under the plurality of fourth NMOS transistors. The method of claim 1, wherein the plurality of first to fifth NMOS transistors And the sub word line driver of the semiconductor memory device is symmetrically laid out around the ground power supply terminal. A semiconductor memory device comprising a normal word line enable signal for decoding a row address to control an enable of a corresponding word line and a row address decoder for generating first to third control signals. A plurality of first NMOS transistors arranged in series with the normal wordline enable signal applied to a drain and gated by the boost power source; A first control signal is applied to the drain, a source is connected to the corresponding word line, gated by a voltage generated in the source of each of the first NMOS transistors, and is arranged in series on the plurality of first NMOS transistors. Second NMOS transistors; The normal word line enable signal is applied to a drain, a source is connected to the corresponding word line, and the first control signal is gated by the second control signal delayed by a predetermined time, and below the plurality of first NMOS transistors. A plurality of third NMOS transistors arranged in series; And A plurality of first drains connected to the corresponding word line, a source connected to a ground power supply terminal, gated by the third control signal inverted by the first control signal, and arranged in series under the third NMOS transistors; 4 NMOS transistors, And the ground power supply terminal is disposed under the plurality of fourth NMOS transistors, and the boost power supply terminal is disposed to pass over the ground power supply terminal. The method of claim 3, wherein the plurality of first to fifth NMOS transistors And the sub word line driver of the semiconductor memory device is symmetrically laid out around the ground power supply terminal. A semiconductor memory device comprising a normal word line enable signal for decoding a row address to control an enable of a corresponding word line and a row address decoder for generating first to third control signals. A plurality of first NMOS transistors arranged in series with the normal wordline enable signal applied to a drain and gated by the boost power source; A first control signal is applied to the drain, a source is connected to the corresponding word line, gated by a voltage generated in the source of each of the first NMOS transistors, and is arranged in series on the plurality of first NMOS transistors. Second NMOS transistors; The normal word line enable signal is applied to a drain, a source is connected to the corresponding word line, and the first control signal is gated by the second control signal delayed by a predetermined time, and below the plurality of first NMOS transistors. A plurality of third NMOS transistors arranged in series; A plurality of first drains connected to the corresponding word line, a source connected to a ground power supply terminal, gated by the third control signal inverted by the first control signal, and arranged in series under the third NMOS transistors; 4 NMOS transistors; And A fifth NMOS transistor connected to the ground power source and gated by the boost power source arranged to pass to one side of the plurality of second NMOS transistors, the fifth NMOS transistor being arranged to one side of the plurality of second NMOS transistors Include, And the ground power supply terminal is disposed under the plurality of fourth NMOS transistors, and the boost power supply terminal is disposed to pass over the ground power supply terminal. The method of claim 5, wherein the plurality of first to fifth NMOS transistors And the sub word line driver of the semiconductor memory device is symmetrically laid out around the ground power supply terminal.

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