KR20060131203A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to improve electrical properties and reliability by forming an oxide layer with same height to horn generated in recess gate etching and removing the oxide layer together with the horn. A substrate(11) having an isolation layer(12) to define an active region and a field region is prepared. A hard mask is deposited on the substrate. A plurality of trenches(15) are formed by etching the hard mask of the active region and the substrate. An oxide layer(18) is formed on the resultant structure by thermal oxidation processing. The oxide layer is removed. The oxide layer has the same height to a horn formed at both sidewalls of the trench.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A and 1B are plan and SEM photographs of a semiconductor device manufactured through an R-gate process according to the prior art.

2A and 2B are cross-sectional views and SEM photographs taken along the line X-X 'of FIG. 1A.

3A and 3B are cross-sectional views and SEM photographs taken along the line Y-Y 'shown in FIG. 1B.

4A to 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: active area

2: field area

3: R-gate

4 horn

11: substrate (active area)

12: device isolation film (field area)

13: hard mask (polysilicon film)

14 photosensitive film pattern

15: trench

16: horn

18 oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a R (recess) -gate electrode in a process of manufacturing a semiconductor device having a line width of 100 nm or less.

As the semiconductor industry develops and the pattern formation gradually becomes finer, semiconductor devices having patterns of 100 nm or less have been developed. As the pattern becomes finer, a refresh characteristic is required, and a three-dimensional pattern structure is attempted to increase the contact area between the gate and the active region. As one of the three-dimensional pattern structure, an R-gate electrode having a trench structure has been proposed.

In order to satisfy the cell threshold voltage required in the cell transistor of a semiconductor device, such as a DRAM device having a line width of 100 nm or less, a channel doping concentration of 10 ¹⁸ / cm ³ or more is necessary. Due to junction leakage currents caused by electrical fields, it is no longer possible to meet the requirements for data retention. Therefore, the planar type cell transistor is replaced with a recessed channel to increase the effective channel length and reduce the channel doping concentration to 10 ¹⁷ / cm ³ to effectively reduce the electric field. As a result, the R-gate process was performed to secure the characteristics of the device in terms of junction leakage current and to improve the refresh characteristics.

Such a gate electrode is manufactured through an R-gate process. Gate electrodes fabricated by the R-gate process are shown in FIGS. 1A and 1B, FIGS. 2A and 2B, and FIGS. 3A and 3B. Here, Figure 1 (a) is a cross-sectional view of the gate electrode, (b) is a SEM (Scanning Electron Microscope) photograph. 2A is a cross-sectional view taken along the line X-X 'of FIG. 1A, and (b) is a SEM photograph. 3A is a cross-sectional view taken along the line Y-Y 'shown in FIG. 1A, and FIG. 3B is a SEM photograph.

However, when the etching process is performed to pattern the gate electrode having the trench structure as a problem that occurs during the R-gate process, the etching selectivity between the field region and the active region is different from each other. And a horn 4 is formed as shown in (b). That is, as shown in (a) of FIG. 3, an oxide-based device isolation film 2 is formed in the field region, while the active region is formed of the silicon substrate 1, so that the etching selectivity is different from each other. The horn 4 is generated during the gate process. These horns concentrate the electric field and degrade the electrical properties.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and removes the horn generated by the different etching selectivity between the field region and the active region in the gate electrode forming process using the R-gate process It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent the electrical characteristics of the semiconductor chip from being lowered.

According to an aspect of the present invention, there is provided a device isolation layer, comprising: providing a substrate defined by an active region and a field region; depositing a hard mask on the substrate; Forming a plurality of trenches by etching the hard mask and the substrate, performing a thermal oxidation process on the upper surface of the entire structure on which the trench is formed, to form an oxide film, and removing the oxide film. Provided are a method of manufacturing a semiconductor device.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. Hereinafter, for convenience of description, a process cross-sectional view taken along a cutting line in the X-X 'direction of FIG. 1A will be described as an example.

First, as shown in FIG. 4A, a shallow trench isolation (STI) process is performed in the substrate 11 to form an isolation layer 12. Although not shown, the STI process is carried out in the following manner. First, after depositing a pad oxide film and a pad nitride film (not shown) on the substrate 11, an etching process is performed to form trenches (not shown) in the substrate 11. Then, a high density plasma (HDP) film (not shown) is deposited to fill the trench, and then planarized through a chemical mechanical polishing (CMP) process. Then, the isolation layer 12 is formed in the trench by removing the pad nitride layer and the pad oxide layer.

Subsequently, a polysilicon film 13 is deposited on the entire structure including the device isolation film 12 for a hard mask. Here, the polysilicon film 13 is deposited to a thickness of 800 to 1200 Å. Meanwhile, a pad oxide layer (not shown) may be formed under the polysilicon layer 13 in order to prevent the substrate 11 from being damaged during the subsequent etching process of the polysilicon layer 13.

Subsequently, as shown in FIG. 4B, the photoresist film is coated on the polysilicon film 13, and then the photoresist pattern 14 is formed by performing exposure and development processes using a photo mask. In this case, the photoresist film must have a resolution that can be formed smaller than the FICD (Final Inspection Critical Dimension) of the gate electrode (not shown) to be formed through the subsequent process, and for the hard mask in the R-gate etching process performed through the subsequent process. The film is deposited to a thickness such that the required depth of the polysilicon film 13 and the device isolation film 12 can be obtained.

Subsequently, as illustrated in FIG. 4C, an etching process using the photosensitive film pattern 14 (hereinafter, referred to as an R-gate etching process) is performed to recess the substrate 11 in the active region to a predetermined depth. . As a result, a trench 15 in which a plurality of gate electrodes are formed in the substrate 11 in the active region is formed. At this time, the horn 16 is formed in the form of horns on both sides of the trench 15, as shown in the same figure. This is due to the difference in etching selectivity between the substrate 11 in the active region and the device isolation film 12 in the field region as described above. The substrate 11 is made of silicon, and the device isolation film 12 is usually SiO _2. Because it is made of.

Meanwhile, in the R-gate etching process, it is preferable to control the process so that the upper both corner portions of the trench 15 are rounded, or for this purpose, a subsequent wall oxidation process may be performed. As such, the reason for rounding the upper both corner portions of the trench 15 is to stably form a gate oxide film (not shown) along the entire upper surface of the subsequent substrate 11.

Subsequently, as shown in FIG. 4D, a thermal oxidation process 17 is performed on the upper surface of the entire structure in which the trench 15 is formed to form an oxide film (SiO ₂ film) 18. At this time, the thermal oxidation process 17 is carried out within a temperature range of several tens to several hundred degrees, it is preferable to form the oxide film 18 so as to have a thickness equal to the thickness of the horn 16 by controlling the process time. As a result, an oxide film 18 is formed on the device isolation film 12 to a thickness of approximately several tens to several micrometers.

Subsequently, as shown in FIG. 4E, the removal process 19 is performed to remove the oxide film 18. In this case, as shown in FIG. 4C, the horn 16 formed during the R-gate etching process is also removed along with the oxide film 18. The removal process 19 may be performed by a front side etching process such as a cleaning process, a dry etching process, a wet etching process, or an etch back.

Subsequently, although not shown, a polysilicon film (not shown) and tungsten silicide doped so that the trench 15 is buried after depositing a gate oxide film (not shown) along a step of the top surface of the entire structure from which the oxide film 18 is removed. A layer (not shown) and a hard mask (not shown) are formed sequentially. At this time, the gate oxide film is preferably 30 to 50 kV, the polysilicon film is 400 to 700 kV, the tungsten silicide layer is 1000 to 1500 mW, and the hard mask is 2000 to 2500 mW.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a thermal oxidation process is performed after the R-gate etching process to form an oxide film at the same height as the horn generated during the R-gate etching process, and then the oxide film is removed. By removing together with the horn, the electrical characteristics of the device can be prevented from being lowered, and the reliability of the device can be improved to increase the yield.

Claims (6)

Forming an isolation layer to provide a substrate defined by an active region and a field region; Depositing a hard mask on the substrate; Etching the hard mask and the substrate of the active region to form a plurality of trenches; Forming an oxide film by performing a thermal oxidation process on the upper surface of the entire structure where the trench is formed; And Removing the oxide film Method of manufacturing a semiconductor device comprising a. The method of claim 1, And the oxide layer is formed at the same height as a horn formed on both sidewalls of the trench due to a difference in etching selectivity between the device isolation layer and the active region during the trench forming process. The method of claim 2, The horn is a semiconductor device manufacturing method that is removed together during the oxide film removal process. The method according to any one of claims 1 to 3, The oxide film removing process is a semiconductor device manufacturing method performing a cleaning process, dry etching process, wet etching process or etch back process. The method according to any one of claims 1 to 3, And forming a pad oxide film on the substrate before depositing the hard mask. The method according to any one of claims 1 to 3, The hard mask is a semiconductor device manufacturing method of forming a polysilicon film.

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