KR20060128374A - Electrostatic discharge protection circuit - Google Patents

Electrostatic discharge protection circuit Download PDF

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KR20060128374A
KR20060128374A KR1020050049776A KR20050049776A KR20060128374A KR 20060128374 A KR20060128374 A KR 20060128374A KR 1020050049776 A KR1020050049776 A KR 1020050049776A KR 20050049776 A KR20050049776 A KR 20050049776A KR 20060128374 A KR20060128374 A KR 20060128374A
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region
silicide
contacts
drain
protection device
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KR1020050049776A
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Korean (ko)
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최낙헌
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An electrostatic protection device is provided to prevent degradation of electrostatic discharge protection characteristics by employing a silicide region formed on a drain region. A gate electrode(210) is formed on a semiconductor substrate(200). Source and drain regions(220,230) are located on both sides of the gate electrode. Plural contact(250) are arranged in a line to be separated from the source and the drain region at a regular interval. A silicide region(240) is formed on a certain region including the contacts with a predetermined depth. A volume between the contacts is greater than that of a region adjacent to the respective contacts in the silicide region formed on the drain region. A width of the silicide region formed on the drain region is increased in proportion to a distance between the contacts located in the drain region and inversely proportional to a resistance ratio of a region where the silicide is not formed for the silicide region.

Description

정전기 보호 소자{Electrostatic discharge protection circuit}Electrostatic protection element {Electrostatic discharge protection circuit}

도 1은 종래의 ESD 보호 소자의 평면도.1 is a plan view of a conventional ESD protection device.

도 2는 본 발명의 일실시예에 따른 ESD 보호 소자의 평면도.2 is a plan view of an ESD protection device according to an embodiment of the present invention.

도 3은 본 발명에 일실시예에 따른 ESD 보호 소자의 부분 확대도.3 is a partially enlarged view of an ESD protection device according to an embodiment of the present invention.

도 4는 본 발명의 다른 실시예에 따른 ESD 보호 소자의 평면도.4 is a plan view of an ESD protection device according to another embodiment of the present invention.

본 발명은 반도체 장치 제조 분야에 관한 것으로, 특히 실리사이드 형성에 따른 정전기 방전 보호 특성의 저하를 방지할 수 있는 정전기 보호 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly, to an electrostatic protection device capable of preventing a decrease in electrostatic discharge protection characteristics due to silicide formation.

최근, 반도체 소자의 집적도가 날로 향상됨에 따라, MOS 트랜지스터의 게이트 선폭이 1㎛ 이하(sub-micron) 크기로 감소되었다. 이와 같이, MOS 트랜지스터의 게이트 폭이 더욱 작아지고 얇아짐에 따라, 접합 펀치쓰루(junction punchthrough) 발생, 누설 전류(leakage current), 및 콘택 저항 증가 등의 문제가 발생하여 반도체 소자의 동작 속도 저하 등을 유발한다. 이러한 문제점을 해결하기 위하여, 종래에는 자기정렬 실리사이드(self aligned silicide) 공정을 이용하 여 소자의 동작 속도를 향상시켰다.In recent years, as the degree of integration of semiconductor devices improves day by day, the gate line width of the MOS transistor has been reduced to a sub-micron size. As the gate width of the MOS transistor becomes smaller and thinner as described above, problems such as generation of junction punchthrough, leakage current, and increase in contact resistance occur, thereby lowering the operation speed of the semiconductor device. Cause. In order to solve this problem, the operation speed of the device is improved by using a self aligned silicide process.

한편, 반도체 소자는 MOS 트랜지스터의 크기 감소에 따라, 정전기(electro static discharge : ESD, 이하 ESD라고 함.)에 의해 손상되는 문제가 있다. 따라서, 반도체 소자는 ESD에 의한 소자의 손상을 방지하기 위하여, 내부회로와 입/출력 패드 사이에 정전기 보호 회로(ESD protection circuits)를 구비한다. 이러한 정전기 보호 회로는, ESD에 의해 방전된 전류가 IC 패키지의 핀으로 유입되면, 이를 정전기 보호 회로 쪽으로 유도하여 접지시킴으로써 내부 소자의 손상을 방지한다.On the other hand, semiconductor devices have a problem of being damaged by electrostatic discharge (ESD), as the size of the MOS transistor decreases. Accordingly, semiconductor devices have ESD protection circuits between internal circuitry and input / output pads to prevent damage to the device by ESD. Such an electrostatic protection circuit prevents damage to internal elements by inducing current to the pin of the IC package when the current discharged by the ESD flows into the pin of the IC package.

이와 같이, 고집적 반도체 소자는 동작속도 향상을 위한 실리사이드 형성 공정이 진행되어야 하고, 아울러, ESD에 의한 손상을 방지하기 위한 정전기 보호 회로가 형성되어야 한다. 그러나, ESD 보호 소자는 실리사이드 공정시 ESD 보호 특성이 저하되는 문제점이 있다.As such, in the highly integrated semiconductor device, a silicide forming process for improving an operation speed should be performed, and an electrostatic protection circuit for preventing damage caused by ESD should be formed. However, the ESD protection device has a problem in that the ESD protection property is degraded during the silicide process.

이를 상세히 살펴보면, ESD 보호 소자는 정전기 전송 경로의 전체 너비에 걸쳐 균일하게 정전기 전류를 흐르게 할수록, 발생되는 열이 분산되어, 보다 높은 전류에서도 견딜 수 있다. 그러나, 실리사이드 공정으로 형성된 부분은 실리사이드가 형성되지 않은 부분에 비해 상대적으로 저항이 작아서 저항의 불균일성이 크다. 이에 따라, 전류의 불균일성이 커져서 전체적인 ESD 특성이 크게 저하되는 문제점이 있다.In detail, the ESD protection device is able to withstand even higher currents by dissipating heat generated as the static current flows uniformly over the entire width of the electrostatic transmission path. However, the portion formed by the silicide process has a relatively small resistance compared to the portion where no silicide is formed, and thus the resistance nonuniformity is large. Accordingly, there is a problem in that the current nonuniformity is increased and the overall ESD characteristic is greatly reduced.

이와 관련하여, 도 1은 종래의 ESD 보호 소자의 평면도이다.In this regard, Figure 1 is a plan view of a conventional ESD protection device.

도시한 바와 같이, 종래의 ESD 보호 소자는, ESD 보호 회로 부분의 드레인 영역(100)에서 게이트(110)와 콘택(120)사이의 일정부분을 절연막 등과 같은 실리사이드 형성 방지막(silicide blocking layer)으로 덮어 실리사이드가 형성되지 않도록 하였다. 따라서, 실리사이드가 형성되지 않은 부분은 일정정도의 밸러스트 저항(ballast resistor)으로 역할하여, ESD 전류가 보다 균일하게 흐른다.As shown in the drawing, the conventional ESD protection device covers a predetermined portion between the gate 110 and the contact 120 in the drain region 100 of the ESD protection circuit portion with a silicide blocking layer such as an insulating film. Silicide was not formed. Therefore, the portion where no silicide is formed serves as a ballast resistor of some degree, so that the ESD current flows more uniformly.

그런데, 종래의 ESD 보호 소자는 드레인(100) 부분에 게이트(110)와 평행하게 실리사이드 패턴(130)이 형성되고, 드레인 콘택(120)이 일정 간격을 두고 형성되는 경우, 콘택(120)으로부터 게이트(110)까지의 밸러스트 저항이 위치마다 불균일성을 갖는다. 예를 들면, 콘택(120)에서 게이트(110)의 A지점까지 흐르는 전류는 콘택(120)에서 게이트(110)의 B지점까지 흐르는 전류보다 더 많은 실리사이드 영역(130)을 통과한다. 이에 따라, 콘택(120)에서 게이트(110)의 A지점까지의 밸러스트 저항은, 콘택(120)에서 게이트(110)의 B지점까지의 밸러스트 저항보다 더 크게 된다.However, in the conventional ESD protection device, when the silicide pattern 130 is formed in the drain 100 in parallel with the gate 110, and the drain contact 120 is formed at a predetermined interval, the gate from the contact 120 is formed. Ballast resistance up to 110 has non-uniformity from location to location. For example, current flowing from contact 120 to point A of gate 110 passes through more silicide region 130 than current flowing from contact 120 to point B of gate 110. Accordingly, the ballast resistance from contact 120 to point A of gate 110 is greater than the ballast resistance from contact 120 to point B of gate 110.

따라서, 콘택(120)으로부터 게이트(110)까지의 밸러스트 저항이 위치마다 불균일하고, 이러한 저항 불균일성은 ESD 전류밀도의 불균일성을 초래하여 ESD 보호소자의 성능에 저해요인이 된다.Therefore, the ballast resistance from the contact 120 to the gate 110 is nonuniform at each position, and this resistance nonuniformity causes nonuniformity of the ESD current density, which is a detrimental factor to the performance of the ESD protection device.

따라서, 본 발명은 상기한 바와 같은 선행기술에 내재된 문제점을 해결하기 위해 창작된 것으로, 본 발명의 목적은 ESD 보호 회로를 구성하는 트랜지스터의 드레인 콘택으로부터 게이트까지의 밸러스트 저항을 더 균일하게 하는 ESD 보호 소자를 제공함에 있다.Accordingly, the present invention has been created to solve the problems inherent in the prior art as described above, and an object of the present invention is to provide an ESD uniformer ballast resistance from the drain contact to the gate of the transistor constituting the ESD protection circuit. In providing a protection device.

상기한 바와 같은 목적을 달성하기 위해 본 발명의 일면에 따라, 반도체 기판 상에 형성된 게이트 전극과 상기 게이트 전극의 양측에 위치한 소오스 및 드레인 영역을 포함하는 정전기 보호 소자가 제공되며: 이 회로는, 상기 소오스 및 드레인 영역에 일정 간격을 유지하며, 일렬로 배열되어 형성되는 다수의 콘택; 및 상기 다수의 콘택을 포함하는 일정 영역상에 소정의 깊이를 갖도록 형성되는 실리사이드 영역;을 포함하며, 상기 드레인 영역에 형성되는 실리사이드 영역은 상기 각각의 컨택에 인접한 영역보다 각 컨택 사이의 영역의 단면적이 커지도록 형성되는 것을 특징으로 한다.According to an aspect of the present invention for achieving the above object, there is provided an electrostatic protection device comprising a gate electrode formed on a semiconductor substrate and source and drain regions located on both sides of the gate electrode: A plurality of contacts arranged in a row at regular intervals in the source and drain regions; And a silicide region formed to have a predetermined depth on a predetermined region including the plurality of contacts, wherein the silicide region formed in the drain region has a cross-sectional area of an area between each contact than a region adjacent to each of the contacts. It is characterized in that it is formed to be large.

상기 구성에서, 상기 드레인 영역에 형성되는 실리사이드 영역의 너비는, 상기 드레인 영역에 위치한 콘택 사이의 거리에 비례하고, 실리사이드 영역에 대한 실리사이드가 형성되지 않은 영역의 저항비에 반비례하는 것을 특징으로 한다.In the above configuration, the width of the silicide region formed in the drain region is proportional to the distance between the contacts located in the drain region, and is inversely proportional to the resistance ratio of the region in which the silicide is not formed with respect to the silicide region.

(실시예)(Example)

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상술하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 일실시예에 따른 ESD 보호 소자의 평면도이다.2 is a plan view of an ESD protection device according to an embodiment of the present invention.

도시한 바와 같이, 본 발명의 일실시예에 따른 ESD 보호 소자는 반도체 기판(200); 반도체 기판(200) 상에 형성된 게이트 전극(210); 반도체 기판(200) 내에 위치하며, 게이트 전극(210) 양단에 위치한 소오스 및 드레인 영역(220,230); 및 드레인 영역(230) 내에서 요철 구조로 형성된 실리사이드 영역(240); 을 포함한다.As shown, an ESD protection device according to an embodiment of the present invention includes a semiconductor substrate 200; A gate electrode 210 formed on the semiconductor substrate 200; Source and drain regions 220 and 230 positioned in the semiconductor substrate 200 and positioned across the gate electrode 210; And a silicide region 240 having a concave-convex structure in the drain region 230. It includes.

여기서, 요철 구조는 콘택(250)과 게이트(210) 사이의 간격에 따라 다르게 형성될 수 있다. 즉, 콘택(250)과 게이트(210) 사이의 간격이 클수록, 실리사이드 영역(240)을 게이트(210)에 가깝게 확장되고, 콘택(250)과 게이트(210) 사이의 간격이 작을수록, 실리사이드 영역(240)을 게이트(210)에 멀게 축소된다.Here, the uneven structure may be formed differently according to the distance between the contact 250 and the gate 210. That is, the larger the distance between the contact 250 and the gate 210, the closer the silicide region 240 is to the gate 210, and the smaller the distance between the contact 250 and the gate 210, the silicide region. 240 is shrunk away from the gate 210.

이와 같은 구조에 있어서, 콘택(250)에서 게이트(210)의 'A'지점까지 흐르는 전류경로는, 콘택(250)에서 게이트(210)의 'B'지점까지 흐르는 전류경로보다 긴 반면, 실리사이더가 형성되지 않는 영역을 통과하는 길이가 짧다.In this structure, the current path flowing from the contact 250 to the 'A' point of the gate 210 is longer than the current path flowing from the contact 250 to the 'B' point of the gate 210, while the silicide The length passing through the area where is not formed is short.

따라서, 본 발명에 따른 ESD 보호 소자는, 요철 구조로 형성된 실리사이드 영역(240)에 의해 콘택(260)에서 게이트(210)까지 흐르는 전류의 경로 상에 밸러스트 저항이 같도록 실리사이드 영역(240)을 조절함으로써, 콘택(250)과 게이트(210) 사이의 전체 밸러스트 저항을 같게 한다.Accordingly, the ESD protection device according to the present invention adjusts the silicide region 240 so that the ballast resistance is the same on the path of the current flowing from the contact 260 to the gate 210 by the silicide region 240 formed of the uneven structure. As a result, the total ballast resistance between the contact 250 and the gate 210 is equalized.

도 3은 본 발명에 일실시예에 따른 ESD 보호 소자의 부분 확대도로서, 도 2의 '가' 영역을 확대한 도면이다. 여기서, 도면상의 부호 'h'는 콘택(310)과 콘택(320) 사이의 간격을 나타내고, 'd'는 요철의 깊이를 나타낸다.FIG. 3 is an enlarged view of a portion of an ESD protection device according to an embodiment of the present invention, and is an enlarged view of an area of FIG. Here, reference numeral 'h' in the drawing represents a gap between the contact 310 and the contact 320, and 'd' represents a depth of the unevenness.

도시한 바와 같이, 본 발명에 따른 ESD 보호 소자는, 콘택(320)과 게이트(350)의 'A'지점 사이의 밸러스트 저항과, 콘택(320)과 게이트(350)의 'B'지점 사이의 밸러스트 저항을 균일하게 하도록 한다. 이를 위해, 'd' 길이의 실리사이드가 형성되지 않은 영역(340)의 밸러스트 저항이 'h/2+d' 길이의 실리사이드 영역(330)의 밸러스트 저항과 같도록 요철 구조의 실리사이드 영역(330)을 형성한다.As shown, an ESD protection device in accordance with the present invention includes a ballast resistor between contact 320 and point 'A' of gate 350 and between contact 320 and point 'B' of gate 350. Make ballast resistance even. To this end, the silicide region 330 of the uneven structure is formed such that the ballast resistance of the region 340 in which the 'd' length silicide is not formed is equal to the ballast resistance of the silicide region 330 having the 'h / 2 + d' length. Form.

'c'를 실리사이드 영역(330)과 실리사이드가 형성되지 않은 영역(340)의 면 저항의 비라 하고, 위 내용을 수식으로 표현하면,'c' is the ratio of the surface resistance of the silicide region 330 and the silicide-free region 340, and the above expression is expressed by a formula,

c * d = h / 2 + dc * d = h / 2 + d

이므로, 요철의 깊이 'd'는 다음과 같다.Therefore, the depth 'd' of the unevenness is as follows.

d = (h / 2) / (c - 1)d = (h / 2) / (c-1)

여기서, 밸러스트 저항의 비율 'c'를 20, 콘택 간격 'h'를 0.5㎛라 하면, 요철의 깊이 'd'는 0.013㎛가 된다.Here, if the ratio 'c' of the ballast resistance is 20 and the contact interval 'h' is 0.5 µm, the depth 'd' of the unevenness is 0.013 µm.

도 4는 본 발명의 다른 실시예에 따른 ESD 보호 소자의 평면도이다.4 is a plan view of an ESD protection device according to another embodiment of the present invention.

도시한 바와 같이, 본 발명의 다른 실시예에 따른 ESD 보호 소자는 드레인(400)에 두 줄의 콘택 배열(410)을 가지며, 드레인(400)과 소오스(420)가 연속적으로 배열되어 있는 경우, 본 발명의 일실시예에 따른 ESD 보호 소자와 동일하게 요철 구조로 실리사이드를 형성한다.As shown, the ESD protection device according to another embodiment of the present invention has a contact array 410 of two lines in the drain 400, when the drain 400 and the source 420 are continuously arranged, As in the ESD protection device according to the exemplary embodiment of the present invention, silicide is formed in an uneven structure.

이상에서 살펴본 바와 같이, 본 발명에 따른 정전기 방전 보호 소자는 드레인 영역 상에 형성되는 실리사이드 영역을 요철 구조로 형성함으로써, 드레인에 형성된 콘택에서 게이트까지 흐르는 전류의 경로상에 같은 밸러스트 저항을 가지도록 조절된다. 그에 따라, 정전기 방전 보호 소자는 드레인에 형성된 콘택과 게이트 사이의 전체 밸러스트 저항이 같게 되고, 이로 인해 저항값의 차이에서 오는 소자의 특정 저하를 방지할 수 있다.As described above, the electrostatic discharge protection device according to the present invention forms a silicide region formed on the drain region in a concave-convex structure, thereby adjusting to have the same ballast resistance on the path of the current flowing from the contact formed in the drain to the gate. do. Accordingly, the electrostatic discharge protection device has the same total ballast resistance between the contact formed on the drain and the gate, thereby preventing the specific degradation of the device resulting from the difference in resistance value.

본 발명의 상기한 바와 같은 구성에 따라, 본 발명에 따른 ESD 보호 소자는 반도체 제조 공정시 실리사이드 형성을 적용하는 제품에서 추가적인 비용없이 ESD 보호 소자의 성능을 향상시키는 효과가 있다.According to the configuration as described above of the present invention, the ESD protection device according to the present invention has the effect of improving the performance of the ESD protection device at no additional cost in the product that applies the silicide formation in the semiconductor manufacturing process.

본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구범위에 의해 마련되는 본 발명의 정신이나 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업자는 용이하게 알 수 있다.While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (2)

반도체 기판 상에 형성된 게이트 전극과 상기 게이트 전극의 양측에 위치한 소오스 및 드레인 영역을 포함하는 정전기 방전 보호 소자에 있어서,In the electrostatic discharge protection device comprising a gate electrode formed on a semiconductor substrate and source and drain regions located on both sides of the gate electrode, 상기 소오스 및 드레인 영역에 일정 간격을 유지하며, 일렬로 배열되어 형성되는 다수의 콘택; 및A plurality of contacts arranged in a row at regular intervals in the source and drain regions; And 상기 다수의 콘택을 포함하는 일정 영역상에 소정의 깊이를 갖도록 형성되는 실리사이드 영역;을 포함하며,And a silicide region formed to have a predetermined depth on a predetermined region including the plurality of contacts. 상기 드레인 영역에 형성되는 실리사이드 영역은 상기 각각의 컨택에 인접한 영역보다 각 컨택 사이의 영역의 단면적이 커지도록 형성되는 것을 특징으로 하는 정전기 방전 보호 소자.And the silicide region formed in the drain region is formed to have a larger cross-sectional area of the region between the contacts than the region adjacent to each of the contacts. 제 1 항에 있어서,The method of claim 1, 상기 드레인 영역에 형성되는 실리사이드 영역의 너비는, 상기 드레인 영역에 위치한 콘택 사이의 거리에 비례하고, 실리사이드 영역에 대한 실리사이드가 형성되지 않은 영역의 저항비에 반비례하는 것을 특징으로 하는 정전기 방전 보호 소자.The width of the silicide region formed in the drain region is in proportion to the distance between the contacts located in the drain region, and inversely proportional to the resistance ratio of the region in which the silicide is not formed with respect to the silicide region.
KR1020050049776A 2005-06-10 2005-06-10 Electrostatic discharge protection circuit KR20060128374A (en)

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