KR20060118898A - Semiconductor memory devices and methods of fabricating the same - Google Patents

Abstract

A semiconductor memory device and a manufacturing method thereof are provided to improve short channel effect of a sensing transistor by arranging a control gate line for controlling the sensing transistor. A body layer pattern(22) is located on a substrate(20). A source region(24) and a drain region(26) are located in the body layer pattern to be separated from each other. A data line(30) crosses an upper portion of a channel region(28) between the source region and the drain region. An MTJ(Multiple Tunnel Junction) barrier layer(32) is arranged between the gate line and the channel line. A floated storage node(34) is located between the channel region and the MTJ barrier layer. A first control gate line(38) crosses an upper portion of the data line and covers both sidewalls of the storage node and both sidewalls of the MTJ barrier layer. A second control gate line(42) is located on a lower portion of the channel region and crosses a lower portion of the body layer pattern.

Description

Semiconductor memory devices and methods of fabricating the same

1A is a cross-sectional view of two conventional collapsible transistor memory (STTM) cells.

1B is a schematic circuit diagram of a conventional STTM cell.

2 is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present invention.

3 is a schematic circuit diagram illustrating a semiconductor memory device and a method of manufacturing the same according to an embodiment of the present invention.

4A to 4F are perspective views illustrating a semiconductor memory device and a method of manufacturing the same according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor storage devices and methods of manufacturing the same, and more particularly, to semiconductor storage devices having two transistor memory cells that can be shrunk and manufacturing methods thereof.

DRAM devices have the advantage of being highly integrated compared to other memory devices such as SRAM devices, but soft errors caused by leakage currents from memory cells, internal noise and alpha particles incident from the outside. Due to this, it is difficult to maintain the stored charges, which are reduced as the device shrinks. Accordingly, the memory cells of such elements require a constant refresh operation to maintain the data stored in the memory cells. Therefore, power consumption increases even in the standby state.

Alternatively, flash memory devices or EEPROM devices have the advantage of not having to refresh the memory cells in order to maintain the data stored in the memory cells. However, the primary drawback of flash memory devices is that it takes a relatively long time to program a memory cell, making it difficult to improve its relative slow access time. In addition, a high voltage is required to program (write) or erase the memory cells of the flash memory device. The high electric field applied during the erase and program operations lowers the film quality of the tunneling barrier layer made of the oxide film. This phenomenon worsens as the number of erase and program operations increases. In general, when the erase and program times reach about 10 ⁵ times, the function of the tunneling barrier layer made of an oxide film is lost. As a result, the memory element has a limited lifetime.

Therefore, there is a need for a new memory cell having both the advantages of DRAM and flash memory devices. In other words, there is a need for a semiconductor memory device having a memory cell that can be reduced in terms of long-term data retention (non-volatile), low operating voltage, high speed operation, high reliability, and integration. A new memory cell called a scalable two transistor memory cell (STTM cell) has been proposed by Nakazato et al. (See US Pat. No. 5,952,692). Nakazato et al. Refer to the new device as a planar localized electron device memory (PLEDM) cell. This memory cell has an electrically isolated memory node (i.e., a floating memory node), which is excellent in resistance to soft errors and high in signal-to-noise ratio (S / N ratio). . In addition, this memory cell is a quantum tunneling element that operates at room temperature without deterioration by hot carriers, and can be fabricated using existing silicon processing techniques. 1A is a cross-sectional view of two conventional collapsible transistor memory (STTM) cells, and FIG. 1B is a schematic circuit diagram of a conventional STTM cell.

As shown in Figs. 1A and 1B, the STTM cell includes a sensing (lower) transistor 1 known as a read or access transistor and a program (top) transistor 2 known as a write transistor. The program transistor 2 has a MOS having two vertical sidewall gates with a multiple tunnel junction (MTJ) barrier layer 4 (hereinafter referred to as an MTJ barrier layer) between the source and the drain. Transistor. The sensing transistor 1 includes a drain region 7 and a source region 8 formed on a predetermined region of the semiconductor substrate 18. The sensing transistor 1 is basically a floating gate 6 having a function of a storage node of a memory cell, a drain 7 serving as a sensing line corresponding to a bit line, and a ground potential or a specific potential. Is a conventional MOS transistor including a source 8 to which is applied.

As shown in the same drawings, a channel region is formed between the drain region 7 and the source region 8 of the sensing transistor 1, and the first gate insulating layer 3 is positioned on the channel region.

Further, as shown in the same figures, in the STTM cell, the program transistor 2 is stacked on the gate of the sensing transistor. The storage node serving as the floating gate 6 of the sensing transistor has a function as a drain of the program transistor. The control gate line 11 formed on the sidewalls of the MTJ barrier layer 4 and the floating gate 6 serves as a write line or a word line. The source region of the program transistor serves as the data line 12. A second gate insulating film 5 is interposed between the control gate line 11 and the floating gate 6. The MTJ barrier layer is formed by alternately stacking the insulating film 13 and the semiconductor layer 14.

In the conventional STTM cell configured as described above, the threshold voltage of the sensing transistor 1 is changed by the charges stored in the floating gate 6. That is, the sensing transistor 1 is not provided with a separate control gate line, but is controlled by the control gate line 11 and the data line 12 of the program transistor 2. In addition, the sensing transistor of the conventional STTM cell employs a conventional planar type transistor. Thus, in the case of having an ultra-short channel length, the sensing transistor may have a short channel effect to degrade the operation characteristics of the STTM cell.

An object of the present invention is to provide a semiconductor memory device having two transistor memory cells that can be reduced.

Another object of the present invention is to provide methods for manufacturing semiconductor memory devices suitable for suppressing short channel effects.

According to one aspect of the present invention, there are provided semiconductor memory devices having two transistor memory cells (STTM cells) that can be shrunk. The unit cell of the semiconductor memory devices may include a semiconductor substrate and a body layer pattern positioned on the substrate. Source and drain regions disposed in the body layer pattern and spaced apart from each other. A data line across the channel region is disposed between the source / drain regions. An MTJ barrier layer is disposed between the data line and the channel region. A floating storage node is located between the MTJ barrier layer and the channel region. A first control gate line is disposed across the top of the data line and covering both sidewalls of the storage node and covering both sidewalls of the MTJ barrier layer. A second control gate line is disposed below the channel region and crosses a lower portion of the body layer pattern.

In some embodiments of the inventive concept, a first gate insulating layer positioned between sidewalls of the storage node and the first control gate line, and positioned between the channel region and the second control gate line. It may include a second gate insulating film.

In other embodiments, the MTJ barrier layer may be formed by alternately stacking semiconductor layers and insulating layers. The semiconductor layer may be any one selected from the group consisting of a silicon layer, a germanium layer, a silicon germanium layer, and a silicon germanium carbide layer. In addition, the insulating layer may be formed of any one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a metal oxide layer, a metal nitride layer, and a metal silicate layer.

In still other embodiments, the first control gate line, in addition to the suspended storage node, the MTJ barrier layer and the data line, can be operated as a vertical program transistor.

In still other embodiments, the second control gate line, together with the floating storage node disposed on the source / drain regions located in the body layer pattern and the channel region therebetween, may be a single sensing transistor. Can work.

According to another aspect of the present invention, methods of manufacturing semiconductor memory devices suitable for suppressing short channel effects are provided. The semiconductor memory device includes two transistor memory cells (STTM cells) that can be shrunk. The unit cell of the two transistor memory cells includes a lower transistor (or sensing transistor) and an upper transistor (or program transistor) stacked on the lower transistor. The STTM cell has control lines including bit lines, data lines and control gate lines (word lines). The control gate line includes a first control gate line controlling the program transistor and a second control gate line controlling the sensing transistor. The program transistor includes a MOS transistor having a plurality of tunnel junction (MTJ) barrier layers (hereinafter referred to as MTJ barrier layers) between the source and the drain and having two vertical sidewall gates. The sensing transistor includes a drain region and a source region formed on a predetermined region of a semiconductor substrate. The sensing transistor is basically a MOS transistor including a floating gate having a function of a storage node of a memory cell, a drain serving as a sensing line corresponding to a bit line, a ground potential, or a source to which a specific potential is applied. . The manufacturing method includes forming a trench on the semiconductor substrate and the trench region defining the formation position of the control gate line on the semiconductor substrate. A first conductive film is filled in the trench region. A single crystal semiconductor layer is formed on the substrate having the trench region. The single crystal semiconductor layer is patterned to form a body layer pattern crossing the trench region. The first conductive film is removed. The second conductive film is filled in the trench region from which the first conductive film is removed. An insulating layer for device isolation is formed on the substrate having the body layer pattern.

In some example embodiments of the inventive concepts, an insulating film may be formed on an inner surface portion of the trench region and a bottom surface of the body layer pattern before the second conductive layer is formed in the trench region. .

In example embodiments, the first control gate line may include a control line for controlling the program transistor and the sensing transistor.

In still other embodiments, the first conductive layer may include a silicon germanium (SiGe) layer, and the second conductive layer may include a polysilicon layer.

In example embodiments, forming a trench region in the semiconductor substrate may include forming a trench mask on the semiconductor substrate, and etching the substrate using the trench mask as an etching mask.

In example embodiments, the forming of the body layer pattern may include forming an active mask on the semiconductor layer, and etching the single crystal semiconductor layer using the active mask as an etching mask to expose an upper surface of the substrate. It may include.

In yet other embodiments, the single crystal semiconductor layer may include forming using a silicon epitaxial process.

In still other embodiments, the forming of the second conductive layer in the trench region may include forming by using LPCVD.

In still other embodiments, the insulating film formed on the inner surface portion of the trench region and the bottom surface portion of the body layer pattern may be formed of an oxide film, and may be formed using LPCVD or a thermal oxide film.

In still other embodiments, removing the first conductive layer may include using a wet etching process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments introduced below are provided to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention may be embodied in other forms without being limited to the embodiments described below. In the drawings, lengths, thicknesses, and the like of layers and regions may be exaggerated for convenience of description. In addition, where a line or layer is said to be on another line, or on another layer, it may be formed directly on the other line or another layer, or a third layer may be interposed therebetween.

2 is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present invention. 3 is a schematic circuit diagram illustrating a semiconductor memory device and a method of manufacturing the same according to an embodiment of the present invention. 4A to 4F are perspective views illustrating a semiconductor memory device and a method of manufacturing the same according to an embodiment of the present invention.

2 and 3, the semiconductor memory device according to the present invention includes two transistor memory cells (STTM cells) that can be shrunk. In the unit cell of the semiconductor memory device, a body layer pattern 22 is disposed on the semiconductor substrate 20 and the substrate 20. A source region 24 and a drain region 26 are disposed on the body layer pattern 22 and spaced apart from each other. The channel region 28 is positioned between the source region 24 and the drain region 26. A data line 30 is disposed across the channel region 28. A multiple tunnel junction (MTJ) barrier layer 32 is positioned between the data line 30 and the channel region 28.

The MTJ barrier layer 32 may be a laminated film including a semiconductor layer and an insulating layer that are alternately stacked. The material used as the semiconductor layer constituting the MTJ barrier layer 32 is any one selected from undoped silicon, doped silicon, germanium, silicon germanium and silicon germanium carbide. It can be one. The material used as the insulating film constituting the MTJ barrier layer may be any one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, metal oxide and metal nitride.

A floating gate (or floating storage node) 34 is disposed between the MTJ barrier layer 32 and the channel region 28. The floating gate 34 serves as a storage node. The floating gate 34 may be a semiconductor layer. The semiconductor layer constituting the floating gate 34 may be a polysilicon film. The semiconductor layer constituting the floating gate 34 and the semiconductor layer constituting the MTJ barrier layer 32 may have different conductivity types. For example, when the semiconductor layer constituting the floating gate 34 is P type, the semiconductor layer constituting the MTJ barrier layer 32 may be N type.

The first gate insulating layer 36 may be positioned between the floating gate 34 and the channel region 28. The first gate insulating layer 36 may be a silicon oxide layer.

A first control gate line 38 is disposed across the top of the data line 30. The first control gate line 38 may be a conductive film such as a polysilicon film. The first control gate line 38 is disposed to cover sidewalls of the MTJ barrier layer 32 and sidewalls of the floating gate 34. The second gate insulating layer 40 is positioned between the sidewalls of the floating gate 34 and the first control gate line 38. That is, the floating gate 34 may be surrounded by the second gate insulating layer 40. As a result, the floating gate 34 is floated. The second gate insulating layer 40 may be a silicon oxide layer.

A second control gate line 42 is disposed below the active region (not shown) of the body layer pattern 22. That is, the second control gate line 42 is disposed under the channel region 28. The second control gate line 42 may be disposed in parallel with the first control gate line 38. The second control gate line 42 may be a conductive film such as a polysilicon film. A third gate insulating layer 44 may be positioned between the channel region 28 and the second control gate line 42. The third gate insulating layer 44 may be located only below the active region (not shown) of the body layer pattern 22. When the third gate insulating layer 44 is positioned below the active region of the body layer pattern 22, the second control gate line 42 may not be provided. The third gate insulating layer 44 may be disposed adjacent to the lower portion of the source region 24 and the drain region 26. As a result, referring to FIG. 2, the channel region 28 may have a thin width between the upper and lower portions thereof. That is, the channel region 28 may be a thinning channel region. The third gate insulating layer 44 may be a silicon oxide layer. The first and second control gate lines 38 and 44 may be arranged to be electrically connected. In this case, the same voltage may be applied to the first and second control gate lines 38 and 44.

An insulating layer 46 may be disposed between the lower surface of the third control gate line 42 and the upper surface of the substrate 20. As a result, the third control gate line 42 and the substrate 20 may be electrically isolated from each other.

Hereinafter, a method of driving the semiconductor memory device of the present invention configured as described above will be described. The semiconductor memory device includes two transistor memory cells (STTM cells) that can be shrunk. In the unit cell of the two transistor memory cells, a lower transistor (or sensing transistor) 50 and an upper transistor (or program transistor) 60 stacked on the lower transistor are disposed. The STTM cell has control lines including bit lines, data lines and control gate lines (word lines). The control gate line includes a first control gate line 38 for controlling the program transistor and a second control gate line 42 for controlling the sensing transistor. The program transistor 60 may be a MOS transistor having an MTJ barrier layer 32 between the source region (data line) 30 and the drain region (floating gate) 34 and having a first control gate line 38. The sensing transistor includes a source region 24 and a drain region 26 formed on the body layer pattern 22 to be spaced apart from each other. The sensing transistor 50 basically includes a floating gate 34 having a function of a storage node of a memory cell, a drain region 26 serving as a sensing line corresponding to a bit line, a ground potential, or a source to which a specific potential is applied. The MOS transistor includes a region 24 and a second control gate line 42 crossing the lower portion of the body layer pattern 22.

In the write mode, a data voltage is applied to the data line 30, and a write voltage, that is, a program voltage, is applied to the first control gate (or write) line 38. Accordingly, the height of the barrier between the data line 30 and the floating gate 34 is reduced, so that the tunneling current flows through the insulating layers forming the MTJ barrier layer 32. As a result, charges (electrons or holes) are stored in the floating gate 34. These stored charges change the threshold voltage of the sensing transistor 50. For example, when electrons are stored in the floating gate 34 and the sensing transistor 50 is an NMOS transistor, the threshold voltage of the sensing transistor 50 is increased in a positive voltage direction. The write operation of the STTM cell can be achieved using a lower write voltage than the flash memory device. This is because charge injection into the floating gate 34 is controlled by the first control gate line 38 together with the data line 30. In addition, the threshold voltage of the sensing transistor 50 may be changed by a voltage applied to the second control gate line 42. In this case, the threshold voltage of the sensing transistor 50 may be controlled by the first and second control gate lines 38 and 42. Therefore, the characteristic of the threshold voltage of the sensing transistor 50 can be improved.

To read the data stored in the STTM cell, a read voltage is applied to the first control gate line 38 and an appropriate voltage is applied to the source region 24. Next, a sensing amplifier (not shown) determines the current flowing through the drain region 26. In this case, when the threshold voltage of the sensing transistor 50 is higher than the read voltage, no current flows in the source region 24. However, when the threshold voltage of the sensing transistor 50 is lower than the read voltage, current flows through the source region 24. In this case, a data read operation may be performed by applying a read voltage to the second control gate line 42 without applying a read voltage to the first control gate line 38. In addition, a data read operation may be performed by applying a read voltage to the first and second control gate lines 38 and 42.

Hereinafter, the method for manufacturing the semiconductor memory device of the present invention described above will be described. The semiconductor memory device has an STTM cell. The STTM cell includes a sensing transistor and a program transistor disposed on the sensing transistor. The manufacturing method of the program transistor is the same as or similar to a conventional manufacturing method. Therefore, a description of the manufacturing method of the program transistor will be omitted. In addition, the manufacturing method of the source region and the drain region which are located in the active region of the semiconductor substrate and provided in the sensing transistor is also the same as or similar to the conventional manufacturing method, and thus will be omitted. That is, the following description will focus on a method of manufacturing a control gate line for controlling the sensing transistor.

Referring to FIG. 4A, a first photoresist film is formed on the semiconductor substrate 20 and the substrate 20. The first photoresist layer is patterned to form a trench mask 70 that exposes a predetermined region of the upper surface portion of the substrate 20. The substrate 20 is etched using the trench mask 70 as an etch mask to form a trench region 72. The trench region 72 may be formed to cross a lower portion of an active region (not shown) of the semiconductor substrate 20. The first conductive layer 74 is filled in the trench region 72. The first conductive layer 74 may be formed of a silicon germanium (SiGe) layer.

Referring to FIG. 4B, the trench mask 70 is removed to expose the top surface of the semiconductor substrate 20. A single crystal semiconductor layer is formed on the substrate having the trench region 72. The single crystal semiconductor layer may be formed using an epitaxial technique. That is, the single crystal semiconductor layer can be formed using the exposed semiconductor substrate 20 as a seed layer. The single crystal semiconductor layer is planarized to form a single crystal body layer 76 having a uniform thickness. The single crystal body layer 76 may be formed of a single crystal silicon film. A second photoresist film is formed on the single crystal body layer 76. The second photoresist layer may be patterned to form an active mask 78 that exposes a predetermined region of the upper surface portion of the single crystal body layer 76. The active mask 78 is formed to define the formation position of subsequent control gate lines. In addition, the active mask 78 is formed to cross the upper portion of the trench region 72.

Referring to FIG. 4C, the single crystal body layer 76 is etched using the active mask 78 as an etch mask to expose an upper surface of the substrate 20 and an upper surface of the first conductive layer 74. Let's do it. As a result, the upper surface portion of the substrate 20 and the upper surface of the first conductive layer 74 are exposed through both side portions of the active mask 78.

Referring to FIG. 4D, the active mask 78 is removed. As a result, a body layer pattern 80 is formed to cross the upper portion of the trench region 72. The first conductive layer 74 formed in the trench region 72 is etched to expose the inner and bottom portions of the trench region 72 and the lower portion of the body layer pattern 80. In this case, the first conductive layer 74 may be etched by using a wet etching process. An insulating layer 82 is formed on the front surface of the substrate having the trench region 72 and the body layer pattern 80. In this case, the insulating layer 82 may be formed on the inner side portion and the bottom portion of the trench region 72 and the bottom portion of the body layer pattern 80. The insulating film 82 may be formed of an oxide film. The oxide film may be formed of a thermal oxide film. Alternatively, the oxide film may be formed using a CPCVD process.

Referring to FIG. 4E, a second conductive layer is filled in the trench region 72. The second conductive film may be formed of a polysilicon film. The second conductive film may be formed using an LPCVD process. The second conductive layer may be planarized to form an upper surface of the second conductive layer and an upper surface of the substrate 20 at substantially the same level. As a result, a control gate line 84 crossing the lower portion of the body layer pattern 80 is formed on the substrate. That is, the control gate line 84 is formed in the trench region 72 under the body layer pattern 80. In this case, the insulating layer 82 positioned between the lower surface of the body layer pattern 80 and the upper surface of the control gate line 84 may serve as a gate insulating layer of the control gate line 84. .

Referring to FIG. 4F, an insulating layer 86 for device isolation is formed on a substrate having the body layer pattern 80 and the control gate line 84.

Source / drain regions (not shown) of the sensing transistor may be formed in the body layer pattern 80. The floating gate, the MTJ barrier layer, and the data line may be sequentially formed on the body layer pattern having the source / drain regions. In addition, a control gate may be formed to cover sidewalls of the floating gate and the MTJ barrier layer.

As described above, according to the exemplary embodiments of the present invention, the short channel effect of the sensing transistor may be improved by disposing a control gate line controlling the sensing transistor of the STTM cell.

Claims (10)

In a semiconductor memory device having two transistor memory cells that can be shrunk, the unit cell of the two transistor cells that can be shrunk A semiconductor substrate and a body layer pattern located on the substrate; Source and drain regions disposed on the body layer pattern and spaced apart from each other; A data line crossing an upper portion of a channel region between the source region and the drain region; An MTJ barrier layer disposed between the data line and the channel region; A suspended storage node located between the MTJ barrier layer and the channel region; A first control gate line crossing the top of the data line, the first control gate line covering both sidewalls of the storage node and both sidewalls of the MTJ barrier layer; And And a second control gate line positioned below the channel region and disposed across the bottom of the body layer pattern. The method of claim 1, And a first gate insulating layer positioned between sidewalls of the storage node and the first control gate line, and a second gate insulating layer positioned between the channel region and the second control gate line. device. The method of claim 1, The MTJ barrier layer may be a stacked layer in which semiconductor layers and insulating layers are alternately stacked, and the semiconductor layer is any one selected from a group consisting of a silicon layer, a germanium layer, a silicon germanium layer, and a silicon germanium carbide layer. A semiconductor memory device comprising one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a metal oxide layer, a metal nitride layer, and a metal silicate layer. The method of claim 1, The first control gate line, in addition to the suspended storage node, the MTJ barrier layer and the data line, is operated with a vertical program transistor, And the second control gate line, in addition to the floating storage node disposed on the source / drain regions located within the body layer pattern and the channel region therebetween, actuated by one sensing transistor. Semiconductor memory device. A manufacturing method of a semiconductor memory device, comprising: a transistor transistor having two shrinkable transistor cells; wherein a unit cell of the two transistor memory cells includes a sensing transistor and a program transistor disposed on the sensing transistor. Way Forming a trench region in the semiconductor substrate and the semiconductor substrate, the trench region defining a formation position of a control gate line, Filling a first conductive layer in the trench region, Forming a single crystal semiconductor layer on the substrate having the trench region, Patterning the single crystal semiconductor layer to form a body layer pattern crossing the trench region, Removing the first conductive film, Filling the second conductive layer in the trench region from which the first conductive layer is removed; Forming a pair of impurity regions spaced apart from each other in the body layer pattern, and And forming a floating storage node on the body layer pattern having the pair of impurity regions. The method of claim 5, And forming an insulating film in an inner surface portion of the trench region and a bottom surface of the body layer pattern before forming the second conductive layer in the trench region. The method of claim 5, And the first conductive film is formed of a silicon germanium (SiGe) film, and the second conductive film is formed of a polysilicon film. The method of claim 5, Forming a trench region in the semiconductor substrate Forming a trench mask on the semiconductor substrate, And etching the substrate by using the trench mask as an etch mask. The method of claim 5, Forming the body layer pattern An active mask is formed on the semiconductor layer, And etching the single crystal semiconductor layer by using the active mask as an etch mask to expose an upper surface of the substrate. The method of claim 5, And said single crystal semiconductor layer is formed using a silicon epitaxial process.

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