KR20060117104A - Receiver chip for diversity satellite digital multimedia broadcasting - Google Patents

Abstract

A diversity satellite DMB(Digital Multimedia Broadcasting) receiving chip is provided to package a first receiving block and a second receiving block into a single chip and minimize interference between the first and second receiving blocks in the chip. A diversity satellite DMB receiving chip(100) includes a first receiving block(101) and a second receiving block(102) isolated from the first receiving block. The first and second receiving blocks are packaged in a single receiving chip. Input/output terminals of the first receiving block are connected to external pins located on one side(120) of the receiving chip, and input/output terminals of the second receiving block are connected to external pin placed on the other side(130) of the receiving chip. A source terminal or a control terminal of the first or second receiving block is connected to an external pin of the receiving chip. Each of the first and second receiving blocks includes a low noise amplifier, a mixer, a filter and a variable gain amplifier. The first and second receiving blocks respectively include a voltage-controlled oscillator for supplying frequencies to first and second mixers of the first and second receiving blocks.

Description

Receive chip for diversity satellite digital multimedia broadcasting. {RECEIVER CHIP FOR DIVERSITY SATELLITE DIGITAL MULTIMEDIA BROADCASTING}

1 is a block diagram illustrating a pin arrangement of a reception chip for diversity satellite digital multimedia broadcasting according to an embodiment of the present invention.

2 is a block diagram illustrating a pin arrangement of a reception chip for diversity satellite digital multimedia broadcasting according to another embodiment of the present invention.

3 is a block diagram illustrating a configuration of a reception block implemented in a reception chip illustrated in FIG. 1 or 2.

<Explanation of symbols on main parts of the drawings>

100, 200, 300: satellite digital multimedia broadcasting receiving chip

101, 201, 310: first receiving block

102, 202, and 320: second receiving block

The present invention relates to a semiconductor chip for a receiver, and more particularly to a receiver chip for diversity satellite digital multimedia broadcasting.

The diversity receiver refers to a receiver implemented to receive an optimal signal using any one of two antennas by receiving a signal using two receiving antennas at a receiving end.

Diversity technique refers to a technique for overcoming fading by receiving and properly combining a plurality of signals affected by independent padding, and multi-path of a mobile object for digital multimedia broadcasting reception. Diversity technique is used as a countermeasure against fading.

However, if two digital multimedia broadcasting receiver chips are used to implement the conventional diversity scheme, the overall size of the semiconductor chip of the receiver for receiving digital multimedia broadcasting increases and the number of processes increases, thereby making the receiver optimal. There are certain limits to the performance.

An object of the present invention for solving the above problems is to implement the first receiving block and the second receiving block in one chip, the arrangement of the external pins to minimize the interference between the two receiving blocks implemented in one chip We want to provide a structure.

The reception chip for diversity satellite digital multimedia broadcasting according to the present invention for solving the above problems includes a first reception block and a reception chip including a first reception block and a second reception block that is isolated from the first reception block. Packaged therein, an input / output terminal of the first receiving block is connected to an external pin of one surface of the receiving chip, and an input / output terminal of the second receiving block is connected to an external pin of a surface opposite to the receiving chip one surface. A source terminal or a control terminal of the first or second receiving block is connected to an external pin of at least one side of the chip or the other surface, and each of the first and second receiving blocks is a low noise amplifier or mixer. And a voltage controlled oscillator for supplying frequencies to the first and second mixers of the first and second receive blocks, the filter including a filter and a variable gain amplifier. The features.

Here, it is preferable that the package type of the receiving chip is 5ⅹ5 mm 2 32-pin quad flat-pack no-lead (QFN).

Herein, the input / output terminals of the first receiving block include (+) terminal for I-channel (In-phase plus), (-) terminal for I-channel (In-phase minus), and Q-channel (Quadrature-phase plus). (+) Terminal and (-) terminal for Q-channel (Quadrature-phase plus), wherein the input and output terminals of the second receiving block are (+) terminal for I-channel and (-) terminal for I-channel It is preferable to include the (+) terminal for the Q-channel and the (-) terminal for the Q-channel.

Here, the source terminal preferably includes a voltage terminal for supplying a voltage to the receiving chip, a frequency terminal for receiving a clock, and a ground terminal for grounding.

Here, the control terminal preferably includes an I2C frequency terminal for receiving a frequency for I2C (Inter IC) and an I2C data terminal for transmitting and receiving I2C data.

In addition, the receiving chip for diversity satellite digital multimedia broadcasting according to the present invention is packaged in one receiving chip including a first receiving block and a second receiving block isolated with the first receiving block, and an external pin on one surface of the receiving chip. Is connected to an input / output terminal of the first receiving block, and an external pin of a surface perpendicular to one surface of the receiving chip is connected to the input / output terminal of the second receiving block, and an external pin of at least one surface of the receiving chip or the other surface of the receiving chip. A source terminal or a control terminal of the first or second receiving block is connected to each of the first and second receiving blocks, each of which includes a low noise amplifier, a mixer, a filter, and a variable gain amplifier; And a voltage controlled oscillator for supplying frequencies to the first and second mixers of the block.

Here, it is preferable that the package type of the receiving chip is 5ⅹ5 mm 2 32-pin quad flat-pack no-lead (QFN).

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a pin arrangement of a reception chip for diversity satellite digital multimedia broadcasting according to an embodiment of the present invention.

As shown, the receiving chip 100 includes a first receiving block 101 and a second receiving block 102, one surface 120, a surface 130 facing one surface, and the other surface 110, 140. .

The first receiving block 101 implements a receiving circuit for satellite digital multimedia broadcasting and constitutes an independent receiving path.

Here, the first receiving block 101 includes a low noise amplifier, a mixer, and a variable gain amplifier, and a circuit configuration will be described with reference to FIG. 3.

In the same structure as the first receiving block 101, the second receiving block 102 is implemented with a receiving circuit for satellite digital multimedia broadcasting and constitutes an independent receiving path.

The first reception block 101 and the second reception block 102 described above have a diversity function, have two different reception paths, and are implemented as one chip.

Since the first receiving block 101 and the second receiving block 102 are integrated on one chip, interference may occur between circuits, and each block may be optimally isolated to prevent and eliminate such interference. do.

That is, one of the structures that can be optimally isolated is an arrangement of external pins. Pins are provided on the outside of the receiving chip 100 connected between the signal input / output portion of the first receiving block 101 and the second receiving block 102 and an external circuit.

The input / output terminal of the first receiving block 101 through which the signal of the first receiving block 101 is input / output is connected to an external pin disposed on one surface 120 of the receiving chip 100.

Here, the input / output terminal of the first receiving block 101 includes an I-channel (+) terminal, an I-channel (-) terminal, a Q-channel (+) terminal and a Q-channel (-) terminal. do.

In addition, an input / output terminal of the second receiving block 102 to which the signal of the second receiving block 102 is input / output is connected to an external pin disposed on a surface 130 opposite to one surface 120 of the receiving chip 100. .

Here, the input / output terminal of the second receiving block 102 includes an I-channel (+) terminal, an I-channel (-) terminal, a Q-channel (+) terminal, and a Q-channel (-) terminal. Done.

Here, the external pin of the surface 130 that is opposite to the outer surface of one surface 120 to which the input and output terminals of the first receiving block 101 is connected and the one surface 120 to which the input and output terminal of the second receiving block 102 is connected. By arranging them so as to face each other, it becomes possible to minimize interference between independently configured receiving circuits or between external pins.

In addition, a source terminal for applying a source to the first receiving block 101 and the second receiving block 102 of the receiving chip 100, the first receiving block 101, and the second receiving block 102. A control terminal for the control is included.

The source terminal includes a power terminal (not shown) for supplying a voltage to the receiving chip 100, a frequency terminal (not shown) for receiving a clock signal, a ground terminal (not shown) for grounding, and the like.

The control terminal includes an I2C frequency terminal (not shown) for supplying a frequency for I2C to the receiving chip 100 and an I2C data terminal (not shown) for transmitting and receiving I2C data.

The source terminal (not shown) and the control terminal (not shown) described above are connected to one or more external pins of one surface 120 or the other surfaces 110, 130, and 140 of the receiving chip 100.

Due to such a structure, external pin-to-pin interference does not occur in the application of a satellite digital multimedia broadcasting receiver chip having a diversity function, thereby improving the reception performance of the receiver chip as well as the diversity function.

2 is a block diagram illustrating a pin arrangement of a reception chip for diversity satellite digital multimedia broadcasting according to another embodiment of the present invention.

As illustrated, the receiving chip 200 may include the first receiving block 201 and the second receiving block 202, one surface 220, and a surface 230 and the other surface 210 and 240 opposite to one surface at right angles. Include.

The first receiving block 201 and the second receiving block 202 are implemented with a receiving circuit for satellite digital multimedia broadcasting, and each constitutes an independent receiving path.

As in the exemplary embodiment illustrated in FIG. 1, the first receiving block 201 and the second receiving block 202 are implemented as one semiconductor chip having a diversity function.

The input / output terminal through which the signal of the first receiving block 201 is input / output is connected to an external pin arranged on one surface 220 of the receiving chip 200.

The input / output terminal through which the signal of the second receiving block 202 is input / output is connected to an external pin arranged on one surface of the surfaces 210 and 230 perpendicular to the one surface 220 of the receiving chip 200. This part has a structure different from that of the embodiment shown in FIG.

In addition, a source terminal for applying a source to the first receiving block 201 and the second receiving block 202 of the receiving chip 200, the first receiving block 201, and the second receiving block 202. A control terminal for the control is included.

The source terminal (not shown) and the control terminal (not shown) described above are connected to at least one external pin of one surface 220 or the other surface 210, 230, and 240 of the receiving chip 200.

The receiving chip according to the present invention shown in Figs. 1 and 2 is implemented with 5ⅹ5mm2 32-pin Quad Flat-pack No-lead (QFN).

3 is a block diagram illustrating a reception chip in which two reception blocks for performing a diversity function according to the present invention are implemented on one chip.

As shown, the reception chip 300 implementing two reception blocks having a diversity function on one chip includes a first reception block 310, a second reception block 320, and a phase locked loop. A PLL) 331 and a Local Oscillator (LO) 332.

Signals In1 and In2 input through the antenna are satellite DMB frequency band signals and generally mean 2605 MHz to 2655 MHz frequency bands.

The first receive block 310 includes a low-noise amplifier (LNA) 311, a mixer 312, a low-pass filter (LPF) 313, and an LNA 314. It includes.

The second receiving block 320 includes the LNA 321, the mixer 322, the LPF 323, and the LNA 324, and preferably has the same structure as the first receiving block 310 and has a symmetrical structure. .

The LNA 311 of the first receiving block 310 amplifies the signal while suppressing amplification of the weak signal IN1 received from the satellite antenna to noise to the mixer 312 of the first receiving block 310. Pass the signal.

The PLL 331 allows the output frequency of the LO 332 to be fixed at a constant frequency without shaking, and precisely adjusts the voltage of the voltage control oscillator (VCO) used in the LO 332 to adjust the LO ( The output frequency of 332) is moved to a desired frequency and fixed.

In addition, the PPL 331 is composed of a frequency combiner (not shown) and a VCO (not shown) and the VCO (not shown) may handle the DMB-S frequency range.

Here, the combiner is composed of a 20-bit sigma-delta fractional-N architecture and has a good noise characteristic according to fast switching, ultra high resolution frequency, and broadband.

The LO 332 generates a frequency for oscillating a frequency for converting the satellite signal into base-band and supplying the mixing unit 312 and 322.

The mixer 312 of the first receiving block 310 is implemented as a down-converter mixer, and basebands the satellite frequency input by mixing the signal amplified by the LNA 311 and the frequency of the LO 332. Change to a frequency signal.

The LPF 313 of the first receiving block 310 selectively filters signals of a desired frequency band among the frequency signals output from the mixer 312.

The LNA 314 of the first receiving block 310 may be configured as a programmable gain amplifier (PGA) or a variable gain amplifier (VGA).

The configuration and operation of the second receiving block 320 is also the same as the first receiving block 310.

Selecting or combining one of the baseband signals output through the two receiving blocks will be omitted in the present invention.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

According to the configuration of the present invention described above, connecting the connection terminal of the first receiving block and the second receiving block to the external circuit included in the application of the diversity scheme to the satellite digital multimedia broadcasting receiving chip to the interference generated from the external pins It has a decreasing effect.

Claims (7)

Packaged in one receiving chip including a first receiving block (block) and the second receiving block isolated (Isolated) with the first receiving block, An input / output terminal of the first receiving block is connected to an external pin of one surface of the receiving chip, an input / output terminal of the second receiving block is connected to an external pin of a surface opposite to the receiving chip one surface, A source terminal or a control terminal of the first or second receiving block is connected to an external pin of at least one surface of one side or the other side of the receiving chip, Each of the first and second receive blocks includes a low noise amplifier, a mixer, a filter, and a variable gain amplifier, and includes a voltage controlled oscillator for supplying frequencies to the first and second mixers of the first and second receive blocks. A receiving chip for diversity satellite digital multimedia broadcasting. The method of claim 1, The receiving chip has a package type of 5ⅹ5mm2 32-pin Quad Flat-pack No-lead (QFN), diversity satellite digital multimedia broadcasting receiver chip. The method of claim 1, The input and output terminals of the first receiving block include (+) terminal for I-channel (In-phase plus), (-) terminal for I-channel (In-phase minus), and Q-channel (Quadrature-phase plus) (+) Terminal and (-) terminal for Q-channel (Quadrature-phase plus), and the input / output terminal of the second receiving block includes (+) terminal for I-channel and (-) terminal for I-channel, Q A receiving chip for diversity satellite digital multimedia broadcasting comprising a (+) terminal for a channel and a (-) terminal for a Q-channel. The method of claim 1, The source terminal comprises a voltage terminal for supplying voltage to the receiving chip, a frequency terminal for receiving a clock, and a ground terminal for grounding, diversity satellite digital multimedia broadcasting receiving chip. The method of claim 1, The control terminal comprises a I2C frequency terminal for receiving a frequency for I2C (Inter IC) and I2C data terminal for transmitting and receiving I2C data, diversity satellite digital multimedia broadcasting receiving chip. Packaged in one receiving chip including a first receiving block and a second receiving block isolated with the first receiving block, An input / output terminal of the first receiving block is connected to an external pin of one surface of the receiving chip, and an input / output terminal of the second receiving block is connected to an external pin of a surface perpendicular to one surface of the receiving chip; A source terminal or a control terminal of the first or second receiving block is connected to an external pin of at least one surface of one side or the other side of the receiving chip, Each of the first and second receive blocks includes a low noise amplifier, a mixer, a filter, and a variable gain amplifier, and includes a voltage controlled oscillator for supplying frequencies to the first and second mixers of the first and second receive blocks. A receiving chip for diversity satellite digital multimedia broadcasting. The method of claim 6, The receiving chip has a package type of 5ⅹ5mm2 32-pin Quad Flat-pack No-lead (QFN), diversity satellite digital multimedia broadcasting receiver chip.

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