KR20060114485A - Semiconductor memory device having bit line over driving scheme - Google Patents

Abstract

A semiconductor memory device having a bit line over driving scheme is provided to improve operation characteristics of the semiconductor memory device, by preventing power noise of a core voltage line. A normal driver drives a bit line sense amplifier pull-up voltage line with a core voltage in response to a voltage line driving control signal. An over driver(p2) transfers a power supply voltage to the normal driver in response to an over driving pulse. A switching unit(p1) controls the connection of the over driver and a core voltage port in response to the inversion signal of the over driving pulse.

Description

Semiconductor memory device with bit line overdriving scheme TECHNICAL FIELD

1 is a diagram illustrating a configuration of a DRAM core employing an overdriving scheme.

2 is a diagram simulating the operation waveform of the circuit of FIG.

3 is a timing diagram showing waveforms of main signals of the circuit of FIG.

4 is a diagram schematically illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

p1: switching PMOS transistor

p2: over-driver PMOS transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to bit line overdriving control of semiconductor memory devices.

As the continuous scaling down of the line width and the cell size constituting the semiconductor memory chip proceeds, the voltage reduction of the power supply voltage is accelerated, and accordingly, a design technique for satisfying the performance required in a low voltage environment is required.

Currently, most semiconductor memory chips are provided with an internal voltage generator circuit for generating an internal voltage by receiving an external voltage (power supply voltage) to supply a voltage necessary for the operation of the chip internal circuit. In particular, in the case of a memory device using a bit line sense amplifier such as DRAM, a core voltage VCORE is used to detect cell data.

When the word line selected by the row address is activated, data of a plurality of memory cells connected to the word line is transferred to the bit line, and the bit line sense amplifier senses and amplifies the voltage difference between the pair of bit lines. Thousands of these bit line sense amplifiers operate at a time, consuming a large amount of current from the core voltage stage (VCORE) used to drive the pull-up power line (commonly referred to as the RTO line) of the bit line sense amplifier. However, in the trend of lowering the operating voltage, the core voltage VCORE must also be relatively low, and it is difficult to amplify data of many cells in a short time by using the core voltage VCORE.

In order to solve this problem, the RTO line of the bit line sense amplifier is initially higher than the core voltage VCORE for a predetermined time (typically the power supply voltage) at the beginning of operation of the bit line sense amplifier (just after the charge sharing between the memory cell and the bit line). (VDD), a bitline sense amplifier overdriving scheme is adopted.

1 is a diagram illustrating a configuration of a DRAM core employing an overdriving scheme.

Referring to FIG. 1, the DRAM core has a bit line sense amplifier 30, an upper bit line separator 10 and a lower bit line separator 50, and bit line equalization / regardless of whether over driving is adopted. The precharge unit 20, the column selector 40, and the bit line sense amplifier power line driver 60 are disposed.

Here, the upper bit line separation unit 10 is for separating / connecting the upper memory cell array and the sensing amplifier 30 in response to the upper separation signal BISH, and the lower bit line separation unit 50 is a lower separation signal. In order to disconnect / connect the lower memory cell array and the sense amplifier 30 in response to (BISL).

When the enable signal is activated and the SB power line and the RTO power line are driven at a predetermined voltage level, the bit line detection amplifier 30 has a minute voltage difference between the bit line pairs BL and BLB. The voltage difference is sensed and one is amplified to ground voltage VSS and one to core voltage VCORE.

In addition, the bit line equalizer / precharge unit 20 bits the bit line pairs BL and BLB in response to the bit line equalization signal BLEQ after completing the sensing / amplification and restoring process for the bit line. It is for precharging to the line precharge voltage VBLP-usually VCORE / 2.

When the read command is applied, the column selector 40 transfers the data sensed / amplified by the sense amplifier 30 to the segment data buses SIO and SIOB in response to the column select signal YI.

Meanwhile, the bit line sense amplifier power line driver 60 may include a first normal driver transistor M2 for driving the RTO power line with a voltage applied to the core voltage terminal VCORE in response to the first power line driving control signal SAP. ), A second normal driver transistor M3 for driving the SB power line with the ground voltage VSS in response to the second power line driving control signal SAN, and an overdriving signal OVD generated by receiving an active command. Is applied to the over-driving pulse generator 64 for generating an over-driving pulse SAOVDP-over-driver control signal, and the core voltage terminal VCORE in response to the over-driving pulse SAOVDP. The over driver transistor M1 and the RTO power line and the SB power line of the bit line sense amplifier 30 in response to the bit line equalization signal BLEQ are connected to the bit line precharge voltage VBLP. Bit lines for precharging a sense amplifier with a power supply line equalizing / free primary portion 62.

Here, the case where the over driving pulse SAOVDP is defined as a high active pulse and the over driver transistor M1 is implemented as an NMOS transistor is illustrated. However, a PMOS transistor more advantageous for pull-up driving may be used.

FIG. 2 is a simulation diagram of an operation waveform of the circuit of FIG. 1, and FIG. 3 is a timing diagram showing a waveform of a main signal of the circuit of FIG. 1. Referring to this, the operation of the circuit of FIG. Take a look.

First, an active command is applied to activate a word line, and data stored in a cell is induced in the bit line pair BL and BLB by charge sharing, respectively, and after a predetermined time, the first and second power line driving control signals SAP , SAN) is activated to a logic level high. Soon, the overdriving pulse SAOVDP is activated to a logic level high, thereby overdriving the RTO power line. That is, when both of the first and second power line driving control signals SAP and SAN and the overdriving pulse SAOVDP are activated at logic level high, the transistors M1, M2, and M3 are all turned on to supply the RTO power line with the power supply voltage (VDD). ) And the SB power line to ground voltage (VSS).

Thereafter, after a predetermined time, the RTO power line is turned on until the overdrive pulse SAOVDP is deactivated to a logic level low until the first and second power line driving control signals SAP and SAN are deactivated to a logic level low. VCORE).

The bit line over-driving method is called a blind method, and the core voltage terminal VCORE and the power supply voltage terminal VDD are short-circuited during the pulse period of the over-driving pulse SAOVDP.

In this case, as the power supply voltage terminal VDD and the core voltage terminal VCORE are short-circuited, current flows from the power supply voltage terminal VDD to the core voltage terminal VCORE, thereby making the potential of the core voltage VCORE unstable. The result is power noise.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor memory device capable of preventing the generation of power noise due to bit line overdriving.

According to an aspect of the present invention for achieving the above technical problem, a normal driver for driving the bit line sense amplifier pull-up power line to the core voltage in response to the power line driving control signal; An over driver for transmitting a power supply voltage to the normal driver in response to an over driving pulse; And switching means for controlling the connection of the over driver and the core voltage terminal in response to the inversion signal of the overdriving pulse.

In the present invention, power noise is prevented by separating the power supply voltage terminal VDD and the core voltage terminal VCORE without shorting during the overdriving period. To this end, in the present invention, a switch controlled by an overdriving pulse is additionally disposed between the core voltage terminal VCORE and the over driver, and the switch is turned off in the overdriving period so that the power supply voltage terminal VDD and the core voltage terminal VCORE are turned off. To be separated.

Hereinafter, preferred embodiments of the present invention will be introduced so that those skilled in the art can more easily implement the present invention.

4 is a diagram schematically illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4, a semiconductor memory device according to the present exemplary embodiment includes a normal driver PMOS transistor for driving a bit line sense amplifier pull-up power line to a core voltage CORE in response to a power line driving control signal SAN. And an over-driver PMOS transistor (p2) for transferring the power supply voltage (VDD) to the normal driver PMOS transistor in response to an overdriving pulse (saovdp) passing through one inverter, and an over-pass through two inverters. And a switching PMOS transistor p1 for controlling the connection of the over driver PMOS transistor and the core voltage terminal VCORE in response to the driving pulse saovdp.

That is, the present embodiment additionally arranges the switching PMOS transistor p1 for separating the power supply voltage terminal VDD and the core voltage terminal VCORE during the overdriving period as compared with the prior art.

When the switching PMOS transistor p1 is disposed as described above, when the overdriving pulse saovdp is activated at a logic level high, the over driver PMOS transistor p2 is turned on to perform overdriving. At this time, the normal driver PMOS transistor is also turned on.

Conventionally, when the two transistors are turned on at the same time, the power supply voltage terminal VDD and the core voltage terminal VCORE are short-circuited. However, in this embodiment, since the switching PMOS transistor p1 is turned off, the power supply voltage terminal ( VDD) and the core voltage terminal VCORE are not shorted.

Therefore, by applying the present embodiment, it is possible to block the current inflow from the power supply voltage terminal VDD to the core voltage terminal VCORE in the overdriving period, thereby preventing power noise of the core voltage VCORE line. have.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, in the above-described embodiment, the case where the PMOS transistor is used as the RTO line driver transistor and the switching transistor has been described as an example, but the present invention is also applied to the case where the transistor is replaced with another type of transistor such as an NMOS transistor. In addition, the inverter and the like exemplified in the above-described embodiments may or may not be additionally used depending on the polarity of the input signal.

The present invention described above has an effect of preventing power noise of the core voltage VCORE line, and thus, an effect of improving the operating characteristics of the semiconductor memory device can be expected.

Claims (1)

A normal driver for driving the bit line sense amplifier pull-up power line to a core voltage in response to a power line driving control signal; An over driver for transmitting a power supply voltage to the normal driver in response to an over driving pulse; And Switching means for controlling the connection of the over driver and the core voltage terminal in response to an inversion signal of the overdriving pulse; A semiconductor memory device having a.

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